Searched refs:MISCREG_SCTLR_EL1 (Results 1 - 10 of 10) sorted by relevance

/gem5/src/arch/arm/
H A Dutility.cc363 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
365 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
827 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa;
829 return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).sa0;
H A Dmiscregs.hh466 MISCREG_SCTLR_EL1, enumerator in enum:ArmISA::MiscRegIndex
H A Dmiscregs.cc1163 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1170 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1175 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
1822 return MISCREG_SCTLR_EL1;
3975 InitReg(MISCREG_SCTLR_EL1)
H A Dtable_walker.cc269 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
274 currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1);
H A Dtlb.cc1321 sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
H A Dfaults.cc455 const SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
H A Disa.cc308 // also MISCREG_SCTLR_EL1 (by mapping)
1838 case MISCREG_SCTLR_EL1:
/gem5/src/arch/arm/insts/
H A Dmisc64.cc168 case MISCREG_SCTLR_EL1:
H A Dstatic_inst.cc780 SCTLR sctlr = ((SCTLR)tc->readMiscReg(MISCREG_SCTLR_EL1));
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc427 { "sctlr_el1", MISCREG_SCTLR_EL1 },

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