Searched refs:MISCREG_SCTLR (Results 1 - 8 of 8) sorted by relevance

/gem5/src/arch/arm/
H A Dutility.cc560 case MISCREG_SCTLR:
672 case MISCREG_SCTLR:
H A Dmiscregs.hh172 MISCREG_SCTLR, enumerator in enum:ArmISA::MiscRegIndex
H A Dfaults.cc314 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
498 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
H A Dtlb.cc1368 sctlr = tc->readMiscReg(snsBankedIndex(MISCREG_SCTLR, tc,
H A Disa.cc1054 case MISCREG_SCTLR:
H A Dmiscregs.cc230 return MISCREG_SCTLR;
3173 InitReg(MISCREG_SCTLR)
H A Dtable_walker.cc294 MISCREG_SCTLR, currState->tc, !currState->isSecure));
/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc922 MISCREG_SCTLR, tc, !inSecureState(tc));
1038 ((SCTLR)tc->readMiscReg(MISCREG_SCTLR)).itd;

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