Searched refs:MISCREG_ICH_LR15_EL2 (Results 1 - 4 of 4) sorted by relevance

/gem5/src/arch/arm/
H A Dmiscregs.hh755 MISCREG_ICH_LR15_EL2, enumerator in enum:ArmISA::MiscRegIndex
H A Disa.cc742 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
2079 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
H A Dmiscregs.cc2557 return MISCREG_ICH_LR15_EL2;
4767 InitReg(MISCREG_ICH_LR15_EL2)
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc715 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2:
1498 case MISCREG_ICH_LR0_EL2 ... MISCREG_ICH_LR15_EL2: { // AArch64

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