Searched refs:MISCREG_HSCTLR (Results 1 - 7 of 7) sorted by relevance

/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc907 setend_disabled = ((SCTLR)tc->readMiscRegNoEffect(MISCREG_HSCTLR)).sed;
1037 ((SCTLR)tc->readMiscReg(MISCREG_HSCTLR)).itd :
/gem5/src/arch/arm/
H A Dmiscregs.hh182 MISCREG_HSCTLR, enumerator in enum:ArmISA::MiscRegIndex
H A Disa.cc306 miscRegs[MISCREG_HSCTLR] = 0x30c50830;
1853 case MISCREG_HSCTLR:
H A Dmiscregs.cc249 return MISCREG_HSCTLR;
3207 InitReg(MISCREG_HSCTLR)
4000 .mapsTo(MISCREG_HSCTLR);
H A Dtlb.cc1400 sctlr = tc->readMiscReg(MISCREG_HSCTLR);
H A Dfaults.cc530 SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc167 { "hsctlr", MISCREG_HSCTLR },

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