| /gem5/src/arch/mips/ |
| H A D | interrupts.cc | 40 #include "debug/Interrupt.hh"
61 DPRINTF(Interrupt, "Interrupt %d posted\n", int_num);
79 DPRINTF(Interrupt, "Interrupt %d cleared\n", int_num);
97 DPRINTF(Interrupt, "Interrupts all cleared\n");
139 DPRINTF(Interrupt, "Interrupt! IM[7:0]=%d IP[7:0]=%d \n",
167 DPRINTF(Interrupt, "Interrupts OnCpuTimerINterrupt(tc) == true\n");
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| /gem5/src/arch/riscv/ |
| H A D | interrupts.hh | 41 #include "debug/Interrupt.hh"
110 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
117 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
124 DPRINTF(Interrupt, "All interrupts cleared\n");
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| /gem5/src/arch/alpha/ |
| H A D | interrupts.hh | 43 #include "debug/Interrupt.hh"
86 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
101 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
117 DPRINTF(Interrupt, "Interrupts all cleared\n");
205 DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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| /gem5/src/cpu/minor/ |
| H A D | pipe_data.cc | 68 case BranchData::Interrupt:
69 os << "Interrupt";
101 case Interrupt:
121 case Interrupt:
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| H A D | pipe_data.hh | 95 Interrupt, enumerator in enum:Minor::BranchData::Reason
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| H A D | fetch2.cc | 138 case BranchData::Interrupt:
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| H A D | execute.cc | 439 updateBranchData(thread_id, BranchData::Interrupt,
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| /gem5/src/arch/arm/ |
| H A D | interrupts.hh | 52 #include "debug/Interrupt.hh"
92 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
107 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
122 DPRINTF(Interrupt, "Interrupts all cleared\n");
212 * @param interrupt Interrupt type to check the state of.
219 panic("Interrupt number out of range.\n");
246 return std::make_shared<Interrupt>();
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| H A D | faults.hh | 520 class Interrupt : public ArmFaultVals<Interrupt> class in namespace:ArmISA
620 template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals;
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| H A D | faults.cc | 244 template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals(
1431 Interrupt::routeToMonitor(ThreadContext *tc) const
1443 Interrupt::routeToHyp(ThreadContext *tc) const
1457 Interrupt::abortDisable(ThreadContext *tc)
1625 template class ArmFaultVals<Interrupt>;
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| /gem5/src/arch/sparc/ |
| H A D | interrupts.hh | 39 #include "debug/Interrupt.hh"
104 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
115 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
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| /gem5/src/dev/arm/ |
| H A D | gic_v2.cc | 50 #include "debug/Interrupt.hh"
93 "Post Interrupt to CPU");
98 DPRINTF(Interrupt, "cpuEnabled[0]=%d cpuEnabled[1]=%d\n", cpuEnabled(0),
216 DPRINTF(Interrupt, "Reading interrupt priority at int# %#x \n",
330 "Interrupt %d active but no CPU generated it?\n",
365 DPRINTF(Interrupt,
538 DPRINTF(Interrupt, "Distributor enable flag set to = %d\n", enabled);
618 DPRINTF(Interrupt, "CPU %d done handling intr IAR = %d from cpu %d\n",
676 // Interrupt requesting cpu only
810 DPRINTF(Interrupt, "Clea
[all...] |
| H A D | gic_v3.cc | 47 #include "debug/Interrupt.hh"
178 DPRINTF(Interrupt, "Gicv3::sendInt(): received SPI %d\n", int_id);
194 DPRINTF(Interrupt, "Gicv3::sendPPInt(): received PPI %d cpuTarget %#x\n",
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| /gem5/src/dev/sparc/ |
| H A D | iob.hh | 107 Interrupt, enumerator in enum:Iob::Type
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| /gem5/src/arch/arm/kvm/ |
| H A D | gic.cc | 47 #include "debug/Interrupt.hh"
242 DPRINTF(Interrupt, "Set SPI %d\n", num);
252 DPRINTF(Interrupt, "Clear SPI %d\n", num);
261 DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
271 DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
346 // Interrupt Priority Mask Register (PMR), and
422 // the values read for the Interrupt Priority Mask Register (PMR)
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