Searched refs:vector (Results 251 - 275 of 763) sorted by relevance

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/gem5/src/mem/cache/tags/
H A Dcompressed_tags.cc55 blks = std::vector<CompressionBlk>(numBlocks);
56 superBlks = std::vector<SuperBlk>(numSectors);
106 std::vector<CacheBlk*>& evict_blks) const
109 const std::vector<ReplaceableEntry*> superblock_entries =
/gem5/src/mem/ruby/system/
H A DRubyPort.hh192 std::vector<MemSlavePort *> slave_ports;
213 typedef std::vector<MemSlavePort *>::iterator CpuPortIter;
214 std::vector<PioMasterPort *> master_ports;
220 std::vector<MemSlavePort *> retryList;
/gem5/src/arch/x86/
H A Dfaults.hh58 uint8_t vector; member in class:X86ISA::X86FaultBase
64 vector(_vector), errorCode(_errorCode)
95 * Get the vector of an interrupt.
97 * @return interrupt vector number.
99 virtual uint8_t getVector() const { return vector; }
108 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
109 : X86FaultBase(name, mnem, vector, _errorCode)
119 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1)
120 : X86FaultBase(name, mnem, vector, _errorCode)
132 const uint8_t vector, uint64_
107 X86Fault(const char * name, const char * mnem, const uint8_t vector, uint64_t _errorCode = (uint64_t)-1) argument
118 X86Trap(const char * name, const char * mnem, const uint8_t vector, uint64_t _errorCode = (uint64_t)-1) argument
131 X86Abort(const char * name, const char * mnem, const uint8_t vector, uint64_t _errorCode = (uint64_t)-1) argument
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H A Dstacktrace.hh66 std::vector<Addr> stack;
91 const std::vector<Addr> &getstack() const { return stack; }
/gem5/src/sim/
H A Dsystem.hh53 #include <vector>
200 std::vector<ThreadContext *> threadContexts;
229 std::vector<ObjectFile *> kernelExtras;
318 std::vector<bool> activeCpus;
325 std::vector<MasterInfo> masters;
448 for (std::vector<bool>::iterator i = activeCpus.begin();
554 std::vector<BaseRemoteGDB *> remoteGDB;
616 static std::vector<System *> systemList;
635 std::vector<RedirectPath*> redirectPaths;
H A Ddrain.hh45 #include <vector>
172 std::vector<Drainable *> _allDrainable;
/gem5/src/gpu-compute/
H A Dgpu_tlb.hh43 #include <vector>
162 std::vector<TlbEntry> tlb;
169 std::vector<EntryList> freeList;
178 std::vector<EntryList> entryList;
307 std::vector<CpuSidePort*> cpuSidePort;
309 std::vector<MemSidePort*> memSidePort;
348 std::vector<SlavePort*>ports;
352 std::vector<int> reqCnt;
437 std::vector<unsigned int> localTLBAccesses;
/gem5/ext/systemc/src/sysc/kernel/
H A Dsc_simcontext.h112 const std::vector<sc_event*>& sc_get_top_level_events(
114 const std::vector<sc_object*>& sc_get_top_level_objects(
153 friend const std::vector<sc_event*>& sc_get_top_level_events(
155 friend const std::vector<sc_object*>& sc_get_top_level_objects(
186 std::vector<sc_thread_handle>& get_active_invokers();
257 const ::std::vector<sc_object*>& get_child_objects() const;
280 const ::std::vector<sc_event*>& get_child_events_internal() const;
281 const ::std::vector<sc_object*>& get_child_objects_internal() const;
331 std::vector<sc_thread_handle> m_active_invokers;
333 std::vector<sc_even
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H A Dsc_object_manager.h34 #include <vector>
66 typedef std::vector<sc_object*> object_vector_t;
/gem5/src/dev/sparc/
H A Diob.cc69 intMan[x].vector = 0;
99 uint64_t data = intMan[index].cpu << 8 | intMan[index].vector << 0;
197 intMan[index].vector = bits(data,5,0);
199 intMan[index].cpu, intMan[index].vector);
223 int vector; local
228 vector = bits(data,5,0);
229 generateIpi(type,cpu_id, vector);
272 devid, intMan[devid].cpu, intMan[devid].vector);
273 ic->post(intMan[devid].cpu, SparcISA::IT_INT_VEC, intMan[devid].vector);
278 Iob::generateIpi(Type type, int cpu_id, int vector) argument
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/gem5/ext/dsent/
H A DDSENT.cc39 const vector<String>& start_net_names =
98 const vector<String>& start_net_names =
126 const vector<String>* parameter_names = ms_model->getParameterNames();
128 for(vector<String>::const_iterator it = parameter_names->begin();
144 const vector<String>* property_names = ms_model->getPropertyNames();
146 for(vector<String>::const_iterator it = property_names->begin();
181 vector<String> type_split = query_str_.splitByString(Model::TYPE_SEPARATOR);
185 vector<String> detail_split =
191 vector<String> subfield_split =
243 void processQuery(const vector<Strin
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/gem5/src/mem/
H A Dphysical.cc75 const vector<AbstractMemory*>& _memories,
113 vector<AbstractMemory*> unmapped_mems{m};
123 vector<AddrRange> intlv_ranges;
124 vector<AbstractMemory*> curr_memories;
156 vector<AbstractMemory*> single_memory{r.second};
186 const vector<AbstractMemory*>& _memories,
247 vector<AddrRange> intlv_ranges;
299 vector<Addr> lal_addr;
300 vector<ContextID> lal_cid;
376 vector<Add
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/gem5/src/dev/arm/
H A Dsmmu_v3_caches.hh48 #include <vector>
142 typedef std::vector<Entry> Set;
143 std::vector<Set> sets;
187 typedef std::vector<Entry> Set;
188 std::vector<Set> sets;
227 typedef std::vector<Entry> Set;
228 std::vector<Set> sets;
274 typedef std::vector<Entry> Set;
275 std::vector<Set> sets;
340 typedef std::vector<Entr
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/gem5/ext/dsent/model/optical_graph/
H A DOpticalNode.cc35 m_downstream_nodes_ = new vector<OpticalNode*>;
48 vector<OpticalNode*>* OpticalNode::getDownstreamNodes() const
/gem5/src/arch/alpha/
H A Dstacktrace.hh67 std::vector<Addr> stack;
93 const std::vector<Addr> &getstack() const { return stack; }
/gem5/src/arch/arm/
H A Dstacktrace.hh69 std::vector<Addr> stack;
94 const std::vector<Addr> &getstack() const { return stack; }
/gem5/src/arch/mips/
H A Dstacktrace.hh66 std::vector<Addr> stack;
91 const std::vector<Addr> &getstack() const { return stack; }
/gem5/src/arch/arm/kvm/
H A Darm_cpu.hh44 #include <vector>
90 typedef std::vector<uint64_t> RegIndexVector;
/gem5/src/mem/ruby/common/
H A DHistogram.hh33 #include <vector>
64 std::vector<uint64_t> m_data;
H A DSubBlock.hh33 #include <vector>
70 std::vector<uint8_t> m_data;
/gem5/src/mem/ruby/structures/
H A DWireBuffer.hh37 #include <vector>
96 std::vector<MsgPtr> m_message_queue;
/gem5/src/dev/net/
H A Dtcp_iface.hh89 static std::vector<std::pair<NodeInfo, int> > nodes;
93 static std::vector<int> sockRegistry;
/gem5/ext/systemc/src/sysc/communication/
H A Dsc_signal_resolved.h106 std::vector<sc_process_b*> m_proc_vec; // processes writing this signal
107 std::vector<data_type> m_val_vec; // new values written this signal
/gem5/src/mem/ruby/network/garnet2.0/
H A DOutputUnit.hh38 #include <vector>
109 std::vector<OutVcState *> m_outvc_state; // vc state of downstream router
/gem5/src/dev/ps2/
H A Ddevice.cc60 std::vector<uint8_t> buffer(outBuffer.size());
70 std::vector<uint8_t> buffer;

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