Searched refs:vector (Results 201 - 225 of 763) sorted by relevance

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/gem5/ext/dsent/model/electrical/
H A DMatrixArbiter.cc25 #include <vector>
37 using std::vector;
125 vector<String> g_inv_names(number_requests, "");
126 vector<StdCell*> g_invs(number_requests, NULL);
127 vector<String> g_and2_names(number_requests, "");
128 vector<StdCell*> g_and2s(number_requests, NULL);
141 vector<String> w_or2_names(number_states, "");
142 vector<StdCell*> w_or2s(number_states, NULL);
143 vector<String> w_and2_names(number_states, "");
144 vector<StdCel
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H A DSeparableAllocator.cc210 const vector<double>& P_request_vector = LibUtil::castStringVector<double>(P_request.split("[,]"));
211 const vector<double>& act_request_vector = LibUtil::castStringVector<double>(act_request.split("[,]"));
220 vector<double> P_int_request_vector(number_requesters * number_resources, 0.0);
221 vector<double> act_int_request_vector(number_requesters * number_resources, 0.0);
222 vector<double> P_out_request_vector(number_requesters * number_resources, 0.0);
223 vector<double> act_out_request_vector(number_requesters * number_resources, 0.0);
229 vector<double> P_arb_request_vector(number_resources, 0.0);
230 vector<double> act_arb_request_vector(number_resources, 0.0);
244 const vector<double>& P_arb_out_request_vector = LibUtil::castStringVector<double>(arb->getGenProperties()->get("P(Grant)").split("[,]"));
245 const vector<doubl
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/gem5/src/base/
H A Ddebug.hh37 #include <vector>
55 virtual std::vector<Flag *> kids() { return std::vector<Flag*>(); }
90 std::vector<Flag *> _kids;
119 std::vector<Flag *> kids() { return _kids; }
/gem5/src/mem/ruby/structures/
H A DPrefetcher.hh135 bool accessUnitFilter(std::vector<Addr>& filter_table,
149 std::vector<PrefetchEntry> m_array;
162 std::vector<Addr> m_unit_filter;
171 std::vector<Addr> m_negative_filter;
180 std::vector<Addr> m_nonunit_filter;
/gem5/src/dev/arm/
H A Dflash_device.hh183 std::vector<uint32_t> unknownPages;
185 std::vector<struct PageMapEntry> locationTable;
187 std::vector<uint32_t> blockValidEntries;
189 std::vector<uint32_t> blockEmptyEntries;
191 /**This vector of queues keeps track of all the callbacks per plane*/
192 std::vector<std::deque<struct CallBackEntry> > planeEventQueue;
/gem5/src/mem/ruby/network/garnet2.0/
H A DRouter.hh38 #include <vector>
89 std::vector<InputUnit *>& get_inputUnit_ref() { return m_input_unit; }
90 std::vector<OutputUnit *>& get_outputUnit_ref() { return m_output_unit; }
124 std::vector<InputUnit *> m_input_unit;
125 std::vector<OutputUnit *> m_output_unit;
H A DGarnetNetwork.hh38 #include <vector>
193 std::vector<VNET_type > m_vnet_type;
194 std::vector<Router *> m_routers; // All Routers in Network
195 std::vector<NetworkLink *> m_networklinks; // All flit links in the network
196 std::vector<CreditLink *> m_creditlinks; // All credit links in the network
197 std::vector<NetworkInterface *> m_nis; // All NI's in Network
/gem5/src/mem/cache/prefetch/
H A Dassociative_set_impl.hh59 const std::vector<ReplaceableEntry*> selected_entries =
84 const std::vector<ReplaceableEntry*> selected_entries =
95 std::vector<Entry *>
98 std::vector<ReplaceableEntry *> selected_entries =
100 std::vector<Entry *> entries(selected_entries.size(), nullptr);
/gem5/src/mem/cache/compressors/
H A Dbdi.hh41 #include <vector>
318 const std::vector<uint64_t> _data;
365 std::vector<uint8_t> bitMask;
370 std::vector<TB> bases;
375 std::vector<TD> deltas;
378 * Add a base to the bases vector.
386 * Add a delta to the deltas vector.
/gem5/src/gpu-compute/
H A Dtlb_coalescer.hh42 #include <vector>
91 typedef std::vector<PacketPtr> coalescedReq;
98 * It contains a vector of coalescedReqs per <tick_index>.
110 typedef std::unordered_map<int64_t, std::vector<coalescedReq>> CoalescingFIFO;
116 * address. Each hash_map entry has a vector of PacketPtr associated
210 std::vector<CpuSidePort*> cpuSidePort;
212 std::vector<MemSidePort*> memSidePort;
H A Dcompute_unit.hh43 #include <vector>
111 std::vector<std::vector<Wavefront*>> readyList;
119 std::vector<std::vector<std::pair<Wavefront*, WAVE_STATUS>>> waveStatusList;
131 std::vector<std::pair<Wavefront*, DISPATCH_STATUS>> dispatchList;
136 std::vector<std::vector<Wavefront*>> wfList;
139 // array of vector register files, one per SIMD
140 std::vector<VectorRegisterFil
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H A Dbrig_object.hh42 #include <vector>
85 std::vector<HsailCode*> kernels;
86 std::vector<HsailCode*> functions;
/gem5/src/cpu/simple/
H A Datomic.hh216 const std::vector<bool>& byte_enable,
221 const std::vector<bool>& byteEnable = std::vector<bool>())
226 const std::vector<bool>& byteEnable = std::vector<bool>())
/gem5/src/cpu/pred/
H A Dmultiperspective_perceptron_tage.hh52 std::vector<unsigned int> tunedHistoryLengths;
100 std::vector<int> pm;
101 std::vector<int8_t> * pgehl;
102 std::vector<int8_t> wp;
107 std::vector<int> gm;
108 std::vector<int8_t> * ggehl;
109 std::vector<int8_t> wg;
116 std::vector<int64_t> historyStack;
177 Addr branch_pc, bool taken, int64_t hist, std::vector<int> & length,
178 std::vector<int8_
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/gem5/src/mem/ruby/common/
H A DWriteMask.hh35 #include <vector>
52 WriteMask(int size, std::vector<bool> & mask)
56 WriteMask(int size, std::vector<bool> &mask,
57 std::vector<std::pair<int, AtomicOpFunctor*> > atomicOp)
67 mMask = std::vector<bool>(mSize, false);
189 std::vector<bool> mMask;
191 std::vector<std::pair<int, AtomicOpFunctor*> > mAtomicOp;
/gem5/ext/dsent/tech/
H A DTechModel.cc75 const vector<String>& available_wire_layer_vector = get("Wire->AvailableLayers").split("[,]");
89 vector<double> stacked_mos_widths_(num_stacks_, uni_stacked_mos_width_);
94 double TechModel::calculateNmosLeakageCurrent(unsigned int num_stacks_, const vector<double>& stacked_mos_widths_, unsigned int input_vector_) const
124 vector<double> stacked_mos_widths_(num_stacks_, uni_stacked_mos_width_);
129 double TechModel::calculatePmosLeakageCurrent(unsigned int num_stacks_, const vector<double>& stacked_mos_widths_, unsigned int input_vector_) const
159 double TechModel::calculateLeakageCurrentFactor(unsigned int num_stacks_, const vector<double>& stacked_mos_widths_, unsigned int input_vector_, double vdd_, double subthreshold_swing_, double dibl_swing_) const
170 std::vector<double> vs(num_stacks_, 0.0);
178 vector<double> ws = stacked_mos_widths_;
190 std::vector<double> a(num_stacks_ - 1, 0);
191 std::vector<doubl
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/gem5/src/mem/ruby/system/
H A DGPUCoalescer.hh248 void completeHitCallback(std::vector<PacketPtr> & mylist, int len);
273 typedef std::unordered_map<Addr, std::vector<RequestDesc>> CoalescingTable;
275 std::vector<Addr> newRequests;
284 std::vector<int> newKernelEnds;
322 std::vector<Stats::Histogram *> m_typeLatencyHist;
327 std::vector<Stats::Histogram *> m_missTypeLatencyHist;
331 std::vector<Stats::Histogram *> m_missMachLatencyHist;
332 std::vector< std::vector<Stats::Histogram *> > m_missTypeMachLatencyHist;
335 std::vector<Stat
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/gem5/ext/dsent/model/
H A DModel.h25 #include <vector>
31 using std::vector;
87 const vector<String>* getParameterNames() const;
92 const vector<String>* getPropertyNames() const;
208 vector<String>* m_parameter_names_;
215 vector<String>* m_property_names_;
/gem5/src/sim/
H A Ddvfs_handler.cc209 std::vector<DomainID> domain_ids;
210 std::vector<PerfLevel> perf_levels;
211 std::vector<Tick> whens;
239 std::vector<DomainID> domain_ids;
240 std::vector<PerfLevel> perf_levels;
241 std::vector<Tick> whens;
H A Dclock_domain.hh100 std::vector<DerivedClockDomain*> children;
106 std::vector<Clocked *> members;
257 const std::vector<Tick> freqOpPoints;
/gem5/src/systemc/tests/systemc/compliance_1666/test233/
H A Dtest233.cpp27 std::vector<sc_object*> children = h.get_child_objects();
54 std::vector<sc_object*> children = h.get_child_objects();
80 std::vector<sc_object*> children = h.get_child_objects();
93 std::vector<sc_object*> children = h.get_child_objects();
106 std::vector<sc_object*> children = h.get_child_objects();
119 std::vector<sc_object*> children = h.get_child_objects();
/gem5/src/cpu/
H A Dexec_context.hh116 /** Reads source vector register operand. */
120 /** Gets destination vector register operand for modification. */
124 /** Sets a destination vector register operand to a value. */
132 /** Reads source vector 8bit operand. */
136 /** Reads source vector 16bit operand. */
140 /** Reads source vector 32bit operand. */
144 /** Reads source vector 64bit operand. */
148 /** Write a lane of the destination vector operand. */
162 /** Reads an element of a vector register. */
166 /** Sets a vector registe
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/gem5/ext/dsent/util/
H A DResult.h26 #include <vector>
34 using std::vector;
99 vector<SubResult*> m_sub_results_;
/gem5/src/arch/x86/bios/
H A Dsmbios.hh47 #include <vector>
99 std::vector<std::string> strings;
211 std::vector<SMBiosStructure *> structures;
/gem5/src/dev/pci/
H A Ddevice.hh53 #include <vector>
106 std::vector<MSIXTable> msix_table;
107 std::vector<MSIXPbaEntry> msix_pba;

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