Searched refs:vector (Results 176 - 200 of 763) sorted by relevance

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/gem5/ext/pybind11/tests/
H A Dlocal_bindings.h28 using LocalVec = std::vector<LocalType>;
29 using LocalVec2 = std::vector<NonLocal2>;
31 using NonLocalVec = std::vector<NonLocalType>;
32 using NonLocalVec2 = std::vector<NonLocal2>;
H A Dtest_opaque_types.cpp12 #include <vector>
18 // bit is just the default `std::vector` allocator).
19 PYBIND11_MAKE_OPAQUE(std::vector<std::string, std::allocator<std::string>>); variable
21 using StringList = std::vector<std::string, std::allocator<std::string>>;
/gem5/src/mem/ruby/network/
H A DBasicRouter.hh34 #include <vector>
/gem5/src/mem/ruby/network/garnet2.0/
H A DInputUnit.hh38 #include <vector>
163 std::vector<VirtualChannel *> m_vcs;
166 std::vector<double> m_num_buffer_writes;
167 std::vector<double> m_num_buffer_reads;
/gem5/src/systemc/core/
H A Dmodule.hh38 #include <vector>
125 void bindPorts(std::vector<const ::sc_core::sc_bind_proxy *> &proxies);
127 std::vector<::sc_core::sc_port_base *> ports;
128 std::vector<::sc_core::sc_export_base *> exports;
/gem5/src/mem/cache/replacement_policies/
H A Dbase.hh43 typedef std::vector<ReplaceableEntry*> ReplacementCandidates;
/gem5/src/mem/cache/tags/indexing_policies/
H A Dset_associative.cc72 std::vector<ReplaceableEntry*>
/gem5/ext/googletest/googletest/src/
H A Dgtest-typed-test.cc48 static std::vector<std::string> SplitIntoTestNames(const char* src) {
49 std::vector<std::string> name_vec;
65 std::vector<std::string> name_vec = SplitIntoTestNames(registered_tests);
70 for (std::vector<std::string>::const_iterator name_it = name_vec.begin();
/gem5/src/arch/mips/
H A Dprocess.hh36 #include <vector>
/gem5/src/arch/power/
H A Dprocess.hh37 #include <vector>
/gem5/src/mem/cache/prefetch/
H A Dslim_ampm.cc42 std::vector<AddrPriority> &addresses)
H A Dtagged.cc48 std::vector<AddrPriority> &addresses)
H A Daccess_map_pattern_matching.hh89 /** vector containing the state of the cachelines in this zone */
90 std::vector<AccessMapState> states;
135 * @param states vector containing the states of three contiguous hot zones
140 inline bool checkCandidate(std::vector<AccessMapState> const &states,
185 std::vector<QueuedPrefetcher::AddrPriority> &addresses);
198 std::vector<AddrPriority> &addresses) override;
/gem5/src/cpu/testers/rubytest/
H A DRubyTester.hh47 #include <vector>
136 std::vector<Cycles> m_last_progress_vector;
140 std::vector<MasterPort*> writePorts;
141 std::vector<MasterPort*> readPorts;
/gem5/src/mem/cache/tags/
H A Dbase_set_assoc.hh54 #include <vector>
81 std::vector<CacheBlk> blks;
170 std::vector<CacheBlk*>& evict_blks) const override
173 const std::vector<ReplaceableEntry*> entries =
/gem5/ext/dsent/libutil/
H A DString.h27 #include <vector>
34 using std::vector;
68 // Split the String into vector of Strings separated by delimiters_
69 vector<String> split(const char* delimiters_) const;
70 vector<String> split(const String* delimiters_, unsigned int num_delimiters_ = 1) const;
71 vector<String> splitByString(const String& delimiters_) const;
187 const vector<T>& vector_, unsigned int start_index_, unsigned int end_index_,
191 // Ensure end_index_ >= start_index_ + 1, or if the vector is empty
194 // If the vector is empty, return empty array
210 template<class T> String vectorToString(const vector<
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/gem5/src/mem/ruby/common/
H A DNetDest.hh33 #include <vector>
82 std::vector<NodeID> getAllDest();
108 std::vector<Set> m_bits; // a vector of bit vectors - i.e. Sets
/gem5/src/sim/
H A Dlinear_solver.cc42 std::vector <double>
46 std::vector < LinearEquation > smatrix = this->matrix;
75 std::vector <double> ret(order, 0.0f);
/gem5/src/mem/ruby/network/simple/
H A DSimpleNetwork.hh33 #include <vector>
86 std::vector<Switch*> m_switches;
87 std::vector<MessageBuffer*> m_int_link_buffers;
/gem5/src/gpu-compute/
H A Dcondition_register_state.hh40 #include <vector>
96 std::vector<VectorMask> c_reg;
98 std::vector<uint8_t> busy;
H A Dexec_stage.hh42 #include <vector>
113 std::vector<std::pair<Wavefront*, DISPATCH_STATUS>> *dispatchList;
114 // flag per vector SIMD unit that is set when there is at least one
115 // WV that has a vector ALU instruction as the oldest in its
117 std::vector<bool> *vectorAluInstAvail;
/gem5/ext/systemc/src/tlm_core/tlm_2/tlm_generic_payload/
H A Dtlm_array.h51 : private std::vector<T>
53 typedef std::vector<T> base_type;
112 std::vector<size_type> m_entries;
H A Dtlm_phase.h25 #include <vector>
38 inline std::vector<const char*>& get_phase_name_vec(){
39 static std::vector<const char*> phase_name_vec(END_RESP+1, (const char*)NULL);
/gem5/src/dev/ps2/
H A Dtypes.hh46 #include <vector>
84 extern const std::vector<uint8_t> ID;
102 extern const std::vector<uint8_t> ID;
/gem5/src/cpu/pred/
H A Dtage_sc_l_8KB.hh75 std::vector<int> gm;
76 std::vector<int8_t> * ggehl;
77 std::vector<int8_t> wg;

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