1/*
2 * Copyright (c) 2014-2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Authors: John Kalamatianos,
34 *          Sooraj Puthoor
35 */
36
37#ifndef __EXEC_STAGE_HH__
38#define __EXEC_STAGE_HH__
39
40#include <string>
41#include <utility>
42#include <vector>
43
44#include "sim/stats.hh"
45
46class ComputeUnit;
47class Wavefront;
48struct ComputeUnitParams;
49
50enum STAT_STATUS
51{
52    IdleExec,
53    BusyExec,
54    PostExec
55};
56
57enum DISPATCH_STATUS
58{
59    EMPTY = 0,
60    FILLED
61};
62
63// Execution stage.
64// Each execution resource executes the
65// wave which is in its dispatch list.
66// The schedule stage is responsible for
67// adding a wave into each execution resource's
68// dispatch list.
69
70class ExecStage
71{
72  public:
73    ExecStage(const ComputeUnitParams* params);
74    ~ExecStage() { }
75    void init(ComputeUnit *cu);
76    void exec();
77
78    std::string name() { return _name; }
79    void regStats();
80    // number of idle cycles
81    Stats::Scalar numCyclesWithNoIssue;
82    // number of busy cycles
83    Stats::Scalar numCyclesWithInstrIssued;
84    // number of cycles (per execution unit) during which at least one
85    // instruction was issued to that unit
86    Stats::Vector numCyclesWithInstrTypeIssued;
87    // number of idle cycles (per execution unit) during which the unit issued
88    // no instruction targeting that unit, even though there is at least one
89    // Wavefront with such an instruction as the oldest
90    Stats::Vector numCyclesWithNoInstrTypeIssued;
91    // SIMDs active per cycle
92    Stats::Distribution spc;
93
94  private:
95    void collectStatistics(enum STAT_STATUS stage, int unitId);
96    void initStatistics();
97    ComputeUnit *computeUnit;
98    uint32_t numSIMDs;
99
100    // Number of memory execution resources;
101    // both global and local memory execution resources in CU
102    uint32_t numMemUnits;
103
104    // List of waves which will be dispatched to
105    // each execution resource. A FILLED implies
106    // dispatch list is non-empty and
107    // execution unit has something to execute
108    // this cycle. Currently, the dispatch list of
109    // an execution resource can hold only one wave because
110    // an execution resource can execute only one wave in a cycle.
111    // dispatchList is used to communicate between schedule
112    // and exec stage
113    std::vector<std::pair<Wavefront*, DISPATCH_STATUS>> *dispatchList;
114    // flag per vector SIMD unit that is set when there is at least one
115    // WV that has a vector ALU instruction as the oldest in its
116    // Instruction Buffer
117    std::vector<bool> *vectorAluInstAvail;
118    int *glbMemInstAvail;
119    int *shrMemInstAvail;
120    bool lastTimeInstExecuted;
121    bool thisTimeInstExecuted;
122    bool instrExecuted;
123    Stats::Scalar  numTransActiveIdle;
124    Stats::Distribution idleDur;
125    uint32_t executionResourcesUsed;
126    uint64_t idle_dur;
127    std::string _name;
128};
129
130#endif // __EXEC_STAGE_HH__
131