/gem5/src/dev/arm/ |
H A D | timer_cpulocal.hh | 131 /** Restart the counter ticking at val 132 * @param val the value to start at */ 133 void restartTimerCounter(uint32_t val); 134 void restartWatchdogCounter(uint32_t val);
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H A D | timer_cpulocal.cc | 266 CpuLocalTimer::Timer::restartTimerCounter(uint32_t val) argument 268 DPRINTF(Timer, "Resetting timer counter with value %#x\n", val); 273 time *= val; 284 CpuLocalTimer::Timer::restartWatchdogCounter(uint32_t val) argument 286 DPRINTF(Timer, "Resetting watchdog counter with value %#x\n", val); 291 time *= val;
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H A D | hdlcd.cc | 463 h_data.val + 1, v_data.val + 1, 464 h_back_porch.val + 1, h_sync.val + 1, h_front_porch.val + 1, 465 v_back_porch.val + 1, v_sync.val + 1, v_front_porch.val + 1);
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/gem5/src/arch/mips/ |
H A D | utility.hh | 63 double roundFP(double val, int digits); 64 double truncFP(double val);
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H A D | isa.cc | 448 ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) argument 455 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 457 miscRegFile[misc_reg][reg_sel] = val; 461 ISA::setRegMask(int misc_reg, RegVal val, ThreadID tid) argument 467 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 468 miscRegFile_WriteMask[misc_reg][reg_sel] = val; 476 ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid) argument 484 tid, misc_reg / 8, misc_reg % 8, miscRegNames[misc_reg], val); 486 RegVal cp0_val = filterCP0Write(misc_reg, reg_sel, val); 499 ISA::filterCP0Write(int misc_reg, int reg_sel, RegVal val) argument [all...] |
H A D | mt.hh | 80 setRegOtherThread(ThreadContext *tc, const RegId& reg, RegVal val, argument 91 return otc->setIntReg(reg.index(), val); 94 return otc->setFloatReg(reg.index(), val); 97 return otc->setMiscReg(reg.index(), val); 111 setRegOtherThread(ExecContext *xc, const RegId& reg, RegVal val, argument 114 setRegOtherThread(xc->tcBase(), reg, val, tid);
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H A D | interrupts.cc | 52 setCauseIP(ThreadContext *tc, uint8_t val) { argument 54 cause.ip = val;
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/gem5/src/dev/ |
H A D | mc146818.cc | 49 bcdize(uint8_t val) argument 52 result = val % 10; 53 result += (val / 10) << 4; 58 unbcdize(uint8_t val) argument 61 result = val & 0xf; 62 result += (val >> 4) * 10;
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/gem5/src/arch/x86/ |
H A D | types.hh | 298 set(Addr val) argument 300 Base::set(val); 305 PCState(Addr val) { set(val); } argument 308 setNPC(Addr val) argument 310 Base::setNPC(val);
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H A D | interrupts.hh | 238 void setReg(ApicRegIndex reg, uint32_t val); 240 setRegNoEffect(ApicRegIndex reg, uint32_t val) argument 242 regs[reg] = val;
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H A D | process.hh | 141 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override; 184 void setSyscallArg(ThreadContext *tc, int i, RegVal val) override;
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/gem5/src/cpu/o3/ |
H A D | cpu.cc | 1184 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid) argument 1186 this->isa[tid]->setMiscRegNoEffect(misc_reg, val); 1191 FullO3CPU<Impl>::setMiscReg(int misc_reg, RegVal val, ThreadID tid) argument 1194 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); 1267 FullO3CPU<Impl>::setIntReg(PhysRegIdPtr phys_reg, RegVal val) argument 1270 regFile.setIntReg(phys_reg, val); 1275 FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, RegVal val) argument 1278 regFile.setFloatReg(phys_reg, val); 1283 FullO3CPU<Impl>::setVecReg(PhysRegIdPtr phys_reg, const VecRegContainer& val) argument 1286 regFile.setVecReg(phys_reg, val); 1291 setVecElem(PhysRegIdPtr phys_reg, const VecElem& val) argument 1299 setVecPredReg(PhysRegIdPtr phys_reg, const VecPredRegContainer& val) argument 1308 setCCReg(PhysRegIdPtr phys_reg, RegVal val) argument 1399 setArchIntReg(int reg_idx, RegVal val, ThreadID tid) argument 1410 setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) argument 1421 setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid) argument 1431 setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, const VecElem& val, ThreadID tid) argument 1441 setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, ThreadID tid) argument 1451 setArchCCReg(int reg_idx, RegVal val, ThreadID tid) argument 1469 pcState(const TheISA::PCState &val, ThreadID tid) argument [all...] |
/gem5/util/stats/ |
H A D | stats.py | 210 val = value(stat, run.run) 211 stdev += pow((val-avg),2) 215 val = value(stat, run.run) 216 if (val < (avg * .9)) or (val > (avg * 1.1)): 218 if (val < (avg - stdev)) or (val > (avg + stdev)): 220 if (val < (avg - (2*stdev))) or (val > (avg + (2*stdev))):
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H A D | display.py | 129 for val,sname,sdesc in map(None, value, subnames, subdescs): 131 mypdf = float(val) / float(mytotal) 142 p.value = val
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H A D | print.py | 126 for val,sname,sdesc in map(None, value, subnames, subdescs): 128 mypdf = float(val) / float(mytotal) 139 p.value = val
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/gem5/ext/systemc/src/sysc/kernel/ |
H A D | sc_time.cpp | 206 value_type val = m_value; local 207 if( val == 0 ) { 221 while( ( val % 10 ) == 0 ) { 222 val /= 10; 226 std::sprintf( buf, "%" PRIu64, val );
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/gem5/src/systemc/tests/systemc/misc/stars/star104726/ |
H A D | global.h | 87 void put(int x, int y, BYTE val); 101 void put(int x, BYTE val); 113 void put(int x, WORD val); 125 void put(int x, COEFF val); 137 void put(int x, int y, COEFF val);
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/gem5/src/dev/net/ |
H A D | i8254xGBe.cc | 167 #define IN_RANGE(val, base, len) (val >= base && val < (base + len)) 379 uint32_t val = pkt->getLE<uint32_t>(); local 386 regs.ctrl = val; 393 regs.ctrl_ext = val; 396 regs.sts = val; 401 regs.eecd = val; 450 regs.eerd = val; 461 regs.mdic = val; [all...] |
/gem5/src/arch/sparc/ |
H A D | isa.hh | 119 void setFSReg(int miscReg, RegVal val, ThreadContext *tc); 189 void setMiscRegNoEffect(int miscReg, RegVal val); 190 void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
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H A D | process.hh | 116 void setSyscallArg(ThreadContext *tc, int i, RegVal val); 160 void setSyscallArg(ThreadContext *tc, int i, RegVal val);
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/gem5/src/python/m5/ |
H A D | options.py | 135 for key,val in opts.__dict__.items(): 136 if val is not None or key not in self: 137 self[key] = val
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/gem5/src/base/ |
H A D | statistics.hh | 514 * @param val The new value. 516 void set(Counter val) { data = val; } 519 * @param val The new value. 521 void inc(Counter val) { data += val; } 524 * @param val The new value. 526 void dec(Counter val) { data -= val; } 585 * @param val Th [all...] |
/gem5/ext/systemc/src/sysc/qt/ |
H A D | qt.h | 78 #define QUICKTHREADS_SPUT(top, at, val) \ 79 (((qt_word_t *)(top))[(at)] = (qt_word_t)(val))
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/gem5/src/base/vnc/ |
H A D | vncserver.hh | 235 * @param val data to recv from the client 237 template <typename T> bool read(T* val); 249 * @param val data to send to the client 251 template <typename T> bool write(T* val);
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/gem5/src/mem/ruby/slicc_interface/ |
H A D | RubySlicc_Util.hh | 78 mod(int val, int mod) argument 80 return val % mod;
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