/gem5/ext/systemc/src/sysc/datatypes/fx/ |
H A D | scfx_other_defs.h | 228 set( i, v.get_bit( i ) ); 243 set( i, v.get_bit( i ) ); 258 set( i, v.get_bit( i ) ); 273 set( i, v.get_bit( i ) ); 297 set( i, v.get_bit( i ) ); 312 set( i, v.get_bit( i ) ); 327 set( i, v.get_bit( i ) ); 342 set( i, v.get_bit( i ) );
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/gem5/src/sim/ |
H A D | eventq_impl.hh | 61 event->flags.set(Event::Scheduled); 103 event->flags.set(Event::Scheduled);
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/gem5/src/arch/arm/kvm/ |
H A D | armv8_cpu.hh | 43 #include <set> 142 static const std::set<MiscRegIndex> deviceRegSet;
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/gem5/ext/testlib/ |
H A D | query.py | 39 tags = set() 41 tags = tags | set(suite.tags)
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/gem5/src/mem/ |
H A D | packet_access.hh | 126 Packet::set(T v, ByteOrder endian) function in class:Packet 136 panic("Illegal byte order in Packet::set()\n"); 143 Packet::set(T v) function in class:Packet
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/gem5/src/cpu/testers/memtest/ |
H A D | memtest.hh | 48 #include <set> 138 std::set<Addr> outstandingAddrs;
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/gem5/src/base/filters/ |
H A D | multi_bloom_filter.cc | 67 Multi::set(Addr addr) function in class:BloomFilter::Multi 70 sub_filter->set(addr);
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H A D | perfect_bloom_filter.cc | 60 Perfect::set(Addr addr) function in class:BloomFilter::Perfect
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/gem5/ext/dsent/model/std_cells/ |
H A D | ADDF.cc | 396 cache->set(cell_name + "->Area->Active", area); 397 cache->set(cell_name + "->Area->Metal1Wire", area); 511 cache->set(cell_name + "->Leakage->!A!B!CI", leakage_000); 512 cache->set(cell_name + "->Leakage->!A!BCI", leakage_001); 513 cache->set(cell_name + "->Leakage->!AB!CI", leakage_010); 514 cache->set(cell_name + "->Leakage->!ABCI", leakage_011); 515 cache->set(cell_name + "->Leakage->A!B!CI", leakage_100); 516 cache->set(cell_name + "->Leakage->A!BCI", leakage_101); 517 cache->set(cell_name + "->Leakage->AB!CI", leakage_110); 518 cache->set(cell_nam [all...] |
/gem5/ext/dsent/model/ |
H A D | OpticalModel.cc | 208 m_optical_input_ports_->set(name_, new PortInfo(name_, wavelength_group_)); 218 m_optical_output_ports_->set(name_, new PortInfo(name_, wavelength_group_)); 228 m_waveguides_->set(name_, new OpticalWaveguide(name_, this, wavelengths_)); 238 m_lasers_->set(name_, new OpticalLaser(name_, this, wavelengths_)); 248 m_modulators_->set(name_, new OpticalModulator(name_, this, wavelengths_, opt_loss_, transmitter_)); 258 m_filters_->set(name_, new OpticalFilter(name_, this, wavelengths_, drop_all_, drop_wavelengths_)); 268 m_detectors_->set(name_, new OpticalDetector(name_, this, wavelengths_, receiver_));
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/gem5/src/gpu-compute/ |
H A D | kernel_cfg.cc | 102 std::set<int> leaders; 158 // In-place set intersection 160 intersect(std::set<uint32_t>& a, const std::set<uint32_t>& b) 162 std::set<uint32_t>::iterator it = a.begin(); 201 // In-place set difference 203 setDifference(std::set<uint32_t>&a, 204 const std::set<uint32_t>& b, uint32_t exception) 224 std::set<uint32_t> candidates = basicBlock->postDominatorIds;
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/gem5/src/mem/probes/ |
H A D | mem_footprint.cc | 93 MemFootprintProbe::insertAddr(Addr addr, AddrSet *set, uint64_t limit) argument 95 set->insert(addr); 96 assert(set->size() <= limit);
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H A D | mem_footprint.hh | 74 void insertAddr(Addr addr, AddrSet *set, uint64_t limit); 86 // Addr set to track unique cache lines accessed 88 // Addr set to track unique cache lines accessed since simulation begin 90 // Addr set to track unique pages accessed 92 // Addr set to track unique pages accessed since simulation begin
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/gem5/src/mem/ruby/structures/ |
H A D | CacheMemory.cc | 110 // Given a cache index: returns the index of the tag in a set. 116 // search the set for the tags 125 // Given a cache index: returns the index of the tag in a set. 132 // search the set for the tags 147 int set = idx / m_cache_assoc; local 148 assert(set < m_cache_num_sets); 150 int way = idx - set * m_cache_assoc; 153 AbstractCacheEntry* entry = m_cache[set][way]; 264 std::vector<AbstractCacheEntry*> &set = m_cache[cacheSet]; local 266 if (!set[ 380 getReplacementWeight(int64_t set, int64_t loc) argument [all...] |
/gem5/ext/nomali/lib/ |
H A D | gpucontrol.hh | 61 void onInterrupt(int set) override;
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/gem5/src/base/ |
H A D | pollevent.hh | 87 static void setupAsyncIO(int fd, bool set);
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H A D | pollevent.cc | 229 PollQueue::setupAsyncIO(int fd, bool set) argument 233 if (set) 238 if (set) 244 // see them if they occurred before we set the FASYNC 248 if (set) {
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/gem5/util/cpt_upgraders/ |
H A D | isa-is-simobject.py | 63 cpt.set(sec, key, value)
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H A D | arm-sysreg-mapping-ns.py | 72 cpt.set(sec, 'miscRegs', ' '.join(str(x) for x in mr))
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/gem5/site_scons/site_tools/ |
H A D | default.py | 51 use_vars = set([ 'AS', 'AR', 'CC', 'CXX', 'HOME', 'LD_LIBRARY_PATH',
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/gem5/src/cpu/ |
H A D | func_unit.cc | 71 capabilityList.set(cap);
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
H A D | dirty.S | 28 # Try a faulting store to make sure dirty bit is not set 42 # Try a non-faulting store to make sure dirty bit is set 53 # Make sure D bit is set 63 # Make sure that superpage entries trap when PPN LSBs are set. 98 # The implementation doesn't appear to set D bits in HW.
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/gem5/src/mem/ruby/system/ |
H A D | RubySystem.py | 40 buffer set its own flag to enable/disable randomization)");
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/gem5/src/mem/cache/tags/ |
H A D | sector_blk.hh | 221 * @param set The set of this entry and sub-entries. 224 void setPosition(const uint32_t set, const uint32_t way) override;
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/gem5/ext/systemc/src/sysc/qt/md/ |
H A D | mips-irix5.s | 79 .set noreorder 83 .set reorder
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