Searched refs:memory (Results 76 - 100 of 107) sorted by relevance

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/gem5/src/mem/
H A Dmem_checker_monitor.cc44 #include <memory>
161 // If a cache miss is served by a cache, a monitor near the memory
163 // would not come back from the memory. Therefore
/gem5/src/sim/
H A Dfd_array.cc42 #include <memory>
H A Deventq.hh46 #include <memory>
295 * Events can use automatic memory management by setting the
302 * memory management. For example, events exported to Python need
/gem5/src/mem/cache/compressors/
H A Dcpack.hh50 #include <memory>
/gem5/src/mem/cache/tags/
H A Dsector_tags.cc39 #include <memory>
/gem5/src/cpu/kvm/
H A Dbase.hh46 #include <memory>
526 * Inject a memory mapped IO request into gem5
532 * @return Number of ticks spent servicing the memory access
576 * KVM memory port. Uses default MasterPort behavior and provides an
H A Dvm.cc51 #include <memory>
302 /* If we couldn't determine how memory slots there are, guess 32. */
350 DPRINTF(Kvm, "Mapping %i memory region(s)\n", memories.size());
365 panic("Tried to map an interleaved memory range into "
373 hack("KVM: Zero memory handled as IO\n");
395 panic("Out of memory slots.\n");
447 panic("Failed to setup KVM memory region:\n"
/gem5/src/mem/ruby/system/
H A DDMASequencer.cc31 #include <memory>
/gem5/src/arch/arm/
H A Dsemihosting.cc572 warn_if(memories.size() > 1, "Multiple physical memory ranges available. "
574 const AddrRange memory = *memories.begin(); local
575 const Addr mem_start = memory.start() + memReserve;
576 Addr mem_end = memory.end();
578 // Make sure that 32-bit guests can access their memory.
582 "Physical memory out of range for a 32-bit guest.");
584 warn("Some physical memory out of range for a 32-bit guest.");
590 "Physical memory too small to fit desired stack and a heap.");
H A Dutility.cc42 #include <memory>
/gem5/ext/systemc/src/
H A Dsystemc.h53 #include <memory>
/gem5/configs/common/
H A DHMC.py44 # [2] High performance AXI-4.0 based interconnect for extensible smart memory
110 # same: It has 4 crossbars in HMC memory. All the crossbars are connected
111 # to each other, providing complete memory range. This archicture also covers
113 # crossbars). All the 4 serial links can access complete memory. So each
228 help="memory range for each of the serial links.\
251 help="Chunk of memory range for each cross bar in\
274 the HMC device. Note: each vault has a memory\
281 default="HMC_2500_1x32", help="type of HMC memory to\
284 help="Number of memory channels")
314 # create memory range
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/gem5/src/arch/arm/insts/
H A Dstatic_inst.hh45 #include <memory>
/gem5/src/arch/x86/
H A Dtlb.cc43 #include <memory>
175 DPRINTF(TLB, "Addresses references internal memory.\n");
179 panic("CPUID memory space not yet implemented!\n");
189 //any memory dependence calculations will not see these as
279 // If this is true, we're dealing with a request to a non-memory address
H A Dpagetable_walker.cc54 #include <memory>
528 // value back to memory.
638 * in the TLB, this should work with no memory accesses.
H A Dinterrupts.cc54 #include <memory>
/gem5/src/base/
H A Dcp_annotate.hh48 #include <memory>
/gem5/src/arch/alpha/
H A Dtlb.cc36 #include <memory>
222 // IPR memory space not implemented
225 "IPR memory space not implemented!");
/gem5/ext/googletest/googlemock/test/
H A Dgmock-internal-utils_test.cc39 #include <memory>
H A Dgmock-actions_test.cc39 #include <memory>
/gem5/ext/mcpat/
H A DxmlParser.cc98 #include <memory.h>
1292 // printf("XMLParser Error: Not enough memory! Aborting...\n"); exit(220);
2350 // Alllocate memory for the XML string + the NULL terminator and
/gem5/tests/test-progs/asmtest/src/riscv/isa/macros/scalar/
H A Dtest_macros.h215 # Test memory instructions
/gem5/src/arch/arm/kvm/
H A Darm_cpu.cc46 #include <memory>
/gem5/src/systemc/core/
H A Dsc_module.cc30 #include <memory>
/gem5/ext/pybind11/include/pybind11/detail/
H A Dcommon.h142 #include <memory>
404 * python side. Non-simple layout allocates the required amount of memory to have multiple

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