/gem5/src/arch/arm/insts/ |
H A D | mem64.hh | 279 void execute(T *b) override 299 void execute(T *b) override 321 void execute(T* b) override
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H A D | misc.cc | 340 McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const function in class:McrMrcMiscInst 365 McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const function in class:McrMrcImplDefined
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H A D | misc.hh | 393 Fault execute(ExecContext *xc, 411 Fault execute(ExecContext *xc,
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H A D | misc64.hh | 227 Fault execute(ExecContext *xc,
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H A D | pred_inst.hh | 369 execute(ExecContext *, Trace::InstRecord *) const override
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H A D | misc64.cc | 373 MiscRegImplDefined64::execute(ExecContext *xc, function in class:MiscRegImplDefined64
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/gem5/ext/systemc/src/sysc/utils/ |
H A D | sc_report_handler.h | 137 static sc_actions execute(sc_msg_def*, sc_severity);
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H A D | sc_report_handler.cpp | 213 sc_actions sc_report_handler::execute(sc_msg_def* md, sc_severity severity_) function in class:sc_core::sc_report_handler 284 sc_actions actions = execute(md, severity_); 312 sc_actions actions = execute(md, severity_);
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H A D | sc_report.cpp | 184 sc_actions actions = execute(md, severity_);
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/gem5/src/systemc/tests/systemc/misc/sim_tests/cycle_dw8051_demo/ |
H A D | cycle_model.h | 152 void execute(instr *i); 180 int cycles2execute; /* number of cycles to execute */
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/gem5/src/gpu-compute/ |
H A D | gpu_dyn_inst.cc | 70 GPUDynInst::execute(GPUDynInstPtr gpuDynInst) function in class:GPUDynInst 72 _staticInst->execute(gpuDynInst);
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H A D | gpu_static_inst.hh | 76 virtual void execute(GPUDynInstPtr gpuDynInst) = 0; 274 execute(GPUDynInstPtr gpuDynInst) override
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/gem5/src/arch/hsail/insts/ |
H A D | mem_impl.hh | 56 LdaInst<DestDataType, AddrRegOperandType>::execute(GPUDynInstPtr gpuDynInst) function in class:HsailISA::LdaInst 165 AddrRegOperandType>::execute(GPUDynInstPtr gpuDynInst) function in class:HsailISA::LdInst 351 AddrRegOperandType>::execute(GPUDynInstPtr gpuDynInst) function in class:HsailISA::StInst 545 HasDst>::execute(GPUDynInstPtr gpuDynInst) function in class:HsailISA::AtomicInst
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H A D | decl.hh | 877 typedef int SrcCType; // used in execute() template 959 void execute(GPUDynInstPtr gpuDynInst); 976 void execute(GPUDynInstPtr gpuDynInst); 1118 execute(GPUDynInstPtr gpuDynInst) function in class:HsailISA::MemFence 1146 fatal("MemFence execute: bad op type\n"); 1256 execute(GPUDynInstPtr gpuDynInst) function in class:HsailISA::Call
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H A D | mem.hh | 180 void execute(GPUDynInstPtr gpuDynInst); 698 void execute(GPUDynInstPtr gpuDynInst) override; 1173 void execute(GPUDynInstPtr gpuDynInst) override; 1502 // if there is no release semantic, execute the RMW immediately 1559 void execute(GPUDynInstPtr gpuDynInst) override;
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/gem5/src/cpu/minor/ |
H A D | lsq.cc | 50 #include "cpu/minor/execute.hh" 82 ExecContext context(port.cpu, thread, port.execute, inst); 105 ExecContext context(port.cpu, thread, port.execute, inst); 642 /* Mark up the error and leave to execute to handle it */ 999 if (!execute.instIsRightStream(request->inst)) { 1054 if (!execute.instIsHeadInst(request->inst)) { 1123 ExecContext context(cpu, thread, execute, request->inst); 1401 execute(execute_),
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H A D | lsq.hh | 66 Execute &execute; member in class:Minor::LSQ
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/gem5/src/cpu/ |
H A D | static_inst.hh | 273 virtual Fault execute(ExecContext *xc, 307 * execute the branch in question. Invalid if not an indirect
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/gem5/src/cpu/o3/ |
H A D | dyn_inst.hh | 92 Fault execute();
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/gem5/src/cpu/trace/ |
H A D | trace_cpu.hh | 100 * readyList) but are not complete. ReadyList handles what and when to execute 123 * compute the execute tick with respect to the time then. Then we proceed to 684 /** Struct to store a ready-to-execute node and its execution tick. */ 922 * This is the main execute function which consumes nodes from the 926 * has its execute tick equal to curTick(), execute it. If the node is 930 void execute(); 946 * are sorted in ascending order of their execute ticks. 949 * @param exec_tick the execute tick of the ready node 1046 /** List of nodes that are ready to execute */ [all...] |
H A D | trace_cpu.cc | 189 dcacheGen.execute(); 329 // Return the execute tick of the earliest ready node so that an event 330 // can be scheduled to call execute() 431 TraceCPU::ElasticDataGen::execute() function in class:TraceCPU::ElasticDataGen 458 // Proceed to execute from readyList 461 // Iterate through readyList until the next free node has its execute 470 // If there is a retryPkt send that else execute the load 491 // as a retry from cache will bring the control to execute(). The 504 // If execute succeeded mark its dependents as complete 593 // execute [all...] |
/gem5/ext/pybind11/include/pybind11/ |
H A D | pybind11.h | 1129 op.execute(*this, extra...); 1141 init.execute(*this, extra...); 1147 init.execute(*this, extra...); 1153 std::move(init).execute(*this, extra...); 1159 std::move(pf).execute(*this, extra...);
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/gem5/util/stats/ |
H A D | db.py | 174 self.cursor.execute(sql)
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/gem5/src/cpu/checker/ |
H A D | cpu_impl.hh | 358 // or we should just go ahead execute the instruction. This assumes 368 fault = curStaticInst->execute(this, traceData); 526 // systems the value obtained at execute may be different than
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/gem5/src/cpu/simple/ |
H A D | atomic.cc | 713 fault = curStaticInst->execute(&t_info, traceData);
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