Searched refs:TLB (Results 26 - 37 of 37) sorted by relevance

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/gem5/src/arch/arm/
H A Dtable_walker.hh61 class TLB;
125 return "Inserting Section Descriptor into TLB\n";
275 return "Inserting L2 Descriptor into TLB\n";
406 return "Inserting Page descriptor into TLB\n";
409 return "Inserting Block descriptor into TLB\n";
605 * function used to simplify the code in the TLB for performing
715 TLB::Translation *transState;
774 TLB::Translation *stage2Tran;
786 TLB::ArmTranslationType tranType;
838 /** TLB tha
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H A Dutility.cc191 dynamic_cast<TLB *>(dest->getITBPtr())->invalidateMiscReg();
192 dynamic_cast<TLB *>(dest->getDTBPtr())->invalidateMiscReg();
/gem5/src/arch/sparc/
H A Dtlb.hh52 class TLB : public BaseTLB class in namespace:SparcISA
58 // TLB state
60 // Only used when this is the data TLB.
108 /** lookup an entry in the TLB based on the partition id, and real bit if
122 /** Remove all entries from the TLB */
126 /** Insert a PTE into the TLB. */
159 TLB(const Params *p);
H A Dfaults.cc670 // Insert the TLB entry.
675 dynamic_cast<TLB *>(tc->getITBPtr())->
740 // the context is the relevant issue since we need to pass it to TLB.
757 // Insert the TLB entry.
762 dynamic_cast<TLB *>(tc->getDTBPtr())->
/gem5/src/arch/alpha/
H A Dev5.cc47 TLB *
50 auto tlb = dynamic_cast<TLB *>(tc->getITBPtr());
56 TLB *
59 auto tlb = dynamic_cast<TLB *>(tc->getDTBPtr());
419 // insert new TAG/PTE value into data TLB
443 // insert new TAG/PTE value into data TLB
H A Dfaults.cc206 dynamic_cast<TLB *>(tc->getITBPtr())->insert(vaddr.page(), entry);
225 dynamic_cast<TLB *>(tc->getDTBPtr())->insert(vaddr.page(), entry);
/gem5/src/arch/arm/insts/
H A Dmacromem.cc477 uint32_t noAlign = TLB::MustBeOne;
838 uint32_t noAlign = TLB::MustBeOne;
1148 uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
1149 TLB::AllowUnaligned;
1256 uint32_t memaccessFlags = TLB::MustBeOne | (TLB::ArmFlags) eSize |
1257 TLB::AllowUnaligned;
1324 uint32_t memaccessFlags = TLB::MustBeOne | (TLB
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H A Dmacromem.hh123 memAccessFlags(TLB::MustBeOne)
397 up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
418 memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
H A Dmem64.cc82 memAccessFlags |= ArmISA::TLB::AllowUnaligned;
/gem5/configs/example/
H A Druby_gpu_random_test.py67 sharing an SQC (icache, and thus icache TLB)")
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc779 unsigned mem_flags = ArmISA::TLB::MustBeOne | 3 |
780 ArmISA::TLB::AllowUnaligned;
1054 ArmISA::TLB* dtb = static_cast<TLB*>(thread->getDTBPtr());
/gem5/src/arch/x86/
H A Dremote_gdb.cc75 Walker *walker = dynamic_cast<TLB *>(

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