Searched hist:9382 (Results 1 - 16 of 16) sorted by relevance

/gem5/src/arch/arm/tracers/
H A Dtarmac_record_v8.cc12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dtarmac_record.hh12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dtarmac_record_v8.hh12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dtarmac_tracer.hh12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dtarmac_tracer.cc12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A DSConscript12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dtarmac_record.cc12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A DTarmacTrace.py12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/cpu/checker/
H A Dcpu_impl.hh9382:1c97b57d5169 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> cpu: rename the misleading inSyscall to noSquashFromTC

isSyscall was originally created because during handling of a syscall in SE
mode the threadcontext had to be updated. However, in many places this is used
in FS mode (e.g. fault handlers) and the name doesn't make much sense. The
boolean actually stops gem5 from squashing speculative and non-committed state
when a write to a threadcontext happens, so re-name the variable to something
more appropriate
/gem5/src/cpu/o3/
H A Ddyn_inst_impl.hh9382:1c97b57d5169 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> cpu: rename the misleading inSyscall to noSquashFromTC

isSyscall was originally created because during handling of a syscall in SE
mode the threadcontext had to be updated. However, in many places this is used
in FS mode (e.g. fault handlers) and the name doesn't make much sense. The
boolean actually stops gem5 from squashing speculative and non-committed state
when a write to a threadcontext happens, so re-name the variable to something
more appropriate
H A Dthread_state.hh9382:1c97b57d5169 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> cpu: rename the misleading inSyscall to noSquashFromTC

isSyscall was originally created because during handling of a syscall in SE
mode the threadcontext had to be updated. However, in many places this is used
in FS mode (e.g. fault handlers) and the name doesn't make much sense. The
boolean actually stops gem5 from squashing speculative and non-committed state
when a write to a threadcontext happens, so re-name the variable to something
more appropriate
H A Ddyn_inst.hh9382:1c97b57d5169 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> cpu: rename the misleading inSyscall to noSquashFromTC

isSyscall was originally created because during handling of a syscall in SE
mode the threadcontext had to be updated. However, in many places this is used
in FS mode (e.g. fault handlers) and the name doesn't make much sense. The
boolean actually stops gem5 from squashing speculative and non-committed state
when a write to a threadcontext happens, so re-name the variable to something
more appropriate
H A Dthread_context.hh9382:1c97b57d5169 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> cpu: rename the misleading inSyscall to noSquashFromTC

isSyscall was originally created because during handling of a syscall in SE
mode the threadcontext had to be updated. However, in many places this is used
in FS mode (e.g. fault handlers) and the name doesn't make much sense. The
boolean actually stops gem5 from squashing speculative and non-committed state
when a write to a threadcontext happens, so re-name the variable to something
more appropriate
H A Dthread_context_impl.hh9382:1c97b57d5169 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> cpu: rename the misleading inSyscall to noSquashFromTC

isSyscall was originally created because during handling of a syscall in SE
mode the threadcontext had to be updated. However, in many places this is used
in FS mode (e.g. fault handlers) and the name doesn't make much sense. The
boolean actually stops gem5 from squashing speculative and non-committed state
when a write to a threadcontext happens, so re-name the variable to something
more appropriate
H A Dcommit_impl.hh9382:1c97b57d5169 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> cpu: rename the misleading inSyscall to noSquashFromTC

isSyscall was originally created because during handling of a syscall in SE
mode the threadcontext had to be updated. However, in many places this is used
in FS mode (e.g. fault handlers) and the name doesn't make much sense. The
boolean actually stops gem5 from squashing speculative and non-committed state
when a write to a threadcontext happens, so re-name the variable to something
more appropriate
H A Dcpu.cc9382:1c97b57d5169 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> cpu: rename the misleading inSyscall to noSquashFromTC

isSyscall was originally created because during handling of a syscall in SE
mode the threadcontext had to be updated. However, in many places this is used
in FS mode (e.g. fault handlers) and the name doesn't make much sense. The
boolean actually stops gem5 from squashing speculative and non-committed state
when a write to a threadcontext happens, so re-name the variable to something
more appropriate

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