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/gem5/src/sim/
H A Dsystem.hh5718:323cfbfec1a4 Wed Nov 05 15:30:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Right now a single thread cpu 1 could get assigned context Id != 1, depending
on the order in which it's registered with the system. To make them match,
here is a little change.
H A Dsystem.cc5718:323cfbfec1a4 Wed Nov 05 15:30:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Right now a single thread cpu 1 could get assigned context Id != 1, depending
on the order in which it's registered with the system. To make them match,
here is a little change.
/gem5/src/cpu/
H A Dbase.cc5718:323cfbfec1a4 Wed Nov 05 15:30:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> Right now a single thread cpu 1 could get assigned context Id != 1, depending
on the order in which it's registered with the system. To make them match,
here is a little change.

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