Searched hist:53 (Results 51 - 75 of 402) sorted by relevance
/gem5/src/mem/cache/replacement_policies/ | ||
H A D | brrip_rp.cc | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | random_rp.hh | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | random_rp.cc | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | lru_rp.cc | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | mru_rp.hh | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | brrip_rp.hh | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/arch/alpha/ | ||
H A D | decoder.hh | 9020:14321ce30881 Fri May 25 03:53:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> Decode: Make the Decoder class defined per ISA. |
/gem5/src/arch/power/ | ||
H A D | decoder.hh | 9020:14321ce30881 Fri May 25 03:53:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> Decode: Make the Decoder class defined per ISA. |
/gem5/src/arch/x86/isa/insts/ | ||
H A D | romutil.py | 6048:65a321a3a691 Sun Apr 19 05:53:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the INIT IPI. |
/gem5/src/arch/x86/ | ||
H A D | decoder_tables.cc | 10593:a39de7b8d2c9 Thu Dec 04 18:53:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Rework opcode parsing to support 3 byte opcodes properly. Instead of counting the number of opcode bytes in an instruction and recording each byte before the actual opcode, we can represent the path we took to get to the actual opcode byte by using a type code. That has a couple of advantages. First, we can disambiguate the properties of opcodes of the same length which have different properties. Second, it reduces the amount of data stored in an ExtMachInst, making them slightly easier/faster to create and process. This also adds some flexibility as far as how different types of opcodes are handled, which might come in handy if we decide to support VEX or XOP instructions. This change also adds tables to support properly decoding 3 byte opcodes. Before we would fall off the end of some arrays, on top of the ambiguity described above. This change doesn't measureably affect performance on the twolf benchmark. |
/gem5/src/arch/sparc/ | ||
H A D | locked_mem.hh | 3170:37fd1e73f836 Sun Oct 08 13:53:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. Note that properly setting cpu_id on all CPUs is now required for correct operation. src/arch/SConscript: src/base/traceflags.py: src/cpu/base.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/cpu/simple/timing.hh: src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: src/python/m5/objects/BaseCPU.py: tests/configs/simple-atomic.py: tests/configs/simple-timing.py: tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing) and PhysicalMemory. *No* support for caches or O3CPU. |
/gem5/src/arch/mips/ | ||
H A D | decoder.hh | 9020:14321ce30881 Fri May 25 03:53:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> Decode: Make the Decoder class defined per ISA. |
/gem5/src/proto/ | ||
H A D | protoio.cc | 9705:177e8d8e50fc Thu May 30 00:53:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> base: Avoid size limitation on protobuf coded streams This patch changes how the streams are created to avoid the size limitation on the coded streams. As we only read/write a single message at a time, there is never any message larger than a few bytes. However, the coded stream eventually complains that its internal counter reaches 64+ MByte if the total file size exceeds this value. Based on suggestions in the protobuf discussion forums, the coded stream is now created for every message that is read/written. The result is that the internal byte count never goes about tens of bytes, and we can read/write any size file that the underlying file I/O can handle. |
/gem5/src/arch/arm/isa/insts/ | ||
H A D | str64.isa | 12386:2bf5fb25a5f1 Wed Dec 13 03:53:00 EST 2017 Gabe Black <gabeblack@google.com> arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. Replace them with std::array<>s. Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34 Reviewed-on: https://gem5-review.googlesource.com/6602 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/dev/storage/ | ||
H A D | ide_ctrl.cc | 12201:cef59b44d586 Mon Sep 25 20:53:00 EDT 2017 Gabe Black <gabeblack@google.com> dev: Make the IDE controller handle NULL simobject pointers. Only panic if there are disks which would actually be connected to it beyond its limit. Also skip past disks which are set to NULL. This is useful since it lets you set up disks on different ports of the controller instead of filling them contiguously. Change-Id: I92f1316d3ad6931e25bfffeb34fb2603c0b95ce7 Reviewed-on: https://gem5-review.googlesource.com/4848 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
/gem5/ | ||
H A D | .gitignore | 12058:bf3a851220c7 Fri Jun 02 19:53:00 EDT 2017 Gabe Black <gabeblack@google.com> misc: Ignore build products in src/util/term. Change-Id: I8027a282c261d29cd276742411eb0ed3ce078247 Reviewed-on: https://gem5-review.googlesource.com/3641 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
/gem5/src/python/m5/util/ | ||
H A D | sorteddict.py | 7503:37da2c208f5f Wed Jul 21 18:53:00 EDT 2010 Nathan Binkert <nate@binkert.org> python: add a sorted dictionary class It would be nice if python had a tree class that would do this for real, but since we don't, we'll just keep a sorted list of keys and update it on demand. |
/gem5/tests/configs/ | ||
H A D | gpu-ruby.py | 13718:89e8bcc7253b Mon Jan 28 11:53:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update test scripts to work with Python 3 Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15999 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | memtest-filter.py | 13718:89e8bcc7253b Mon Jan 28 11:53:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update test scripts to work with Python 3 Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15999 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | pc-simple-timing-ruby.py | 13916:efa5b9e899e3 Wed May 01 16:53:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> tests: Add missing kernels to system creation Change 149c1fc2d070a8ce073263880ecf2ccf7535e569 removed the default value of the kernels, and fs tests rely on those. Change-Id: I6d83420af5881ab59c2d223a9915f363dd8a1c69 Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18528 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> 13718:89e8bcc7253b Mon Jan 28 11:53:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update test scripts to work with Python 3 Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15999 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> 9577:91cac7c9c636 Wed Mar 06 22:53:00 EST 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove the functional copy of memory in se mode This patch removes the functional copy of the memory that was maintained in the se mode. Now ruby itself will provide the data. |
/gem5/util/ | ||
H A D | encode_packet_trace.py | 9706:fbb19814adbc Thu May 30 00:53:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> util: Auto generate the packet proto definitions This patch simplifies the usage of the packet trace encoder/decoder by attempting to automatically generating the packet proto definitions in case they cannot be found. |
H A D | o3-pipeview.py | 8471:18e560ba1539 Fri Jul 15 12:53:00 EDT 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Create a pipeline activity viewer for the O3 CPU model. Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py) and modified O3 code base to support an extra trace flag (O3PipeView) for generating traces to be used as inputs by the tool. |
/gem5/src/mem/ruby/network/ | ||
H A D | Network.py | 9594:219ad5fe8c04 Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: convert Topology to regular class The Topology class in Ruby does not need to inherit from SimObject class. This patch turns it into a regular class. The topology object is now created in the constructor of the Network class. All the parameters for the topology class have been moved to the network class. 9593:9441ca79f3c8 Fri Mar 22 16:53:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: move routers from topology to network |
/gem5/configs/boot/ | ||
H A D | nat-netperf-maerts-client.rcS | 3690:28b3001a883d Thu Nov 30 11:53:00 EST 2006 Lisa Hsu <hsul@eecs.umich.edu> netperf-maerts-client.rcS: change /netperf/netperf to /netperf-bin/netperf nat-netperf-maerts-client.rcS: bad comment that went with the file - accidentally committed but probably doesn't matter, i ust eliminated an ivlb in the script. configs/boot/nat-netperf-maerts-client.rcS: replace netperf/netperf with netperf-bin/netperf configs/boot/netperf-maerts-client.rcS: change /netperf/netperf to /netperf-bin/netperf |
/gem5/src/arch/arm/isa/formats/ | ||
H A D | macromem.isa | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
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