Searched hist:53 (Results 26 - 50 of 402) sorted by relevance
/gem5/src/gpu-compute/ | ||
H A D | hsail_code.hh | 12603:ab2cec4483af Fri Mar 16 03:53:00 EDT 2018 Gabe Black <gabeblack@google.com> hsail: Get rid of an inert private member of StorageSpace. The "segment" private element in this class was only ever set to zero on construction, and then used to index into a list of segment names to get the string "none" in a DPRINTF. If debugging was turned off, there would be no consumers of that variable, and that upset g++. This change removes the essentially useless variable, and also that bit of text in the DPRINTF. Change-Id: I3f85db4af5f0678768243daf84b8d698350af931 Reviewed-on: https://gem5-review.googlesource.com/9221 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> |
H A D | hsail_code.cc | 12603:ab2cec4483af Fri Mar 16 03:53:00 EDT 2018 Gabe Black <gabeblack@google.com> hsail: Get rid of an inert private member of StorageSpace. The "segment" private element in this class was only ever set to zero on construction, and then used to index into a list of segment names to get the string "none" in a DPRINTF. If debugging was turned off, there would be no consumers of that variable, and that upset g++. This change removes the essentially useless variable, and also that bit of text in the DPRINTF. Change-Id: I3f85db4af5f0678768243daf84b8d698350af931 Reviewed-on: https://gem5-review.googlesource.com/9221 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com> |
/gem5/tests/legacy-configs/ | ||
H A D | run.py | 13718:89e8bcc7253b Mon Jan 28 11:53:00 EST 2019 Andreas Sandberg <andreas.sandberg@arm.com> tests: Update test scripts to work with Python 3 Change-Id: I71b1e595765fed9e9f234c9722c33ac5348d4f11 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15999 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/proto/ | ||
H A D | protoio.hh | 9705:177e8d8e50fc Thu May 30 00:53:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> base: Avoid size limitation on protobuf coded streams This patch changes how the streams are created to avoid the size limitation on the coded streams. As we only read/write a single message at a time, there is never any message larger than a few bytes. However, the coded stream eventually complains that its internal counter reaches 64+ MByte if the total file size exceeds this value. Based on suggestions in the protobuf discussion forums, the coded stream is now created for every message that is read/written. The result is that the internal byte count never goes about tens of bytes, and we can read/write any size file that the underlying file I/O can handle. |
/gem5/configs/boot/ | ||
H A D | netperf-maerts-client.rcS | 3690:28b3001a883d Thu Nov 30 11:53:00 EST 2006 Lisa Hsu <hsul@eecs.umich.edu> netperf-maerts-client.rcS: change /netperf/netperf to /netperf-bin/netperf nat-netperf-maerts-client.rcS: bad comment that went with the file - accidentally committed but probably doesn't matter, i ust eliminated an ivlb in the script. configs/boot/nat-netperf-maerts-client.rcS: replace netperf/netperf with netperf-bin/netperf configs/boot/netperf-maerts-client.rcS: change /netperf/netperf to /netperf-bin/netperf |
/gem5/src/arch/arm/ | ||
H A D | stacktrace.hh | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
H A D | vtophys.hh | 6019:76890d8b28f5 Sun Apr 05 21:53:00 EDT 2009 Stephen Hines <hines@cs.fsu.edu> arm: add ARM support to M5 |
/gem5/src/arch/power/ | ||
H A D | faults.hh | 6972:b6482c4c89e3 Fri Feb 12 14:53:00 EST 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> Power ISA: Add an alignment fault to Power ISA and check alignment in TLB. |
/gem5/src/arch/x86/isa/decoder/ | ||
H A D | locked_opcodes.isa | 10593:a39de7b8d2c9 Thu Dec 04 18:53:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Rework opcode parsing to support 3 byte opcodes properly. Instead of counting the number of opcode bytes in an instruction and recording each byte before the actual opcode, we can represent the path we took to get to the actual opcode byte by using a type code. That has a couple of advantages. First, we can disambiguate the properties of opcodes of the same length which have different properties. Second, it reduces the amount of data stored in an ExtMachInst, making them slightly easier/faster to create and process. This also adds some flexibility as far as how different types of opcodes are handled, which might come in handy if we decide to support VEX or XOP instructions. This change also adds tables to support properly decoding 3 byte opcodes. Before we would fall off the end of some arrays, on top of the ambiguity described above. This change doesn't measureably affect performance on the twolf benchmark. |
/gem5/src/base/ | ||
H A D | fenv.c | 4571:04b82abadd44 Thu Jun 14 09:53:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix an assert to allow rounding mode 0. |
/gem5/src/mem/cache/replacement_policies/ | ||
H A D | bip_rp.cc | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | bip_rp.hh | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | lfu_rp.cc | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | lfu_rp.hh | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | fifo_rp.cc | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | fifo_rp.hh | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
H A D | mru_rp.cc | 12684:44ebd2bc020f Tue Mar 27 05:53:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: ReplacementPolicy specific replacement data Replacement data is specific for each replacement policy, and thus should be instantiated differently by each policy. Touch() and reset() do not need to be aware of CacheBlk, as they only update its ReplacementData. Invalidate() makes replacement policies independent of cache blocks, by removing the awareness of the valid state. An inheritable base ReplaceableEntry class was created to allow usage of replacement policies with any table-like structure. Change-Id: I998917d800fa48504ed95abffa2f1b7bfd68522b Reviewed-on: https://gem5-review.googlesource.com/9421 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
/gem5/src/sim/ | ||
H A D | emul_driver.hh | 10496:0a5a8ecd0ec6 Wed Oct 22 18:53:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> syscall_emul: add EmulatedDriver object Fake SE-mode device drivers can now be added by deriving from this abstract object. |
/gem5/src/arch/arm/insts/ | ||
H A D | sve_macromem.hh | 14106:293e3f4b1321 Wed Apr 04 11:53:00 EDT 2018 Javier Setoain <javier.setoain@arm.com> arch-arm: Add support for SVE load/store structures Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13524 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
/gem5/src/systemc/ext/core/ | ||
H A D | sc_time.hh | 13263:bcd6d8140486 Thu Sep 27 01:53:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Implement the sc_time_tuple class. This class is non-standard and is an implementation detail in Accellera's implementation, but is referred to directly by the tests. It does the same thing as the time printing function, so rather than having duplicate code the printing function now uses the sc_time_tuple class even though it was doing fine on its own already. Change-Id: I69594ed0651f212ded6d979d60523bb3b0a789b1 Reviewed-on: https://gem5-review.googlesource.com/c/13189 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> 12983:fb1f462ae89e Thu Jul 19 19:53:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Implement some of the basics of sc_time. This is a very incomplete implementation, but is enough to unblock implementing some other dependent features. Change-Id: Ibd2f3476fe01389e277c6956d48337f551d14acd Reviewed-on: https://gem5-review.googlesource.com/12034 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
H A D | sc_interface.hh | 13041:ffcb5efb97d7 Tue Aug 07 07:53:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: "Implement" sc_interface's methods. Most don't do anything. Make default_event() return a dummy event to avoid dereferencing a null pointer. Change-Id: I8d6d576d3a1f585029c387cd414bbebf2d670644 Reviewed-on: https://gem5-review.googlesource.com/12072 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/arch/x86/isa/insts/general_purpose/input_output/ | ||
H A D | general_io.py | 8103:53c2d9b1c15d Wed Mar 02 01:42:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Mark IO reads and writes as non-speculative. |
H A D | string_io.py | 8103:53c2d9b1c15d Wed Mar 02 01:42:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Mark IO reads and writes as non-speculative. |
/gem5/src/systemc/ext/ | ||
H A D | systemc | 12873:9e8c1b5de92c Mon Jun 11 21:53:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Include boost/bind.hpp in the systemc header. The systemc spec says that sc_bind, sc_ref and sc_cref macros should expand to boost::bind, boost::ref, and boost::cref respectively, but that it's "use is not mandantory". Unfortunately, the regression tests use those macros without actually including the boost headers for themselves, and so they won't compile without dragging in these boost headers as a dependency. This should be mostly ok to include here since gem5 itself shouldn't include systemc, just the sub headers that systemc brings in. systemc code which includes systemc *will* have a dependency on boost, but that at least contains the new dependency somewhat. Change-Id: I1877a1b7dae2952f30a9d577d778739abbe7ac3b Reviewed-on: https://gem5-review.googlesource.com/11178 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
/gem5/src/sim/power/ | ||
H A D | MathExprPowerModel.py | 11969:206f7111d5aa Thu Apr 06 09:53:00 EDT 2017 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Clarify the unit used for the power equations (W) Change-Id: Iab5070fc9b666fcb5b49b0e2b99a4a1605b3b721 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> |
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