History log of /gem5/src/arch/x86/isa/decoder/locked_opcodes.isa
Revision Date Author Comments
# 10593:a39de7b8d2c9 04-Dec-2014 Gabe Black <gabeblack@google.com>

x86: Rework opcode parsing to support 3 byte opcodes properly.

Instead of counting the number of opcode bytes in an instruction and recording
each byte before the actual opcode, we can represent the path we took to get to
the actual opcode byte by using a type code. That has a couple of advantages.
First, we can disambiguate the properties of opcodes of the same length which
have different properties. Second, it reduces the amount of data stored in an
ExtMachInst, making them slightly easier/faster to create and process. This
also adds some flexibility as far as how different types of opcodes are
handled, which might come in handy if we decide to support VEX or XOP
instructions.

This change also adds tables to support properly decoding 3 byte opcodes.
Before we would fall off the end of some arrays, on top of the ambiguity
described above.

This change doesn't measureably affect performance on the twolf benchmark.


# 6611:2cd76560a1f1 17-Aug-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Double check the two byte portion of the decoder and fix bugs/clean up.


# 6486:33faa9915d16 09-Aug-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Implement the CMPXCHG8B/CMPXCHG16B instruction.


# 6100:a61ac4a3591d 19-Apr-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Fix up a copyright.


# 6098:34690e3cf53e 19-Apr-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Recognize and handle the lock legacy prefix.