Searched hist:52 (Results 776 - 800 of 992) sorted by relevance
| /gem5/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/ | ||
| H A D | stats.txt | 10433:821cbe4a183b Thu Oct 09 17:52:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Add DRAM power statistics to reference output 9838:43d22d746e7a Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size. 8983:8800b05e1cb3 Wed May 09 14:52:00 EDT 2012 Nathan Binkert <nate@binkert.org> stats: update stats for no_value -> nan Lots of accumulated older changes too. |
| /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/ | ||
| H A D | stats.txt | 10433:821cbe4a183b Thu Oct 09 17:52:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Add DRAM power statistics to reference output 9838:43d22d746e7a Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size. 8983:8800b05e1cb3 Wed May 09 14:52:00 EDT 2012 Nathan Binkert <nate@binkert.org> stats: update stats for no_value -> nan Lots of accumulated older changes too. |
| H A D | config.ini | 8983:8800b05e1cb3 Wed May 09 14:52:00 EDT 2012 Nathan Binkert <nate@binkert.org> stats: update stats for no_value -> nan Lots of accumulated older changes too. |
| H A D | simout | 8983:8800b05e1cb3 Wed May 09 14:52:00 EDT 2012 Nathan Binkert <nate@binkert.org> stats: update stats for no_value -> nan Lots of accumulated older changes too. |
| /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/ | ||
| H A D | stats.txt | 10433:821cbe4a183b Thu Oct 09 17:52:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Add DRAM power statistics to reference output 9838:43d22d746e7a Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Cumulative stats update This patch updates the stats to reflect the: 1) addition of the internal queue in SimpleMemory, 2) moving of the memory class outside FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying burst size and interface width for the DRAM instead of relying on cache-line size, 5) performing merging in the DRAM controller write buffer, and 6) fixing how idle cycles are counted in the atomic and timing CPU models. The main reason for bundling them up is to minimise the changeset size. 8983:8800b05e1cb3 Wed May 09 14:52:00 EDT 2012 Nathan Binkert <nate@binkert.org> stats: update stats for no_value -> nan Lots of accumulated older changes too. |
| /gem5/src/arch/arm/linux/ | ||
| H A D | process.cc | 13984:7200989d951c Fri May 03 01:52:00 EDT 2019 Gabe Black <gabeblack@google.com> arm: Add an object file loader for linux and freebsd. Change-Id: Ie5fd187a4897aa608ffc12278b23d3ee8c0f323c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18585 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> 13533:c19aabc6fe2b Tue Jan 08 19:52:00 EST 2019 Javier Setoain <javier.setoain@arm.com> arch-arm, sim-se: Wire up syscalls needed for pthreads Change-Id: I8da5e3e0d7dc5d31ac82ed2045109d6d73cbf99d Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Cc: Giacomo Travaglini <giacomo.travaglini@arm.com> Cc: Javier Setoain <javier.setoain@arm.com> Cc: Brandon Potter <Brandon.Potter@amd.com> Reviewed-on: https://gem5-review.googlesource.com/c/15415 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> 9146:a61fdbbc1d45 Mon Aug 06 22:52:00 EDT 2012 Marc Orr <marc.orr@gmail.com> syscall emulation: Enabled getrlimit and getrusage for x86. Added/moved rlimit constants to base linux header file. This patch is a revised version of Vince Weaver's earlier patch. |
| /gem5/src/cpu/ | ||
| H A D | exetrace.cc | 4572:5499df089a6c Thu Jun 14 16:52:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Modified instruction decode method. Make code compatible with new decode method. src/arch/alpha/remote_gdb.cc: src/cpu/base_dyn_inst_impl.hh: src/cpu/exetrace.cc: src/cpu/simple/base.cc: Make code compatible with new decode method. src/cpu/static_inst.cc: src/cpu/static_inst.hh: Modified instruction decode method. 4359:6b6cb2927594 Mon Apr 09 21:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fixed a compile error. 4011:e6899d7ca5b1 Tue Feb 06 15:52:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> more fp fixes fix unaligned accesses in mmaped disk device src/arch/sparc/isa/decoder.isa: get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code src/arch/sparc/isa/formats/basic.isa: move the cexec into the aexec field src/cpu/exetrace.cc: copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer src/dev/sparc/mm_disk.cc: src/dev/sparc/mm_disk.hh: fix unaligned accesses in the memory mapped disk device 3970:d54945bab95d Wed Jan 03 00:52:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem 3380:382e21bc32f3 Wed Oct 18 20:52:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Fixed up exetrace.cc to deal with microcode, and to made floating point register numbers correlate to the numbers used in SPARC in m5 and statetrace. src/cpu/exetrace.cc: Fixed up to deal with microcode, and to make floating point register numbers correlate to the numbers used in SPARC. util/statetrace/arch/tracechild_sparc.cc: util/statetrace/arch/tracechild_sparc.hh: Make floating point register numbers correlate to the numbers used in SPARC. |
| /gem5/configs/example/ | ||
| H A D | fs.py | 9836:4411b4e0c03a Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Command line support for multi-channel memory This patch adds support for specifying multi-channel memory configurations on the command line, e.g. 'se/fs.py --mem-type=ddr3_1600_x64 --mem-channels=4'. To enable this, it enhances the functionality of MemConfig and moves the existing makeMultiChannel class method from SimpleDRAM to the support scripts. The se/fs.py example scripts are updated to make use of the new feature. 9835:cc7a7fc71c42 Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> mem: Change AbstractMemory defaults to match the common case This patch changes the default parameter value of conf_table_reported to match the common case. It also simplifies the regression and config scripts to reflect this change. 9827:f47274776aa0 Mon Aug 19 03:52:00 EDT 2013 Akash Bagdia <akash.bagdia@arm.com> power: Add voltage domains to the clock domains This patch adds the notion of voltage domains, and groups clock domains that operate under the same voltage (i.e. power supply) into domains. Each clock domain is required to be associated with a voltage domain, and the latter requires the voltage to be explicitly set. A voltage domain is an independently controllable voltage supply being provided to section of the design. Thus, if you wish to perform dynamic voltage scaling on a CPU, its clock domain should be associated with a separate voltage domain. The current implementation of the voltage domain does not take into consideration cases where there are derived voltage domains running at ratio of native voltage domains, as with the case where there can be on-chip buck/boost (charge pumps) voltage regulation logic. The regression and configuration scripts are updated with a generic voltage domain for the system, and one for the CPUs. 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. 6995:f2b4d8bea5d3 Sat Feb 27 21:52:00 EST 2010 Gabe Black <gblack@eecs.umich.edu> Config: Fix fs.py's call to CacheConfig.config_cache. 5133:a88763dd4a84 Sun Oct 07 20:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Adjust the config scripts for x86 fs. 3970:d54945bab95d Wed Jan 03 00:52:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem |
| /gem5/src/arch/sparc/isa/ | ||
| H A D | decoder.isa | 11294:a368064a2ab5 Mon Jan 11 05:52:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable -Wextra by default Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial. 8450:40e10746b049 Tue Jul 05 19:52:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISAs: Streamline some spots where Mem is used in the ISA descriptions. 4011:e6899d7ca5b1 Tue Feb 06 15:52:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> more fp fixes fix unaligned accesses in mmaped disk device src/arch/sparc/isa/decoder.isa: get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code src/arch/sparc/isa/formats/basic.isa: move the cexec into the aexec field src/cpu/exetrace.cc: copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer src/dev/sparc/mm_disk.cc: src/dev/sparc/mm_disk.hh: fix unaligned accesses in the memory mapped disk device 4010:52c2b6941c02 Fri Feb 02 19:02:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> more sparc fixes src/arch/sparc/isa/decoder.isa: fix rdgsr fault check src/arch/sparc/tlb.cc: block asis are now supported 3992:d08b4ae09876 Mon Jan 29 22:52:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add implementation for the fcmp instructions. These don't behave -quite- right with respect to quite NaNs, but hopefully we don't need to worry about the distinction. 3970:d54945bab95d Wed Jan 03 00:52:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem |
| /gem5/configs/common/ | ||
| H A D | Simulation.py | 12880:cb1fb179e8c8 Thu Sep 21 20:52:00 EDT 2017 Jason Lowe-Power <jason@lowepower.com> configs: Always exit with code 0 Update simulation.py to always exit with code 0 assuming the simulation exits normally. If the running application has a return code that is non zero, then print the return code before exiting. Change-Id: I1983985d50311627574d4364b32ee961ae88e003 Signed-off-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-on: https://gem5-review.googlesource.com/4880 6107:52a5e1c63380 Tue Apr 21 11:17:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> Minor tweaks for future Ruby compatibility. 5311:9ed42a2315ae Tue Dec 18 01:52:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Checkpointing: Fix a bug in the simulation script when restoring without standard switch and change some ifs to work with the default port since every port is now connected to something. |
| /gem5/src/mem/ | ||
| H A D | dram_ctrl.hh | 12969:52de9d619ce6 Fri Aug 04 06:11:00 EDT 2017 Matteo Andreozzi <Matteo.Andreozzi@arm.com> mem: Make DRAMCtrl a QoS-aware Memory Controller This patch is turning DRAMCtrl a QoS-aware Memory Controller with "no policy" as a default policy. Change-Id: I48163da8c8208498cf0398b07094cb840272507f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11973 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> 10216:52c869140fc2 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add DRAM cycle time This patch extends the current timing parameters with the DRAM cycle time. This is needed as the DRAMPower tool expects timestamps in DRAM cycles. At the moment we could get away with doing this in a post-processing step as the DRAMPower execution is separate from the simulation run. However, in the long run we want the tool to be called during the simulation, and then the cycle time is needed. 10215:52d46098c1b6 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Simplify DRAM response scheduling This patch simplifies the DRAM response scheduling based on the assumption that they are always returned in order. |
| /gem5/src/cpu/o3/ | ||
| H A D | SConscript | 2817:273f7fb94f83 Fri Jun 30 19:52:00 EDT 2006 Korey Sewell <ksewell@umich.edu> Make O3CPU model independent of the ISA Use O3CPU when building instead of AlphaO3CPU. I could use some better python magic in the cpu_models.py file! AUTHORS: add middle initial SConstruct: change from AlphaO3CPU to O3CPU src/cpu/SConscript: edits to build O3CPU instead of AlphaO3CPU src/cpu/cpu_models.py: change substitution template to use proper CPU EXEC CONTEXT For O3CPU Model... Actually, some Python expertise could be used here. The 'env' variable is not passed to this file, so I had to parse through the ARGV to find the ISA... src/cpu/o3/base_dyn_inst.cc: src/cpu/o3/bpred_unit.cc: src/cpu/o3/commit.cc: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/decode.cc: src/cpu/o3/fetch.cc: src/cpu/o3/iew.cc: src/cpu/o3/inst_queue.cc: src/cpu/o3/lsq.cc: src/cpu/o3/lsq_unit.cc: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/rename.cc: src/cpu/o3/rob.cc: use isa_specific.hh src/sim/process.cc: only initi NextNPC if not ALPHA src/cpu/o3/alpha/cpu.cc: alphao3cpu impl src/cpu/o3/alpha/cpu.hh: move AlphaTC to it's own file src/cpu/o3/alpha/cpu_impl.hh: Move AlphaTC to it's own file ... src/cpu/o3/alpha/dyn_inst.cc: src/cpu/o3/alpha/dyn_inst.hh: src/cpu/o3/alpha/dyn_inst_impl.hh: include paths src/cpu/o3/alpha/impl.hh: include paths, set default MaxThreads to 2 instead of 4 src/cpu/o3/alpha/params.hh: set Alpha Specific Params here src/python/m5/objects/O3CPU.py: add O3CPU class src/cpu/o3/SConscript: include isa-specific build files src/cpu/o3/alpha/thread_context.cc: NEW HOME of AlphaTC src/cpu/o3/alpha/thread_context.hh: new home of AlphaTC src/cpu/o3/isa_specific.hh: includes ISA specific files src/cpu/o3/params.hh: base o3 params src/cpu/o3/thread_context.hh: base o3 thread context src/cpu/o3/thread_context_impl.hh: base o3 thead context impl |
| /gem5/tests/configs/ | ||
| H A D | realview-simple-atomic.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
| H A D | pc-simple-timing.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
| H A D | pc-o3-timing.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
| H A D | realview-simple-timing.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
| H A D | tsunami-o3-dual.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
| H A D | tsunami-o3.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
| H A D | realview-o3-dual.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
| H A D | realview-o3.py | 9826:014ff1fbff6d Mon Aug 19 03:52:00 EDT 2013 Andreas Hansson <andreas.hansson@arm.com> config: Move the memory instantiation outside FSConfig This patch moves the instantiation of the memory controller outside FSConfig and instead relies on the mem_ranges to pass the information to the caller (e.g. fs.py or one of the regression scripts). The main motivation for this change is to expose the structural composition of the memory system and allow more tuning and configuration without adding a large number of options to the makeSystem functions. The patch updates the relevant example scripts to maintain the current functionality. As the order that ports are connected to the memory bus changes (in certain regresisons), some bus stats are shuffled around. For example, what used to be layer 0 is now layer 1. Going forward, options will be added to support the addition of multi-channel memory controllers. |
| /gem5/system/alpha/console/ | ||
| H A D | console.c | 7977:60051d2262c2 Fri Nov 14 10:52:00 EST 2003 Lisa Hsu <hsul@eecs.umich.edu> Import changeset |
| /gem5/src/sim/ | ||
| H A D | stat_control.cc | 4078:3f73f808bbd4 Sun Feb 18 01:52:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Statistics and Statreset ParamContexts, and expose all of the relevant functionality to python. Clean up the mysql code while we're at it. |
| /gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/ | ||
| H A D | stats.txt | 8983:8800b05e1cb3 Wed May 09 14:52:00 EDT 2012 Nathan Binkert <nate@binkert.org> stats: update stats for no_value -> nan Lots of accumulated older changes too. |
| /gem5/src/arch/alpha/ | ||
| H A D | faults.hh | 11294:a368064a2ab5 Mon Jan 11 05:52:00 EST 2016 Andreas Hansson <andreas.hansson@arm.com> scons: Enable -Wextra by default Make best use of the compiler, and enable -Wextra as well as -Wall. There are a few issues that had to be resolved, but they are all trivial. |
| H A D | SConscript | 9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change. |
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