Searched hist:2014 (Results 926 - 950 of 1681) sorted by relevance

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/gem5/src/arch/arm/
H A Ddecoder.cc10611:3bba9f2d0c7d Tue Dec 23 09:31:00 EST 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm: Raise an alignment fault if a PC has illegal alignment

We currently don't handle unaligned PCs correctly. There is one check
for unaligned PCs in the TLB when running in aarch64 mode, but this
check does not cover cases where the CPU does not do a TLB lookup when
decoding an instruction (e.g., a branch stays within the same cache
line). Additionally, the Decoder class sometimes throws an assertion
for unaligned PCs which breaks speculation.

This changeset introduces a decoder fault bit field in the ExtMachInst
structure. This field can be used to signal a decoder failure. If set,
the decoder generates an internal gem5fault instruction instead of a
normal instruction. This instruction in turns either panics (fault
type PANIC), returns an PCAlignmentFault (fault type UNALIGNED,
aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32).

The patch causes minor changes to the realview64 regressions, and a
stats bump will follow.
10610:5fae03bd840a Tue Dec 23 09:31:00 EST 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm: Clean up and document decoder API

This changeset adds more documentation to the ArmISA::Decoder class
and restructures it slightly to make API groups more obvious.
10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
/gem5/src/arch/arm/isa/insts/
H A Dneon64.isa10474:799c8ee4ecba Thu Oct 16 05:49:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arch: Use shared_ptr for all Faults

This patch takes quite a large step in transitioning from the ad-hoc
RefCountingPtr to the c++11 shared_ptr by adopting its use for all
Faults. There are no changes in behaviour, and the code modifications
are mostly just replacing "new" with "make_shared".
10197:a60405212dea Fri May 09 18:58:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> arm: add preliminary ISA splits for ARM arch
10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
/gem5/src/mem/
H A DCommMonitor.py10615:cd8aae15f89a Tue Dec 23 09:31:00 EST 2014 Kanishk Sugand <kanishk.sugand@arm.com> mem: Add stack distance statistics to the CommMonitor

This patch adds the stack distance calculator to the CommMonitor. The
stats are disabled by default.
10189:94d6ffac1e9b Fri May 09 18:58:00 EDT 2014 Sascha Bischoff <sascha.bischoff@ARM.com> mem: Auto-generate CommMonitor trace file names

Splits the CommMonitor trace_file parameter into three parameters. Previously,
the trace was only enabled if the trace_file parameter was set, and would be
written to this file. This patch adds in a trace_enable and trace_compress
parameter to the CommMonitor.

No trace is generated if trace_enable is set to False. If it is set to True, the
trace is written to a file based on the name of the SimObject in the simulation
hierarchy. For example, system.cluster.il1_commmonitor.trc. This filename can be
overridden by additionally specifying a file name to the trace_file parameter
(more on this later).

The trace_compress parameter will append .gz to any filename if set to True.
This enables compression of the generated traces. If the file name already ends
in .gz, then no changes are made.

The trace_file parameter will override the name set by the trace_enable
parameter. In the case that the specified name does not end in .gz but
trace_compress is set to true, .gz is appended to the supplied file name.
10129:eb34ae5204b8 Sun Mar 23 11:11:00 EDT 2014 Sascha Bischoff <Sascha.Bischoff@ARM.com> mem: CommMonitor trace warn on non-timing mode

Add a warning to the CommMonitor which will alert the user if they try
and record a trace when the system is not in timing mode.
H A Dexternal_slave.cc10563:755b18321206 Tue Dec 02 06:07:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add const getters for write packet data

This patch takes a first step in tightening up how we use the data
pointer in write packets. A const getter is added for the pointer
itself (getConstPtr), and a number of member functions are also made
const accordingly. In a range of places throughout the memory system
the new member is used.

The patch also removes the unused isReadWrite function.
10559:62f5f7363197 Mon Nov 24 09:03:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> misc: Another round of static analysis fixups

Mostly addressing uninitialised members.
10478:7135f938ff28 Thu Oct 16 05:49:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> mem: Add ExternalMaster and ExternalSlave ports

This patch adds two MemoryObject's: ExternalMaster and ExternalSlave.
Each object has a single port which can be bound to an externally-
provided bridge to a port of another simulation system at
initialisation.
H A DSConscript10614:da37aec3ed1a Tue Dec 23 09:31:00 EST 2014 Kanishk Sugand <kanishk.sugand@arm.com> mem: Add a stack distance calculator

This patch adds a stand-alone stack distance calculator. The stack
distance calculator is a passive SimObject that observes the addresses
passed to it. It calculates stack distances (LRU Distances) of
incoming addresses based on the partial sum hierarchy tree algorithm
described by Alamasi et al. http://doi.acm.org/10.1145/773039.773043.

For each transaction a hashtable look-up is performed. At every
non-unique transaction the tree is traversed from the leaf at the
returned index to the root, the old node is deleted from the tree, and
the sums (to the right) are collected and decremented. The collected
sum represets the stack distance of the found node. At every unique
transaction the stack distance is returned as
numeric_limits<uint64>::max().

In addition to the basic stack distance calculation, a feature to mark
an old node in the tree is added. This is useful if it is required to
see the reuse pattern. For example, Writebacks to the lower level
(e.g. membus from L2), can be marked instead of being removed from the
stack (isMarked flag of Node set to True). And then later if this same
address is accessed (by L1), the value of the isMarked flag would be
True. This gives some insight on how the Writeback policy of the
lower level affect the read/write accesses in an application.

Debugging is enabled by setting the verify flag to true. Debugging is
implemented using a dummy stack that behaves in a naive way, using STL
vectors. Note that this has a large impact on run time.
10612:6332c9d471a8 Tue Dec 23 09:31:00 EST 2014 Marco Elver <Marco.Elver@ARM.com> mem: Add MemChecker and MemCheckerMonitor

This patch adds the MemChecker and MemCheckerMonitor classes. While
MemChecker can be integrated anywhere in the system and is independent,
the most convenient usage is through the MemCheckerMonitor -- this
however, puts limitations on where the MemChecker is able to observe
read/write transactions.
10478:7135f938ff28 Thu Oct 16 05:49:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> mem: Add ExternalMaster and ExternalSlave ports

This patch adds two MemoryObject's: ExternalMaster and ExternalSlave.
Each object has a single port which can be bound to an externally-
provided bridge to a port of another simulation system at
initialisation.
10431:d9415c7f61a9 Tue Jul 29 12:29:00 EDT 2014 Omar Naji <Omar.Naji@arm.com> mem: Add DRAMPower wrapping class

This patch adds a class to wrap DRAMPower Library in gem5.
This class initiates an object of class MemorySpecification
of the DRAMPower Library, passes the parameters from DRAMCtrl.py
to this object and creates an object of drampower library using
the memory specification.
10405:7a618c07e663 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Rename Bus to XBar to better reflect its behaviour

This patch changes the name of the Bus classes to XBar to better
reflect the actual timing behaviour. The actual instances in the
config scripts are not renamed, and remain as e.g. iobus or membus.

As part of this renaming, the code has also been clean up slightly,
making use of range-based for loops and tidying up some comments. The
only changes outside the bus/crossbar code is due to the delay
variables in the packet.
10399:0644819fc32f Sat Sep 20 17:18:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> mem: Simple Snoop Filter

This is a first cut at a simple snoop filter that tracks presence of lines in
the caches "above" it. The snoop filter can be applied at any given cache
hierarchy and will then handle the caches above it appropriately; there is no
need to use this only in the last-level bus.

This design currently has some limitations: missing stats, no notion of clean
evictions (these will not update the underlying snoop filter, because they are
not sent from the evicting cache down), no notion of capacity for the snoop
filter and thus no need for invalidations caused by capacity pressure in the
snoop filter. These are planned to be added on top with future change sets.
10299:bec0c5ffc323 Thu Aug 28 11:11:00 EDT 2014 Alexandru <alexandru.dutu@amd.com> mem: adding architectural page table support for SE mode
This patch enables the use of page tables that are stored in system memory
and respect x86 specification, in SE mode. It defines an architectural
page table for x86 as a MultiLevelPageTable class and puts a placeholder
class for other ISAs page tables, giving the possibility for future
implementation.
10247:0ad233f0a77d Mon Jun 30 13:56:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: DRAMPower trace output

This patch adds a DRAMPower flag to enable off-line DRAM power
analysis using the DRAMPower tool. A new DRAMPower flag is added
and a follow-on patch adds a Python script to post-process the output
and order it based on time stamps.

The long-term goal is to link DRAMPower as a library and provide the
commands through function calls to the model rather than first
printing and then parsing the commands. At the moment it is also up to
the user to ensure that the same DRAM configuration is used by the
gem5 controller model and DRAMPower.
10208:c249f7660eb7 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add DRAM power states to the controller

This patch adds power states to the controller. These states and the
transitions can be used together with the Micron power model. As a
more elaborate use-case, the transitions can be used to drive the
DRAMPower tool.

At the moment, the power-down modes are not used, and this patch
simply serves to capture the idle, auto refresh and active modes. The
patch adds a third state machine that interacts with the refresh state
machine.
10146:27dfed4c8403 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Rename SimpleDRAM to a more suitable DRAMCtrl

This patch renames the not-so-simple SimpleDRAM to a more suitable
DRAMCtrl. The name change is intended to ensure that we do not send
the wrong message (although the "simple" in SimpleDRAM was originally
intended as in cleverly simple, or elegant).

As the DRAM controller modelling work is being presented at ISPASS'14
our hope is that a broader audience will use the model in the future.
/gem5/src/arch/x86/
H A Dcpuid.cc10552:41ebfed1dc89 Sun Nov 23 21:01:00 EST 2014 Alexandru Dutu <alexandru.dutu@amd.com> cpuid, x86: Enabling more features in CPUid
Adding more features in the CPUid with the purpose of supporting running the
KvmCPU in SE mode.
10539:cd107abe79dd Mon Nov 17 02:12:00 EST 2014 Gabe Black <gabeblack@google.com> x86: Fix the CPUID Long Mode Address Size function.

The value in EAX has an 8 bit field for the linear address size and one for
the physical address size when calling that function. A recent change
implemented it but returned 0xff for both of those fields. That implies that
linear and physical addresses are 255 bits wide which is wrong. When using the
KVM CPU model this causes an error, presumably because some of those bits are
actually reserved, or the CPU or kernel realizes 255 bits is a bad value.

This change makes those values 48.
10439:1bd64b294fe4 Fri Jun 13 04:48:00 EDT 2014 Jiuyue Ma <majiuyue@ncic.ac.cn> x86: add LongModeAddressSize function to cpuid

LongModeAddressSize was used by kernel 2.6.28.4 for physical address
validation, if not properly implemented, PCI resource allocation may
failed because of ioremap failed:

- linux-2.6.28.4/arch/x86/mm/ioremap.c:27-30
27 static inline int phys_addr_valid(unsigned long addr)
28 {
29 return addr < (1UL << boot_cpu_data.x86_phys_bits);
30 }

- linux-2.6.28.4/arch/x86/kernel/cpu/common.c:475-482
475 #ifdef CONFIG_X86_64
476 if (c->extended_cpuid_level >= 0x80000008) {
477 u32 eax = cpuid_eax(0x80000008);
478
479 c->x86_virt_bits = (eax >> 8) & 0xff;
480 c->x86_phys_bits = eax & 0xff;
481 }
482 #endif

- linux-2.6.28.4/arch/x86/mm/ioremap.c:209-214
209 if (!phys_addr_valid(phys_addr)) {
210 printk(KERN_WARNING "ioremap: invalid physical address %llx\n",
211 (unsigned long long)phys_addr);
212 WARN_ON_ONCE(1);
213 return NULL;
214 }

This patch return 0x0000ffff for LongModeAddressSize, which guarantee phys_addr_valid never failed.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
/gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/
H A Dstats.txt10530:533ec854b2f1 Tue Nov 11 15:17:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: changes to x86 o3 fs and sparc fs regression tests.
10411:d96740732a61 Sun Sep 21 23:04:00 EDT 2014 Steve Reinhardt <stever@gmail.com> stats: update t1000 stats for recent changes
10222:d51e31eef415 Mon May 12 17:22:00 EDT 2014 Steve Reinhardt <stever@gmail.com> tests: update t1000 & pc-switcheroo-full stats

committed reference config.json files too
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
10040:48a9e57de52e Mon Jan 27 14:30:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: update sparc fs stats
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/
H A Dsimout10517:ba51f8572571 Mon Nov 03 11:14:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update stats no match.

Bootloader I had on my sytem was an older version with a couple of
instruction differences.
10513:ca4438b6e39a Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> tests: Update regressions for the new kernels and various preceeding fixes.
10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/
H A Dstats.txt10488:7c27480a5031 Mon Oct 20 17:48:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to previous mmap and exit_group patches.
10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/20.parser/ref/x86/linux/simple-timing/
H A Dstats.txt10488:7c27480a5031 Mon Oct 20 17:48:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to previous mmap and exit_group patches.
10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/
H A Dstats.txt10488:7c27480a5031 Mon Oct 20 17:48:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to previous mmap and exit_group patches.
10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing/
H A Dstats.txt10488:7c27480a5031 Mon Oct 20 17:48:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to previous mmap and exit_group patches.
10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/
H A Dstats.txt10488:7c27480a5031 Mon Oct 20 17:48:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to previous mmap and exit_group patches.
10409:8c80b91944c5 Sat Sep 20 17:18:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for filter, crossbar and config changes

This patch bumps the stats to reflect the addition of the snoop filter
and snoop stats, the change from bus to crossbar, and the updates to
the ARM regressions that are now using a different CPU and cache
configuration. Lastly, some minor changes are expected due to the
activation cleanup of the CPUs.
10220:9eab5efc02e8 Fri May 09 18:58:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for the fixes, and mostly DRAM controller changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/src/mem/ruby/network/
H A DNetwork.cc10370:4466307b8a2a Mon Sep 15 17:19:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: revert some of the changes from ad9c042dce54
The changeset ad9c042dce54 made changes to the structures under the network
directory to use a map of buffers instead of vector of buffers.
The reasoning was that not all vnets that are created are used and we
needlessly allocate more buffers than required and then iterate over them
while processing network messages. But the move to map resulted in a slow
down which was pointed out by Andreas Hansson. This patch moves things
back to using vector of message buffers.
10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes

This patch is the final patch in a series of patches. The aim of the series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is ready
to make significant changes to the coherence protocol). Moreover the buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.

This patch makes changes so that these connections will now be made in the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and output.
So, the patch makes these buffers configurable members of the machines.

The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been modified to
take care of allocating the actual message buffer. This is inline with how
other port connections work.
10303:71e0934af9f1 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: move getNumNodes() to base class
All the implementations were doing the same things.
10086:bd1089db3a88 Sun Feb 23 20:16:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove few not required #includes
10076:f81d94b53661 Thu Feb 20 18:27:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: removes unused code.
/gem5/src/mem/ruby/slicc_interface/
H A DRubySlicc_Util.hh10563:755b18321206 Tue Dec 02 06:07:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add const getters for write packet data

This patch takes a first step in tightening up how we use the data
pointer in write packets. A const getter is added for the pointer
itself (getConstPtr), and a number of member functions are also made
const accordingly. In a range of places throughout the memory system
the new member is used.

The patch also removes the unused isReadWrite function.
10562:b99fdc295c34 Tue Dec 02 06:07:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Remove null-check bypassing in Packet::getPtr

This patch removes the parameter that enables bypassing the null check
in the Packet::getPtr method. A number of call sites assume the value
to be non-null.

The one odd case is the RubyTester, which issues zero-sized
prefetches(!), and despite being reads they had no valid data
pointer. This is now fixed, but the size oddity remains (unless anyone
object or has any good suggestions).

Finally, in the Ruby Sequencer, appropriate checks are made for flush
packets as they have no valid data pointer.
10348:c91b23c72d5e Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> base: Use the global Mersenne twister throughout

This patch tidies up random number generation to ensure that it is
done consistently throughout the code base. In essence this involves a
clean-up of Ruby, and some code simplifications in the traffic
generator.

As part of this patch a bunch of skewed distributions (off-by-one etc)
have been fixed.

Note that a single global random number generator is used, and that
the object instantiation order will impact the behaviour (the sequence
of numbers will be unaffected, but if module A calles random before
module B then they would obviously see a different outcome). The
dependency on the instantiation order is true in any case due to the
execution-model of gem5, so we leave it as is. Also note that the
global ranom generator is not thread safe at this point.

Regressions using the memtest, TrafficGen or any Ruby tester are
affected and will be updated accordingly.
10302:0e9e99e6369a Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: eliminate type Time
There is another type Time in src/base class which results in a conflict.
10086:bd1089db3a88 Sun Feb 23 20:16:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove few not required #includes
H A DAbstractController.hh10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller
This patch is the final in the series. The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system. This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs. Classic's memory controller is more up to date and
supports multiple different types of DRAM. This also brings classic and
ruby ever more close. The patch also changes ruby's memory controller to
expose the same interface.
10523:5777a3e55603 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove the function functionalReadBuffers()
This function was added when I had incorrectly arrived at the conclusion
that such a function can improve the chances of a functional read succeeding.
As was later realized, this is not possible in the current setup. While the
code using this function was dropped long back, this function was not. Hence
the patch.
10522:13312d6e1caf Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: coherence protocols: remove data block from dirctory entry
This patch removes the data block present in the directory entry structure
of each protocol in gem5's mainline. Firstly, this is required for moving
towards common set of memory controllers for classic and ruby memory systems.
Secondly, the data block was being misused in several places. It was being
used for having free access to the physical memory instead of calling on the
memory controller.

From now on, the directory controller will not have a direct visibility into
the physical memory. The Memory Vector object now resides in the
Memory Controller class. This also means that some significant changes are
being made to the functional accesses in ruby.
10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes

This patch is the final patch in a series of patches. The aim of the series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is ready
to make significant changes to the coherence protocol). Moreover the buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.

This patch makes changes so that these connections will now be made in the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and output.
So, the patch makes these buffers configurable members of the machines.

The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been modified to
take care of allocating the actual message buffer. This is inline with how
other port connections work.
10304:a2f88c6d9e54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove unused toString() from AbstractController
10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures

The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures. This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.

The directory ruby/systems has the glue code that holds these structures
together.
10096:e0167dda38dc Sun Mar 02 00:59:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: make the max_size variable of the MessageBuffer unsigned
10087:86f3b546c214 Sun Feb 23 20:16:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffer: refactor code
Code in two of the functions was exactly the same. This patch moves
this code to a new function which is called from the two functions
mentioned initially.
10078:9400a90ec5d1 Thu Feb 20 18:27:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: controller: slight code refactoring
10012:ec5a5bfb941d Fri Jan 10 17:19:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move all statistics to stats.txt, eliminate ruby.stats
/gem5/src/arch/arm/isa/formats/
H A Dmisc.isa10506:aa23216161fa Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm: Mark some miscregs (timer counter) registers at unverifiable.

The checker can't verify timer registers, so it should just grab the version
from the executing CPU, otherwise it could get a larger value and diverge
execution.
10420:cc13df09fa55 Wed Oct 01 08:05:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arm: More UBSan cleanups after additional full-system runs

Some incorrect casting to IntRegIndex, and a few uninitialized members
in the i8254xGBe device.
10418:7a76e13f0101 Sat Sep 27 09:08:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> arm: Fixed undefined behaviours identified by gcc

This patch fixes the runtime errors highlighted by the undefined
behaviour sanitizer. In the end there were two issues. First, when
rotating an immediate, we ended up shifting an uint32_t by 32 in some
cases. This case is fixed by checking for a rotation by 0
positions. Second, the Mrc15 and Mcr15 are operating on an IntReg and
a MiscReg, but we used the type RegRegImmOp and passed a MiscRegIndex
as an IntRegIndex. This issue is resolved by introducing a
MiscRegRegImmOp and RegMiscRegImmOp with the appropriate types.

With these fixes there are no runtime errors identified for the full
ARM regressions.
10173:a6402a046e36 Wed Apr 23 05:18:00 EDT 2014 Mitchell Hayenga <Mitchell.Hayenga@ARM.com> arm: Don't use a stack allocated mnemonic

FailUnimplemented passed a stack created mnemonic as a const char * which
causes some grief when the stack goes away.
10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
/gem5/util/
H A Dcpt_upgrader.py10338:8bee5f4edb92 Tue Apr 29 17:05:00 EDT 2014 Curtis Dunham <Curtis.Dunham@arm.com> arm: use condition code registers for ARM ISA

Analogous to ee049bf (for x86). Requires a bump of the checkpoint version
and corresponding upgrader code to move the condition code register values
to the new register file.
10285:6cb378bad253 Wed Feb 05 17:17:00 EST 2014 Curtis Dunham <Curtis.Dunham@arm.com> sim: bump checkpoint version for multiple event queues

This patch adds a fix for older checkpoints before support for
multiple event queues were added in changeset 2cce74fe359e. The change
in checkpoint version should really hav ebeen part of the
aforementioned changeset.
10250:9f5e9bdc2f27 Tue Jul 01 11:58:00 EDT 2014 Radhika Jagtap <radhika.jagtap@ARM.com> util: Add DVFS perfLevel to checkpoint upgrade script

This patch updates the checkpoint upgrader script. It adds the _perfLevel
variable in the clock domain and voltage domain simObjects used for DVFS.
10163:e8608cdddae2 Sat Apr 19 10:00:00 EDT 2014 Marco Elver <marco.elver@ed.ac.uk> ruby: recorder: Fix (de-)serializing with different cache block-sizes

Upon aggregating records, serialize system's cache-block size, as the
cache-block size can be different when restoring from a checkpoint. This way,
we can correctly read all records when restoring from a checkpoints, even if
the cache-block size is different.

Note, that it is only possible to restore from a checkpoint if the
desired cache-block size is smaller or equal to the cache-block size
when the checkpoint was taken; we can split one larger request into
multiple small ones, but it is not reliable to do the opposite.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
10037:5cac77888310 Fri Jan 24 16:29:00 EST 2014 ARM gem5 Developers arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black
/gem5/tests/configs/
H A Dpc-simple-timing-ruby.py10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller
This patch is the final in the series. The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system. This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs. Classic's memory controller is more up to date and
supports multiple different types of DRAM. This also brings classic and
ruby ever more close. The patch also changes ruby's memory controller to
expose the same interface.
10519:7a3ad4b09ce4 Thu Nov 06 06:41:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: single physical memory in fs mode
Both ruby and the system used to maintain memory copies. With the changes
carried for programmed io accesses, only one single memory is required for
fs simulations. This patch sets the copy of memory that used to reside
with the system to null, so that no space is allocated, but address checks
can still be carried out. All the memory accesses now source and sink values
to the memory maintained by ruby.
10120:f5ceb3c3edb6 Thu Mar 20 10:14:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> config: ruby: rename _cpu_ruby_ports to _cpu_ports
10118:5e1f04b4d5e4 Thu Mar 20 09:03:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> config: remove ruby_fs.py

The patch removes the ruby_fs.py file. The functionality is being moved to
fs.py. This would being ruby fs simulations in line with how ruby se
simulations are started (using --ruby option). The alpha fs config functions
are being combined for classing and ruby memory systems. This required
renaming the piobus in ruby to iobus. So, we will have stats being renamed
in the stats file for ruby fs regression.
10090:4eec7bdde5b0 Sun Feb 23 20:16:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: route all packets through ruby port
Currently, the interrupt controller in x86 is connected to the io bus
directly. Therefore the packets between the io devices and the interrupt
controller do not go through ruby. This patch changes ruby port so that
these packets arrive at the ruby port first, which then routes them to their
destination. Note that the patch does not make these packets go through the
ruby network. That would happen in a subsequent patch.
/gem5/src/mem/ruby/
H A DSConscript10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller
This patch is the final in the series. The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system. This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs. Classic's memory controller is more up to date and
supports multiple different types of DRAM. This also brings classic and
ruby ever more close. The patch also changes ruby's memory controller to
expose the same interface.
10310:61c7f1d06575 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> build opts: add MI_example to NULL ISA
A later changeset changes the file src/python/swig/pyobject.cc to include
a header file that includes a header file generated at build time depending
on the PROTOCOL in use. Since NULL ISA was not specifying any protocol,
this resulted in compilation problems. Hence, the changeset.
10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures

The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures. This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.

The directory ruby/systems has the glue code that holds these structures
together.
10133:0749c3ec92f4 Sun Mar 23 11:11:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> ruby: Move Ruby debug flags to ruby dir and remove stale options

This patch moves the Ruby-related debug flags to the ruby
sub-directory, and also removes the state SConsopts that add the
no-longer-used NO_VECTOR_BOUNDS_CHECK.
10086:bd1089db3a88 Sun Feb 23 20:16:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: remove few not required #includes
/gem5/configs/common/
H A DMemConfig.py10620:74834c49fbbe Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> config: Expose the DRAM ranks as a command-line option

This patch gives the user direct influence over the number of DRAM
ranks to make it easier to tune the memory density without affecting
the bandwidth (previously the only means of scaling the device count
was through the number of channels).

The patch also adds some basic sanity checks to ensure that the number
of ranks is a power of two (since we rely on bit slices in the address
decoding).
10524:fff17530cef6 Thu Nov 06 06:42:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: interface with classic memory controller
This patch is the final in the series. The whole series and this patch in
particular were written with the aim of interfacing ruby's directory controller
with the memory controller in the classic memory system. This is being done
since ruby's memory controller has not being kept up to date with the changes
going on in DRAMs. Classic's memory controller is more up to date and
supports multiple different types of DRAM. This also brings classic and
ruby ever more close. The patch also changes ruby's memory controller to
expose the same interface.
10442:cd2daa931a54 Sat Oct 11 16:02:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> config: separate function for instantiating a memory controller
This patch moves code for instantiating a single memory controller from
the function config_mem() to a separate function. This is being done
so that memory controllers can be instantiated without assuming that
they will be attached to the system in a particular fashion.
10146:27dfed4c8403 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Rename SimpleDRAM to a more suitable DRAMCtrl

This patch renames the not-so-simple SimpleDRAM to a more suitable
DRAMCtrl. The name change is intended to ensure that we do not send
the wrong message (although the "simple" in SimpleDRAM was originally
intended as in cleverly simple, or elegant).

As the DRAM controller modelling work is being presented at ISPASS'14
our hope is that a broader audience will use the model in the future.
10136:ba1ed063e3af Sun Mar 23 11:11:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: More descriptive address-mapping scheme names

This patch adds the row bits to the name of the address mapping
schemes to make it more clear that all the current schemes places the
row bits as the most significant bits.
10066:06a33d872798 Tue Feb 18 05:50:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add a wrapped DRAMSim2 memory controller

This patch adds DRAMSim2 as a memory controller by wrapping the
external library and creating a sublass of AbstractMemory that bridges
between the semantics of gem5 and the DRAMSim2 interface.

The DRAMSim2 wrapper extracts the clock period from the config
file. There is no way of extracting this information from DRAMSim2
itself, so we simply read the same config file and get it from there.

To properly model the response queue, the wrapper keeps track of how
many transactions are in the actual controller, and how many are
stacking up waiting to be sent back as responses (in the wrapper). The
latter requires us to move away from the queued port and manage the
packets ourselves. This is due to DRAMSim2 not having any flow control
on the response path.

DRAMSim2 assumes that the transactions it is given are matching the
burst size of the choosen memory. The wrapper checks to ensure the
cache line size of the system matches the burst size of DRAMSim2 as
there are currently no provisions to split the system requests. In
theory we could allow a cache line size smaller than the burst size,
but that would lead to inefficient use of the DRAM, so for not we
fatal also in this case.
10041:fae4550d2103 Mon Jan 27 19:50:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> config: allow more than 3GB of memory for x86 simulations
This patch edits the configuration files so that x86 simulations can have
more than 3GB of memory. It also corrects a bug in the MemConfig.py script.
/gem5/src/mem/ruby/network/simple/
H A DThrottle.cc10370:4466307b8a2a Mon Sep 15 17:19:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: revert some of the changes from ad9c042dce54
The changeset ad9c042dce54 made changes to the structures under the network
directory to use a map of buffers instead of vector of buffers.
The reasoning was that not all vnets that are created are used and we
needlessly allocate more buffers than required and then iterate over them
while processing network messages. But the move to map resulted in a slow
down which was pointed out by Andreas Hansson. This patch moves things
back to using vector of message buffers.
10311:ad9c042dce54 Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffers: significant changes

This patch is the final patch in a series of patches. The aim of the series
is to make ruby more configurable than it was. More specifically, the
connections between controllers are not at all possible (unless one is ready
to make significant changes to the coherence protocol). Moreover the buffers
themselves are magically connected to the network inside the slicc code.
These connections are not part of the configuration file.

This patch makes changes so that these connections will now be made in the
python configuration files associated with the protocols. This requires
each state machine to expose the message buffers it uses for input and output.
So, the patch makes these buffers configurable members of the machines.

The patch drops the slicc code that usd to connect these buffers to the
network. Now these buffers are exposed to the python configuration system
as Master and Slave ports. In the configuration files, any master port
can be connected any slave port. The file pyobject.cc has been modified to
take care of allocating the actual message buffer. This is inline with how
other port connections work.
10301:44839e8febbd Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: move files from ruby/system to ruby/structures

The directory ruby/system is crowded and unorganized. Hence, the files the
hold actual physical structures, are being moved to the directory
ruby/structures. This includes Cache Memory, Directory Memory,
Memory Controller, Wire Buffer, TBE Table, Perfect Cache Memory, Timer Table,
Bank Array.

The directory ruby/systems has the glue code that holds these structures
together.
10226:056363356d15 Fri May 23 07:07:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffer: drop dequeue_getDelayCycles()
The functionality of updating and returning the delay cycles would now be
performed by the dequeue() function itself.
10076:f81d94b53661 Thu Feb 20 18:27:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: network: removes unused code.
10074:0e013fa647ac Thu Feb 20 18:26:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> ruby: message buffer: removes some unecessary functions.
/gem5/src/base/
H A Dremote_gdb.hh10601:6efb37480d87 Sat Dec 06 01:37:00 EST 2014 Gabe Black <gabeblack@google.com> misc: Generalize GDB single stepping.

The new single stepping implementation for x86 doesn't rely on any ISA
specific properties or functionality. This change pulls out the per ISA
implementation of those functions and promotes the X86 implementation to the
base class.

One drawback of that implementation is that the CPU might stop on an
instruction twice if it's affected by both breakpoints and single stepping.
While that might be a little surprising, it's harmless and would only happen
under somewhat unlikely circumstances.
10599:910fc5624d68 Sat Dec 06 01:35:00 EST 2014 Gabe Black <gabeblack@google.com> misc: Add some utility functions for schedule inst commit events.

These can be used to simplify the implementation of single step in derived
classes.
10598:3d7653a2538b Sat Dec 06 01:34:00 EST 2014 Gabe Black <gabeblack@google.com> misc: Rename the GDB "Event" event class to InputEvent.

The "Event" name is the same as the base event class. That's a bit confusing,
and makes it a little awkward to add other event types.
10597:bd68c6838b9f Fri Dec 05 04:51:00 EST 2014 Gabe Black <gabeblack@google.com> sim: Ensure GDB interrupts the simulation at an instruction boundary.

Use the comInstEventQueue to ensure GDB interrupts the simulation at an
instruction boundary and not in the middle of a macroop, memory access, etc.
10595:25ecfc14f73f Fri Dec 05 04:44:00 EST 2014 Gabe Black <gabeblack@google.com> misc: Make the GDB register cache accessible in various sized chunks.

Not all ISAs have 64 bit sized registers, so it's not always very convenient
to access the GDB register cache in 64 bit sized chunks. This change makes it
accessible in 8, 16, 32, or 64 bit chunks. The MIPS and ARM implementations
were working around that limitation by bundling and unbundling 32 bit values
into 64 bit values. That code has been removed.
10589:5962812f80fe Wed Dec 03 06:27:00 EST 2014 Gabe Black <gabeblack@google.com> sim: Make it possible to override the breakpoint length check.

The check which makes sure the length of the breakpoint being written is the
same as a MachInst is only correct on fixed instruction width ISAs. Instead of
incorrectly applying that check to all ISAs, this change makes that the
default check and lets ISA specific GDB classes override it.
/gem5/src/mem/cache/prefetch/
H A Dstride.cc10627:63edd4a1243f Tue Dec 23 09:31:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> mem: Change prefetcher to use random_mt

Prefechers has used rand() to generate random numers previously.
10623:b9646f4546ad Tue Dec 23 09:31:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> mem: Rework the structuring of the prefetchers

Re-organizes the prefetcher class structure. Previously the
BasePrefetcher forced multiple assumptions on the prefetchers that
inherited from it. This patch makes the BasePrefetcher class truly
representative of base functionality. For example, the base class no
longer enforces FIFO order. Instead, prefetchers with FIFO requests
(like the existing stride and tagged prefetchers) now inherit from a
new QueuedPrefetcher base class.

Finally, the stride-based prefetcher now assumes a custimizable lookup table
(sets/ways) rather than the previous fully associative structure.
10054:baaed1733069 Thu Jan 30 00:21:00 EST 2014 Mitch Hayenga <mitch.hayenga+gem5@gmail.com> mem: Add additional tolerance to stride prefetcher
Forces the prefetcher to mispredict twice in a row before resetting the
confidence of prefetching. This helps cases where a load PC strides by a
constant factor, however it may operate on different arrays at times.
Avoids the cost of retraining. Primarily helps with small iteration loops.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
10053:b0b69dbafc08 Thu Jan 30 00:21:00 EST 2014 Mitch Hayenga <mitch.hayenga+gem5@gmail.com> mem: Allowed tagged instruction prefetching in stride prefetcher
For systems with a tightly coupled L2, a stride-based prefetcher may observe
access requests from both instruction and data L1 caches. However, the PC
address of an instruction miss gives no relevant training information to the
stride based prefetcher(there is no stride to train). In theses cases, its
better if the L2 stride prefetcher simply reverted back to a simple N-block
ahead prefetcher. This patch enables this option.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
10052:5bb8e054456b Thu Jan 30 00:21:00 EST 2014 Mitch Hayenga <mitch.hayenga+gem5@gmail.com>, Amin Farmahini <aminfar@gmail.com> mem: prefetcher: add options, support for unaligned addresses

This patch extends the classic prefetcher to work on non-block aligned
addresses. Because the existing prefetchers in gem5 mask off the lower
address bits of cache accesses, many predictable strides fail to be
detected. For example, if a load were to stride by 48 bytes, with 64 byte
cachelines, the current stride based prefetcher would see an access pattern
of 0, 64, 64, 128, 192.... Thus not detecting a constant stride pattern. This
patch fixes this, by training the prefetcher on access and not masking off the
lower address bits.

It also adds the following configuration options:
1) Training/prefetching only on cache misses,
2) Training/prefetching only on data acceses,
3) Optionally tagging prefetches with a PC address.
#3 allows prefetchers to train off of prefetch requests in systems with
multiple cache levels and PC-based prefetchers present at multiple levels.
It also effectively allows a pipelining of prefetch requests (like in POWER4)
across multiple levels of cache hierarchy.

Improves performance on my gem5 configuration by 4.3% for SPECINT and 4.7% for SPECFP (geomean).
10028:fb8c44de891a Fri Jan 24 16:29:00 EST 2014 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> mem: Add support for a security bit in the memory system

This patch adds the basic building blocks required to support e.g. ARM
TrustZone by discerning secure and non-secure memory accesses.
/gem5/src/cpu/minor/
H A Dexecute.cc10580:953d7b741619 Tue Dec 02 06:08:00 EST 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Fix memoryIssueLimit checking in Minor

This patch fixes the checking of the number of memory instructions issued
per cycles in the Minor CPU.
10563:755b18321206 Tue Dec 02 06:07:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Add const getters for write packet data

This patch takes a first step in tightening up how we use the data
pointer in write packets. A const getter is added for the pointer
itself (getConstPtr), and a number of member functions are also made
const accordingly. In a range of places throughout the memory system
the new member is used.

The patch also removes the unused isReadWrite function.
10527:d0c2ba70dc12 Thu Nov 06 06:42:00 EST 2014 Andrew Lukefahr <lukefahr@umich.edu> cpu: Minor Draining Bug

Fixes a bug where Minor drains in the midst of committing a
conditional store.

While committing a conditional store, lastCommitWasEndOfMacroop is true
(from the previous instruction) as we still haven't finished the conditional
store. If a drain occurs before the cache response, Minor would check just
lastCommitWasEndOfMacroop, which was true, and set drainState=DrainHaltFetch,
which increases the streamSeqNum. This caused the conditional store to be
squashed when the memory responded and it completed. However, to the memory
the store succeeded, while to the instruction sequence it never occurred.

In the case of an LLSC, the instruction sequence will replay the squashed
STREX, which will fail as the cache is no longer in LLSC. Then the
instruction sequence will loop back to a LDREX, which receives the updated
(incorrect) value.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
10464:2a0fe8bca031 Thu Oct 16 05:49:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> cpu: Probe points for basic PMU stats

This changeset adds probe points that can be used to implement PMU
counters for CPU stats. The following probes are supported:

* BaseCPU::ppCycles / Cycles
* BaseCPU::ppRetiredInsts / RetiredInsts
* BaseCPU::ppRetiredLoads / RetiredLoads
* BaseCPU::ppRetiredStores / RetiredStores
* BaseCPU::ppRetiredBranches RetiredBranches
10366:128c1ed03f4e Fri Sep 12 10:22:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> minor: Fix typo in DPRINTF for Minor branch prediction
10259:ebb376f73dd2 Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: `Minor' in-order CPU model

This patch contains a new CPU model named `Minor'. Minor models a four
stage in-order execution pipeline (fetch lines, decompose into
macroops, decompose macroops into microops, execute).

The model was developed to support the ARM ISA but should be fixable
to support all the remaining gem5 ISAs. It currently also works for
Alpha, and regressions are included for ARM and Alpha (including Linux
boot).

Documentation for the model can be found in src/doc/inside-minor.doxygen and
its internal operations can be visualised using the Minorview tool
utils/minorview.py.

Minor was designed to be fairly simple and not to engage in a lot of
instruction annotation. As such, it currently has very few gathered
stats and may lack other gem5 features.

Minor is faster than the o3 model. Sample results:

Benchmark | Stat host_seconds (s)
---------------+--------v--------v--------
(on ARM, opt) | simple | o3 | minor
| timing | timing | timing
---------------+--------+--------+--------
10.linux-boot | 169 | 1883 | 1075
10.mcf | 117 | 967 | 491
20.parser | 668 | 6315 | 3146
30.eon | 542 | 3413 | 2414
40.perlbmk | 2339 | 20905 | 11532
50.vortex | 122 | 1094 | 588
60.bzip2 | 2045 | 18061 | 9662
70.twolf | 207 | 2736 | 1036

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