Searched hist:2014 (Results 676 - 700 of 1681) sorted by relevance

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/gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/
H A Dconfig.ini10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/src/sim/
H A Ddvfs_handler.hh10398:d65768b9ffc2 Tue Aug 12 14:00:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> energy: Tighter checking of levels for DFS systems

There are cases where users might by accident / intention specify less voltage
operating points thatn frequency points. We consider one of these cases
special: giving only a single voltage to a voltage domain effectively renders
it as a static domain. This patch adds additional logic in the auxiliary parts
of the functionality to handle these cases properly (simple driver asking for
N>1 operating levels, we should return the same voltage for all of them) and
adds error checking code in the voltage domain.
10395:77b9f96786c1 Mon Jun 16 09:59:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> energy: Small extentions and fixes for DVFS handler

These additions allow easier interoperability with and querying from an
additional controller which will be in a separate patch. Also adding warnings
for changing the enabled state of the handler across checkpoint / resume and
deviating from the state in the configuration.

Contributed-by: Akash Bagdia <akash.bagdia@arm.com>
10360:919c02740209 Tue Sep 09 04:36:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> misc: Fix a number of unitialised variables and members

Static analysis unearther a bunch of uninitialised variables and
members, and this patch addresses the problem. In all cases these
omissions seem benign in the end, but at least fixing them means less
false positives next time round.
10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
H A Dvoltage_domain.cc11422:4f749e00b667 Tue Nov 18 09:00:00 EST 2014 Akash Bagdia <akash.bagdia@ARM.com> power: Add power states to ClockedObject

Add 4 power states to the ClockedObject, provides necessary access functions
to check and update the power state. Default power state is UNDEFINED, it is
responsibility of the respective simulation model to provide the startup state
and any other logic for state change.

Add number of transition stat.
Add distribution of time spent in clock gated state.
Add power state residency stat.

Add dump call back function to allow stats update of distribution and residency
stats.
10395:77b9f96786c1 Mon Jun 16 09:59:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> energy: Small extentions and fixes for DVFS handler

These additions allow easier interoperability with and querying from an
additional controller which will be in a separate patch. Also adding warnings
for changing the enabled state of the handler across checkpoint / resume and
deviating from the state in the configuration.

Contributed-by: Akash Bagdia <akash.bagdia@arm.com>
10249:6bbb7ae309ac Mon Jun 30 13:56:00 EDT 2014 Stephan Diestelhorst <stephan.diestelhorst@arm.com> power: Add basic DVFS support for gem5

Adds DVFS capabilities to gem5, by allowing users to specify lists for
frequencies and voltages in SrcClockDomains and VoltageDomains respectively.
A separate component, DVFSHandler, provides a small interface to change
operating points of the associated domains.

Clock domains will be linked to voltage domains and thus allow separate clock,
but shared voltage lines.

Currently all the valid performance-level updates are performed with a fixed
transition latency as specified for the domain.

Config file example:
...
vd = VoltageDomain(voltage = ['1V','0.95V','0.90V','0.85V'])
tsys.cluster1.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster2.clk_domain.clock = ['1GHz','700MHz','400MHz','230MHz']
tsys.cluster1.clk_domain.domain_id = 0
tsys.cluster2.clk_domain.domain_id = 1
tsys.cluster1.clk_domain.voltage_domain = vd
tsys.cluster2.clk_domain.voltage_domain = vd
tsys.dvfs_handler.domains = [tsys.cluster1.clk_domain,
tsys.cluster2.clk_domain]
tsys.dvfs_handler.enable = True
10022:db307bac42fc Fri Jan 24 16:29:00 EST 2014 Andreas Hansson <Andreas.Hansson@ARM.com> sim: Expose the current voltage for each object as a stat
H A Dpy_interact.cc10453:d0365cc3d05f Thu Oct 16 05:49:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> config: Add a --without-python option to build process

Add the ability to build libgem5 without embedded Python or the
ability to configure with Python.

This is a prelude to a patch to allow config.ini files to be loaded
into libgem5 using only C++ which would make embedding gem5 within
other simulation systems easier.

This adds a few registration interfaces to things which cross
between Python and C++. Namely: stats dumping and SimObject resolving
/gem5/tests/configs/
H A Dminor-timing-mp.py10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA

This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
H A Dminor-timing.py10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA

This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
H A Drealview-minor-dual.py10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA

This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
H A Drealview-minor.py10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA

This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
H A Drealview64-switcheroo-full.py10512:b423e1d0735e Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Update config files to more recent kernels and create 64-bit regressions.

This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.

In addition a set of 64-bit ARM regressions have been added to the regression system.
H A Drealview64-simple-timing-dual.py10512:b423e1d0735e Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Update config files to more recent kernels and create 64-bit regressions.

This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.

In addition a set of 64-bit ARM regressions have been added to the regression system.
H A Drealview64-minor-dual.py10512:b423e1d0735e Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Update config files to more recent kernels and create 64-bit regressions.

This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.

In addition a set of 64-bit ARM regressions have been added to the regression system.
H A Drealview64-simple-timing.py10512:b423e1d0735e Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Update config files to more recent kernels and create 64-bit regressions.

This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.

In addition a set of 64-bit ARM regressions have been added to the regression system.
H A Drealview64-minor.py10512:b423e1d0735e Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Update config files to more recent kernels and create 64-bit regressions.

This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.

In addition a set of 64-bit ARM regressions have been added to the regression system.
H A Drealview64-switcheroo-timing.py10512:b423e1d0735e Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Update config files to more recent kernels and create 64-bit regressions.

This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.

In addition a set of 64-bit ARM regressions have been added to the regression system.
H A Drealview64-switcheroo-o3.py10512:b423e1d0735e Thu Oct 30 00:18:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Update config files to more recent kernels and create 64-bit regressions.

This changes the default ARM system to a Versatile Express-like system that supports
2GB of memory and PCI devices and updates the default kernels/file-systems for
AArch64 ARM systems (64-bit) to support up to 32GB of memory and PCI devices. Some
platforms that are no longer supported have been pruned from the configuration files.

In addition a set of 64-bit ARM regressions have been added to the regression system.
H A Dtsunami-minor-dual.py10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA

This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
H A Dtsunami-minor.py10260:384d554cea8c Wed Jul 23 17:09:00 EDT 2014 Andrew Bardsley <Andrew.Bardsley@arm.com> cpu: Minor CPU add regression tests for ARM and ALPHA

This patch adds regression tests results and test harnesses
for the Minor CPU on ARM and ALPHA.
/gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/
H A Dstats.txt10628:c9b7e0c69f88 Tue Dec 23 09:31:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for decoder, TLB, prefetcher and DRAM changes

Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
10585:1c9d5d9417b3 Tue Dec 02 06:08:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for fixes, mostly TLB and WriteInvalidate
10576:de2979ff873a Tue Dec 02 06:08:00 EST 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Bump stats for o3 LSQ changes
10515:bd7c2aa12122 Thu Oct 30 00:50:00 EDT 2014 Ali Saidi <Ali.Saidi@ARM.com> arm, tests: Add 64-bit ARM regression tests
/gem5/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/
H A Dconfig.ini10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10411:d96740732a61 Sun Sep 21 23:04:00 EDT 2014 Steve Reinhardt <stever@gmail.com> stats: update t1000 stats for recent changes
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10222:d51e31eef415 Mon May 12 17:22:00 EDT 2014 Steve Reinhardt <stever@gmail.com> tests: update t1000 & pc-switcheroo-full stats

committed reference config.json files too
/gem5/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/
H A Dsimerr10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/
H A Dconfig.ini10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/10.mcf/ref/x86/linux/simple-timing/
H A Dsimerr10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/20.parser/ref/arm/linux/simple-atomic/
H A Dsimerr10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/
H A Dconfig.ini10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10242:cb4e86c17767 Sun Jun 22 17:33:00 EDT 2014 Steve Reinhardt <steve.reinhardt@amd.com> stats: update for O3 changes

Mostly small differences in total ticks, but O3 stall causes
shifted significantly.

30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes
/gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/
H A Dconfig.ini10451:3a87241adfb8 Sat Oct 11 17:18:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to changes to x86, stale configs.
10315:9e02c14446bb Mon Sep 01 17:55:00 EDT 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to recent ruby and x86 changes
Also updates many out of date config files.
10038:7eccd14e2610 Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for ARMv8 changes
10036:80e84beef3bb Fri Jan 24 16:29:00 EST 2014 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for cache occupancy and clock domain changes

Completed in 79 milliseconds

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