1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.341923 # Number of seconds simulated 4sim_ticks 47341923254000 # Number of ticks simulated 5final_tick 47341923254000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 198941 # Simulator instruction rate (inst/s) 8host_op_rate 237233 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 10723675807 # Simulator tick rate (ticks/s) 10host_mem_usage 786956 # Number of bytes of host memory used 11host_seconds 4414.71 # Real time elapsed on the host 12sim_insts 878265186 # Number of instructions simulated 13sim_ops 1047316960 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 242176 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 233728 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 4193568 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 18888648 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 25252160 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 159808 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 110720 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 3691360 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 11578384 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 16897024 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 434368 # Number of bytes read from this memory 28system.physmem.bytes_read::total 81681944 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 4193568 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 3691360 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 7884928 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 97721664 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 97742248 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 3784 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 3652 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 67077 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 295148 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 394565 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 2497 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1730 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 57721 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 180925 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 264016 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6787 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 1277902 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1526901 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1529475 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 5115 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 4937 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 88580 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 398984 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 533400 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 3376 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 2339 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 77972 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 244569 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 356915 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9175 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1725362 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 88580 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 77972 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 166553 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 2064168 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 435 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 2064602 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 2064168 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 5115 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 4937 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 88580 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 399418 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 533400 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 3376 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 2339 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 77972 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 244569 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 356915 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9175 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 3789964 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 1277902 # Number of read requests accepted 85system.physmem.writeReqs 1529475 # Number of write requests accepted 86system.physmem.readBursts 1277902 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1529475 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 81759232 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 26496 # Total number of bytes read from write queue 90system.physmem.bytesWritten 97740224 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 81681944 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 97742248 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 414 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2256 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 74308 # Per bank write bursts 97system.physmem.perBankRdBursts::1 87985 # Per bank write bursts 98system.physmem.perBankRdBursts::2 79775 # Per bank write bursts 99system.physmem.perBankRdBursts::3 80704 # Per bank write bursts 100system.physmem.perBankRdBursts::4 79279 # Per bank write bursts 101system.physmem.perBankRdBursts::5 87661 # Per bank write bursts 102system.physmem.perBankRdBursts::6 78349 # Per bank write bursts 103system.physmem.perBankRdBursts::7 78833 # Per bank write bursts 104system.physmem.perBankRdBursts::8 69442 # Per bank write bursts 105system.physmem.perBankRdBursts::9 78370 # Per bank write bursts 106system.physmem.perBankRdBursts::10 69793 # Per bank write bursts 107system.physmem.perBankRdBursts::11 81996 # Per bank write bursts 108system.physmem.perBankRdBursts::12 80451 # Per bank write bursts 109system.physmem.perBankRdBursts::13 82396 # Per bank write bursts 110system.physmem.perBankRdBursts::14 80116 # Per bank write bursts 111system.physmem.perBankRdBursts::15 88030 # Per bank write bursts 112system.physmem.perBankWrBursts::0 92185 # Per bank write bursts 113system.physmem.perBankWrBursts::1 101129 # Per bank write bursts 114system.physmem.perBankWrBursts::2 94103 # Per bank write bursts 115system.physmem.perBankWrBursts::3 97328 # Per bank write bursts 116system.physmem.perBankWrBursts::4 94264 # Per bank write bursts 117system.physmem.perBankWrBursts::5 99023 # Per bank write bursts 118system.physmem.perBankWrBursts::6 94391 # Per bank write bursts 119system.physmem.perBankWrBursts::7 95568 # Per bank write bursts 120system.physmem.perBankWrBursts::8 90026 # Per bank write bursts 121system.physmem.perBankWrBursts::9 95851 # Per bank write bursts 122system.physmem.perBankWrBursts::10 88927 # Per bank write bursts 123system.physmem.perBankWrBursts::11 96294 # Per bank write bursts 124system.physmem.perBankWrBursts::12 94934 # Per bank write bursts 125system.physmem.perBankWrBursts::13 97047 # Per bank write bursts 126system.physmem.perBankWrBursts::14 95210 # Per bank write bursts 127system.physmem.perBankWrBursts::15 100911 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 51774 # Number of times write queue was full causing retry 130system.physmem.totGap 47341921675500 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 0 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 2133 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 1275744 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1526901 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 505708 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 298665 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 136731 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 85460 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 55927 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 46831 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 42547 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 39408 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 35921 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 11095 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 6380 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 3835 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 2485 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 1956 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 1332 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 1133 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 952 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 753 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 214 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 132 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 14 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 5 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 2 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 1 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 1 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 24179 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 28209 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 39999 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 46492 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 52355 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 57811 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 64510 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 71167 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 77564 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 80217 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 85971 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 89992 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 89616 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 91327 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 98798 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 107236 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 96475 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 90527 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 10742 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 6106 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 4571 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 3497 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 2697 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 2502 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 2142 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 1954 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 1797 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 1675 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 1702 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 1596 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 1489 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 1728 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 1697 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 1857 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 2065 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 2040 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 2043 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 2289 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 2323 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 2551 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 2701 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 3106 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 3300 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 3341 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 3948 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 4411 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 6171 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 25276 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 121442 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 1170396 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 153.366156 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 102.854296 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 197.868960 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 748847 63.98% 63.98% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 241823 20.66% 84.64% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 67607 5.78% 90.42% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 29756 2.54% 92.96% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 24374 2.08% 95.05% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 14066 1.20% 96.25% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 9299 0.79% 97.04% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 7338 0.63% 97.67% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 27286 2.33% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 1170396 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 74463 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 17.155890 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 20.196232 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-255 74449 99.98% 99.98% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::256-511 8 0.01% 99.99% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::512-767 3 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::768-1023 2 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes 263system.physmem.rdPerTurnAround::total 74463 # Reads before turning the bus around for writes 264system.physmem.wrPerTurnAround::samples 74463 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::mean 20.509394 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::gmean 17.370303 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::stdev 552.030208 # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::0-4095 74461 100.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::40960-45055 1 0.00% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::143360-147455 1 0.00% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::total 74463 # Writes before turning the bus around for reads 272system.physmem.totQLat 79629370316 # Total ticks spent queuing 273system.physmem.totMemAccLat 103582270316 # Total ticks spent from burst creation until serviced by the DRAM 274system.physmem.totBusLat 6387440000 # Total ticks spent in databus transfers 275system.physmem.avgQLat 62332.77 # Average queueing delay per DRAM burst 276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 277system.physmem.avgMemAccLat 81082.77 # Average memory access latency per DRAM burst 278system.physmem.avgRdBW 1.73 # Average DRAM read bandwidth in MiByte/s 279system.physmem.avgWrBW 2.06 # Average achieved write bandwidth in MiByte/s 280system.physmem.avgRdBWSys 1.73 # Average system read bandwidth in MiByte/s 281system.physmem.avgWrBWSys 2.06 # Average system write bandwidth in MiByte/s 282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 283system.physmem.busUtil 0.03 # Data bus utilization in percentage 284system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 285system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 286system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing 287system.physmem.avgWrQLen 25.79 # Average write queue length when enqueuing 288system.physmem.readRowHits 958718 # Number of row buffer hits during reads 289system.physmem.writeRowHits 675564 # Number of row buffer hits during writes 290system.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads 291system.physmem.writeRowHitRate 44.23 # Row buffer hit rate for writes 292system.physmem.avgGap 16863400.13 # Average gap between requests 293system.physmem.pageHitRate 58.27 # Row buffer hit rate, read and write combined 294system.physmem_0.actEnergy 4260723600 # Energy for activate commands per rank (pJ) 295system.physmem_0.preEnergy 2264628300 # Energy for precharge commands per rank (pJ) 296system.physmem_0.readEnergy 4618823160 # Energy for read commands per rank (pJ) 297system.physmem_0.writeEnergy 4008913020 # Energy for write commands per rank (pJ) 298system.physmem_0.refreshEnergy 30164687280.000008 # Energy for refresh commands per rank (pJ) 299system.physmem_0.actBackEnergy 41855751510 # Energy for active background per rank (pJ) 300system.physmem_0.preBackEnergy 1419463680 # Energy for precharge background per rank (pJ) 301system.physmem_0.actPowerDownEnergy 63813765750 # Energy for active power-down per rank (pJ) 302system.physmem_0.prePowerDownEnergy 36794590560 # Energy for precharge power-down per rank (pJ) 303system.physmem_0.selfRefreshEnergy 11286440815140 # Energy for self refresh per rank (pJ) 304system.physmem_0.totalEnergy 11475654576000 # Total energy per rank (pJ) 305system.physmem_0.averagePower 242.399417 # Core power per rank (mW) 306system.physmem_0.totalIdleTime 47246408217619 # Total Idle time Per DRAM Rank 307system.physmem_0.memoryStateTime::IDLE 2341242543 # Time in different power states 308system.physmem_0.memoryStateTime::REF 12803196000 # Time in different power states 309system.physmem_0.memoryStateTime::SREF 47010648524500 # Time in different power states 310system.physmem_0.memoryStateTime::PRE_PDN 95818811721 # Time in different power states 311system.physmem_0.memoryStateTime::ACT 80368685838 # Time in different power states 312system.physmem_0.memoryStateTime::ACT_PDN 139942793398 # Time in different power states 313system.physmem_1.actEnergy 4095910980 # Energy for activate commands per rank (pJ) 314system.physmem_1.preEnergy 2177024520 # Energy for precharge commands per rank (pJ) 315system.physmem_1.readEnergy 4502441160 # Energy for read commands per rank (pJ) 316system.physmem_1.writeEnergy 3963024000 # Energy for write commands per rank (pJ) 317system.physmem_1.refreshEnergy 30680370240.000008 # Energy for refresh commands per rank (pJ) 318system.physmem_1.actBackEnergy 42163353720 # Energy for active background per rank (pJ) 319system.physmem_1.preBackEnergy 1422051360 # Energy for precharge background per rank (pJ) 320system.physmem_1.actPowerDownEnergy 64060335210 # Energy for active power-down per rank (pJ) 321system.physmem_1.prePowerDownEnergy 38109219360 # Energy for precharge power-down per rank (pJ) 322system.physmem_1.selfRefreshEnergy 11285470021935 # Energy for self refresh per rank (pJ) 323system.physmem_1.totalEnergy 11476656465255 # Total energy per rank (pJ) 324system.physmem_1.averagePower 242.420579 # Core power per rank (mW) 325system.physmem_1.totalIdleTime 47245728134436 # Total Idle time Per DRAM Rank 326system.physmem_1.memoryStateTime::IDLE 2323672783 # Time in different power states 327system.physmem_1.memoryStateTime::REF 13022950000 # Time in different power states 328system.physmem_1.memoryStateTime::SREF 47006002235750 # Time in different power states 329system.physmem_1.memoryStateTime::PRE_PDN 99242546502 # Time in different power states 330system.physmem_1.memoryStateTime::ACT 80848444531 # Time in different power states 331system.physmem_1.memoryStateTime::ACT_PDN 140483404434 # Time in different power states 332system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 333system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 334system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 335system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 336system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 337system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 338system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 339system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 340system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 341system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory 342system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 343system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 344system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 345system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory 346system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 347system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 348system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 349system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 350system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 355system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 356system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 358system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 359system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 360system.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 361system.bridge.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 362system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 363system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 364system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 365system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 366system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 367system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 368system.cpu0.branchPred.lookups 135771616 # Number of BP lookups 369system.cpu0.branchPred.condPredicted 86347947 # Number of conditional branches predicted 370system.cpu0.branchPred.condIncorrect 6838936 # Number of conditional branches incorrect 371system.cpu0.branchPred.BTBLookups 91129477 # Number of BTB lookups 372system.cpu0.branchPred.BTBHits 54316721 # Number of BTB hits 373system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 374system.cpu0.branchPred.BTBHitPct 59.603899 # BTB Hit Percentage 375system.cpu0.branchPred.usedRAS 20002366 # Number of times the RAS was used to get a target. 376system.cpu0.branchPred.RASInCorrect 187416 # Number of incorrect RAS predictions. 377system.cpu0.branchPred.indirectLookups 4394152 # Number of indirect predictor lookups. 378system.cpu0.branchPred.indirectHits 2878401 # Number of indirect target hits. 379system.cpu0.branchPred.indirectMisses 1515751 # Number of indirect misses. 380system.cpu0.branchPredindirectMispredicted 382217 # Number of mispredicted indirect branches. 381system.cpu_clk_domain.clock 500 # Clock period in ticks 382system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 392system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 393system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 394system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 395system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 396system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 397system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 398system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 399system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 400system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 401system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 402system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 403system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 404system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 405system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 407system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 408system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 409system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 410system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 411system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 412system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 413system.cpu0.dtb.walker.walks 656993 # Table walker walks requested 414system.cpu0.dtb.walker.walksLong 656993 # Table walker walks initiated with long descriptors 415system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 15295 # Level at which table walker walks with long descriptors terminate 416system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 109934 # Level at which table walker walks with long descriptors terminate 417system.cpu0.dtb.walker.walksSquashedBefore 315620 # Table walks squashed before starting 418system.cpu0.dtb.walker.walkWaitTime::samples 341373 # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::mean 2464.513889 # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::stdev 14057.964276 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::0-65535 338378 99.12% 99.12% # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkWaitTime::65536-131071 2127 0.62% 99.75% # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::131072-196607 591 0.17% 99.92% # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::196608-262143 168 0.05% 99.97% # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::327680-393215 50 0.01% 100.00% # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::393216-458751 9 0.00% 100.00% # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::589824-655359 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::720896-786431 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::total 341373 # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkCompletionTime::samples 358442 # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::mean 21996.103972 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::gmean 18865.832829 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::stdev 18729.819330 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::0-65535 353579 98.64% 98.64% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::65536-131071 3217 0.90% 99.54% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::131072-196607 596 0.17% 99.71% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::196608-262143 697 0.19% 99.90% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::262144-327679 228 0.06% 99.97% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::327680-393215 58 0.02% 99.98% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::393216-458751 45 0.01% 99.99% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::458752-524287 6 0.00% 100.00% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::589824-655359 12 0.00% 100.00% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walkCompletionTime::total 358442 # Table walker service (enqueue to completion) latency 448system.cpu0.dtb.walker.walksPending::samples 470936013252 # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::mean 0.670912 # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::stdev 0.545830 # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::0-1 469324214752 99.66% 99.66% # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::2-3 904884000 0.19% 99.85% # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::4-5 330855500 0.07% 99.92% # Table walker pending requests distribution 454system.cpu0.dtb.walker.walksPending::6-7 151555000 0.03% 99.95% # Table walker pending requests distribution 455system.cpu0.dtb.walker.walksPending::8-9 116006500 0.02% 99.98% # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::10-11 57420000 0.01% 99.99% # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::12-13 24613500 0.01% 99.99% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::14-15 25389500 0.01% 100.00% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::16-17 1013500 0.00% 100.00% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::18-19 61000 0.00% 100.00% # Table walker pending requests distribution 461system.cpu0.dtb.walker.walksPending::total 470936013252 # Table walker pending requests distribution 462system.cpu0.dtb.walker.walkPageSizes::4K 109934 87.79% 87.79% # Table walker page sizes translated 463system.cpu0.dtb.walker.walkPageSizes::2M 15295 12.21% 100.00% # Table walker page sizes translated 464system.cpu0.dtb.walker.walkPageSizes::total 125229 # Table walker page sizes translated 465system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 656993 # Table walker requests started/completed, data/inst 466system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 467system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 656993 # Table walker requests started/completed, data/inst 468system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 125229 # Table walker requests started/completed, data/inst 469system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 470system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 125229 # Table walker requests started/completed, data/inst 471system.cpu0.dtb.walker.walkRequestOrigin::total 782222 # Table walker requests started/completed, data/inst 472system.cpu0.dtb.inst_hits 0 # ITB inst hits 473system.cpu0.dtb.inst_misses 0 # ITB inst misses 474system.cpu0.dtb.read_hits 107772870 # DTB read hits 475system.cpu0.dtb.read_misses 484010 # DTB read misses 476system.cpu0.dtb.write_hits 87417439 # DTB write hits 477system.cpu0.dtb.write_misses 172983 # DTB write misses 478system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 479system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 480system.cpu0.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID 481system.cpu0.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID 482system.cpu0.dtb.flush_entries 44511 # Number of entries that have been flushed from TLB 483system.cpu0.dtb.align_faults 282 # Number of TLB faults due to alignment restrictions 484system.cpu0.dtb.prefetch_faults 7018 # Number of TLB faults due to prefetch 485system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 486system.cpu0.dtb.perms_faults 39566 # Number of TLB faults due to permissions restrictions 487system.cpu0.dtb.read_accesses 108256880 # DTB read accesses 488system.cpu0.dtb.write_accesses 87590422 # DTB write accesses 489system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 490system.cpu0.dtb.hits 195190309 # DTB hits 491system.cpu0.dtb.misses 656993 # DTB misses 492system.cpu0.dtb.accesses 195847302 # DTB accesses 493system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 494system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 501system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 502system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 503system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 504system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 505system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 506system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 507system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 508system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 509system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 510system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 511system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 512system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 513system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 514system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 515system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 516system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 517system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 518system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 519system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 520system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 521system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 522system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 523system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 524system.cpu0.itb.walker.walks 88518 # Table walker walks requested 525system.cpu0.itb.walker.walksLong 88518 # Table walker walks initiated with long descriptors 526system.cpu0.itb.walker.walksLongTerminationLevel::Level2 982 # Level at which table walker walks with long descriptors terminate 527system.cpu0.itb.walker.walksLongTerminationLevel::Level3 60760 # Level at which table walker walks with long descriptors terminate 528system.cpu0.itb.walker.walksSquashedBefore 10909 # Table walks squashed before starting 529system.cpu0.itb.walker.walkWaitTime::samples 77609 # Table walker wait (enqueue to first request) latency 530system.cpu0.itb.walker.walkWaitTime::mean 1509.006687 # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::stdev 11301.495781 # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkWaitTime::0-65535 77034 99.26% 99.26% # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkWaitTime::65536-131071 519 0.67% 99.93% # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::131072-196607 33 0.04% 99.97% # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkWaitTime::196608-262143 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::327680-393215 8 0.01% 100.00% # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::524288-589823 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::total 77609 # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkCompletionTime::samples 72651 # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::mean 27149.240891 # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::gmean 23393.498423 # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::stdev 24986.363412 # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::0-65535 70103 96.49% 96.49% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::65536-131071 1723 2.37% 98.86% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::131072-196607 517 0.71% 99.58% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::196608-262143 199 0.27% 99.85% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.92% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::327680-393215 35 0.05% 99.97% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::393216-458751 7 0.01% 99.98% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::524288-589823 7 0.01% 99.99% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::total 72651 # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walksPending::samples 367854316648 # Table walker pending requests distribution 557system.cpu0.itb.walker.walksPending::mean 0.912736 # Table walker pending requests distribution 558system.cpu0.itb.walker.walksPending::stdev 0.282646 # Table walker pending requests distribution 559system.cpu0.itb.walker.walksPending::0 32141827252 8.74% 8.74% # Table walker pending requests distribution 560system.cpu0.itb.walker.walksPending::1 335673383896 91.25% 99.99% # Table walker pending requests distribution 561system.cpu0.itb.walker.walksPending::2 36841000 0.01% 100.00% # Table walker pending requests distribution 562system.cpu0.itb.walker.walksPending::3 2085000 0.00% 100.00% # Table walker pending requests distribution 563system.cpu0.itb.walker.walksPending::4 179500 0.00% 100.00% # Table walker pending requests distribution 564system.cpu0.itb.walker.walksPending::total 367854316648 # Table walker pending requests distribution 565system.cpu0.itb.walker.walkPageSizes::4K 60760 98.41% 98.41% # Table walker page sizes translated 566system.cpu0.itb.walker.walkPageSizes::2M 982 1.59% 100.00% # Table walker page sizes translated 567system.cpu0.itb.walker.walkPageSizes::total 61742 # Table walker page sizes translated 568system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 569system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 88518 # Table walker requests started/completed, data/inst 570system.cpu0.itb.walker.walkRequestOrigin_Requested::total 88518 # Table walker requests started/completed, data/inst 571system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 572system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 61742 # Table walker requests started/completed, data/inst 573system.cpu0.itb.walker.walkRequestOrigin_Completed::total 61742 # Table walker requests started/completed, data/inst 574system.cpu0.itb.walker.walkRequestOrigin::total 150260 # Table walker requests started/completed, data/inst 575system.cpu0.itb.inst_hits 209275517 # ITB inst hits 576system.cpu0.itb.inst_misses 88518 # ITB inst misses 577system.cpu0.itb.read_hits 0 # DTB read hits 578system.cpu0.itb.read_misses 0 # DTB read misses 579system.cpu0.itb.write_hits 0 # DTB write hits 580system.cpu0.itb.write_misses 0 # DTB write misses 581system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 582system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 583system.cpu0.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID 584system.cpu0.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID 585system.cpu0.itb.flush_entries 31869 # Number of entries that have been flushed from TLB 586system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 587system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 588system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 589system.cpu0.itb.perms_faults 214657 # Number of TLB faults due to permissions restrictions 590system.cpu0.itb.read_accesses 0 # DTB read accesses 591system.cpu0.itb.write_accesses 0 # DTB write accesses 592system.cpu0.itb.inst_accesses 209364035 # ITB inst accesses 593system.cpu0.itb.hits 209275517 # DTB hits 594system.cpu0.itb.misses 88518 # DTB misses 595system.cpu0.itb.accesses 209364035 # DTB accesses 596system.cpu0.numPwrStateTransitions 11060 # Number of power state transitions 597system.cpu0.pwrStateClkGateDist::samples 5530 # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::mean 8500198165.069259 # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::stdev 152149510782.295166 # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::underflows 4198 75.91% 75.91% # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::1000-5e+10 1307 23.63% 99.55% # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.11% 99.66% # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.67% # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 2 0.04% 99.71% # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.73% # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.75% # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::4e+11-4.5e+11 1 0.02% 99.76% # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.78% # Distribution of time spent in the clock gated state 609system.cpu0.pwrStateClkGateDist::overflows 12 0.22% 100.00% # Distribution of time spent in the clock gated state 610system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 611system.cpu0.pwrStateClkGateDist::max_value 6914082541000 # Distribution of time spent in the clock gated state 612system.cpu0.pwrStateClkGateDist::total 5530 # Distribution of time spent in the clock gated state 613system.cpu0.pwrStateResidencyTicks::ON 335827401167 # Cumulative time (in ticks) in various power states 614system.cpu0.pwrStateResidencyTicks::CLK_GATED 47006095852833 # Cumulative time (in ticks) in various power states 615system.cpu0.numCycles 671656145 # number of cpu cycles simulated 616system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 617system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 618system.cpu0.fetch.icacheStallCycles 89746186 # Number of cycles fetch is stalled on an Icache miss 619system.cpu0.fetch.Insts 605326172 # Number of instructions fetch has processed 620system.cpu0.fetch.Branches 135771616 # Number of branches that fetch encountered 621system.cpu0.fetch.predictedBranches 77197488 # Number of branches that fetch has predicted taken 622system.cpu0.fetch.Cycles 539879458 # Number of cycles fetch has run and was not squashing or blocked 623system.cpu0.fetch.SquashCycles 14767666 # Number of cycles fetch has spent squashing 624system.cpu0.fetch.TlbCycles 2125862 # Number of cycles fetch has spent waiting for tlb 625system.cpu0.fetch.MiscStallCycles 314132 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 626system.cpu0.fetch.PendingTrapStallCycles 6298223 # Number of stall cycles due to pending traps 627system.cpu0.fetch.PendingQuiesceStallCycles 772099 # Number of stall cycles due to pending quiesce instructions 628system.cpu0.fetch.IcacheWaitRetryStallCycles 851881 # Number of stall cycles due to full MSHR 629system.cpu0.fetch.CacheLines 209041727 # Number of cache lines fetched 630system.cpu0.fetch.IcacheSquashes 1674502 # Number of outstanding Icache misses that were squashed 631system.cpu0.fetch.ItlbSquashes 29298 # Number of outstanding ITLB misses that were squashed 632system.cpu0.fetch.rateDist::samples 647371674 # Number of instructions fetched each cycle (Total) 633system.cpu0.fetch.rateDist::mean 1.105525 # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::stdev 1.248840 # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 636system.cpu0.fetch.rateDist::0 308576951 47.67% 47.67% # Number of instructions fetched each cycle (Total) 637system.cpu0.fetch.rateDist::1 127594651 19.71% 67.38% # Number of instructions fetched each cycle (Total) 638system.cpu0.fetch.rateDist::2 45508982 7.03% 74.41% # Number of instructions fetched each cycle (Total) 639system.cpu0.fetch.rateDist::3 165691090 25.59% 100.00% # Number of instructions fetched each cycle (Total) 640system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 641system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 642system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 643system.cpu0.fetch.rateDist::total 647371674 # Number of instructions fetched each cycle (Total) 644system.cpu0.fetch.branchRate 0.202145 # Number of branch fetches per cycle 645system.cpu0.fetch.rate 0.901244 # Number of inst fetches per cycle 646system.cpu0.decode.IdleCycles 102332613 # Number of cycles decode is idle 647system.cpu0.decode.BlockedCycles 273941666 # Number of cycles decode is blocked 648system.cpu0.decode.RunCycles 237936691 # Number of cycles decode is running 649system.cpu0.decode.UnblockCycles 27831297 # Number of cycles decode is unblocking 650system.cpu0.decode.SquashCycles 5329407 # Number of cycles decode is squashing 651system.cpu0.decode.BranchResolved 50359670 # Number of times decode resolved a branch 652system.cpu0.decode.BranchMispred 2095113 # Number of times decode detected a branch misprediction 653system.cpu0.decode.DecodedInsts 630187004 # Number of instructions handled by decode 654system.cpu0.decode.SquashedInsts 23557218 # Number of squashed instructions handled by decode 655system.cpu0.rename.SquashCycles 5329407 # Number of cycles rename is squashing 656system.cpu0.rename.IdleCycles 133079950 # Number of cycles rename is idle 657system.cpu0.rename.BlockCycles 61214716 # Number of cycles rename is blocking 658system.cpu0.rename.serializeStallCycles 153180346 # count of cycles rename stalled for serializing inst 659system.cpu0.rename.RunCycles 234286149 # Number of cycles rename is running 660system.cpu0.rename.UnblockCycles 60281106 # Number of cycles rename is unblocking 661system.cpu0.rename.RenamedInsts 612391061 # Number of instructions processed by rename 662system.cpu0.rename.SquashedInsts 6345537 # Number of squashed instructions processed by rename 663system.cpu0.rename.ROBFullEvents 11623022 # Number of times rename has blocked due to ROB full 664system.cpu0.rename.IQFullEvents 442390 # Number of times rename has blocked due to IQ full 665system.cpu0.rename.LQFullEvents 950471 # Number of times rename has blocked due to LQ full 666system.cpu0.rename.SQFullEvents 35105207 # Number of times rename has blocked due to SQ full 667system.cpu0.rename.FullRegisterEvents 13004 # Number of times there has been no free registers 668system.cpu0.rename.RenamedOperands 561787552 # Number of destination operands rename has renamed 669system.cpu0.rename.RenameLookups 866106072 # Number of register rename lookups that rename has made 670system.cpu0.rename.int_rename_lookups 720689595 # Number of integer rename lookups 671system.cpu0.rename.fp_rename_lookups 706575 # Number of floating rename lookups 672system.cpu0.rename.CommittedMaps 502207885 # Number of HB maps that are committed 673system.cpu0.rename.UndoneMaps 59579653 # Number of HB maps that are undone due to squashing 674system.cpu0.rename.serializingInsts 6816633 # count of serializing insts renamed 675system.cpu0.rename.tempSerializingInsts 4684361 # count of temporary serializing insts renamed 676system.cpu0.rename.skidInsts 58564314 # count of insts added to the skid buffer 677system.cpu0.memDep0.insertedLoads 107690406 # Number of loads inserted to the mem dependence unit. 678system.cpu0.memDep0.insertedStores 90791382 # Number of stores inserted to the mem dependence unit. 679system.cpu0.memDep0.conflictingLoads 10221267 # Number of conflicting loads. 680system.cpu0.memDep0.conflictingStores 8541253 # Number of conflicting stores. 681system.cpu0.iq.iqInstsAdded 598417989 # Number of instructions added to the IQ (excludes non-spec) 682system.cpu0.iq.iqNonSpecInstsAdded 7027379 # Number of non-speculative instructions added to the IQ 683system.cpu0.iq.iqInstsIssued 594218555 # Number of instructions issued 684system.cpu0.iq.iqSquashedInstsIssued 2775784 # Number of squashed instructions issued 685system.cpu0.iq.iqSquashedInstsExamined 55969109 # Number of squashed instructions iterated over during squash; mainly for profiling 686system.cpu0.iq.iqSquashedOperandsExamined 36418491 # Number of squashed operands that are examined and possibly removed from graph 687system.cpu0.iq.iqSquashedNonSpecRemoved 281604 # Number of squashed non-spec instructions that were removed 688system.cpu0.iq.issued_per_cycle::samples 647371674 # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::mean 0.917894 # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::stdev 1.123620 # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::0 341377364 52.73% 52.73% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::1 105270736 16.26% 68.99% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::2 121758490 18.81% 87.80% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::3 70435170 10.88% 98.68% # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::4 8524242 1.32% 100.00% # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::5 5671 0.00% 100.00% # Number of insts issued each cycle 698system.cpu0.iq.issued_per_cycle::6 1 0.00% 100.00% # Number of insts issued each cycle 699system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 700system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 701system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 702system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 703system.cpu0.iq.issued_per_cycle::max_value 6 # Number of insts issued each cycle 704system.cpu0.iq.issued_per_cycle::total 647371674 # Number of insts issued each cycle 705system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 706system.cpu0.iq.fu_full::IntAlu 65687551 45.22% 45.22% # attempts to use FU when none available 707system.cpu0.iq.fu_full::IntMult 64582 0.04% 45.27% # attempts to use FU when none available 708system.cpu0.iq.fu_full::IntDiv 15638 0.01% 45.28% # attempts to use FU when none available 709system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.28% # attempts to use FU when none available 710system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.28% # attempts to use FU when none available 711system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.28% # attempts to use FU when none available 712system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.28% # attempts to use FU when none available 713system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available 714system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.28% # attempts to use FU when none available 715system.cpu0.iq.fu_full::FloatMisc 12 0.00% 45.28% # attempts to use FU when none available 716system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.28% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.28% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.28% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.28% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.28% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.28% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.28% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.28% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.28% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.28% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.28% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.28% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.28% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.28% # attempts to use FU when none available 730system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.28% # attempts to use FU when none available 731system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.28% # attempts to use FU when none available 732system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.28% # attempts to use FU when none available 733system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 45.28% # attempts to use FU when none available 734system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.28% # attempts to use FU when none available 735system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.28% # attempts to use FU when none available 736system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.28% # attempts to use FU when none available 737system.cpu0.iq.fu_full::MemRead 38738584 26.67% 71.95% # attempts to use FU when none available 738system.cpu0.iq.fu_full::MemWrite 40389693 27.81% 99.76% # attempts to use FU when none available 739system.cpu0.iq.fu_full::FloatMemRead 34528 0.02% 99.78% # attempts to use FU when none available 740system.cpu0.iq.fu_full::FloatMemWrite 315988 0.22% 100.00% # attempts to use FU when none available 741system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 742system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 743system.cpu0.iq.FU_type_0::No_OpClass 70 0.00% 0.00% # Type of FU issued 744system.cpu0.iq.FU_type_0::IntAlu 392733469 66.09% 66.09% # Type of FU issued 745system.cpu0.iq.FU_type_0::IntMult 1547002 0.26% 66.35% # Type of FU issued 746system.cpu0.iq.FU_type_0::IntDiv 82083 0.01% 66.37% # Type of FU issued 747system.cpu0.iq.FU_type_0::FloatAdd 53 0.00% 66.37% # Type of FU issued 748system.cpu0.iq.FU_type_0::FloatCmp 15 0.00% 66.37% # Type of FU issued 749system.cpu0.iq.FU_type_0::FloatCvt 25 0.00% 66.37% # Type of FU issued 750system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.37% # Type of FU issued 751system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 66.37% # Type of FU issued 752system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.37% # Type of FU issued 753system.cpu0.iq.FU_type_0::FloatMisc 42153 0.01% 66.37% # Type of FU issued 754system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.37% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdAdd 2 0.00% 66.37% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.37% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.37% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.37% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.37% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.37% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.37% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.37% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.37% # Type of FU issued 764system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.37% # Type of FU issued 765system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.37% # Type of FU issued 766system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.37% # Type of FU issued 767system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.37% # Type of FU issued 768system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.37% # Type of FU issued 769system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.37% # Type of FU issued 770system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.37% # Type of FU issued 771system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.37% # Type of FU issued 772system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.37% # Type of FU issued 773system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.37% # Type of FU issued 774system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.37% # Type of FU issued 775system.cpu0.iq.FU_type_0::MemRead 111068257 18.69% 85.07% # Type of FU issued 776system.cpu0.iq.FU_type_0::MemWrite 88363067 14.87% 99.94% # Type of FU issued 777system.cpu0.iq.FU_type_0::FloatMemRead 53874 0.01% 99.94% # Type of FU issued 778system.cpu0.iq.FU_type_0::FloatMemWrite 328485 0.06% 100.00% # Type of FU issued 779system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 780system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 781system.cpu0.iq.FU_type_0::total 594218555 # Type of FU issued 782system.cpu0.iq.rate 0.884706 # Inst issue rate 783system.cpu0.iq.fu_busy_cnt 145246576 # FU busy when requested 784system.cpu0.iq.fu_busy_rate 0.244433 # FU busy rate (busy events/executed inst) 785system.cpu0.iq.int_inst_queue_reads 1982627676 # Number of integer instruction queue reads 786system.cpu0.iq.int_inst_queue_writes 661129837 # Number of integer instruction queue writes 787system.cpu0.iq.int_inst_queue_wakeup_accesses 575942513 # Number of integer instruction queue wakeup accesses 788system.cpu0.iq.fp_inst_queue_reads 1203467 # Number of floating instruction queue reads 789system.cpu0.iq.fp_inst_queue_writes 445947 # Number of floating instruction queue writes 790system.cpu0.iq.fp_inst_queue_wakeup_accesses 420205 # Number of floating instruction queue wakeup accesses 791system.cpu0.iq.int_alu_accesses 738689926 # Number of integer alu accesses 792system.cpu0.iq.fp_alu_accesses 775135 # Number of floating point alu accesses 793system.cpu0.iew.lsq.thread0.forwLoads 2992085 # Number of loads that had data forwarded from stores 794system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 795system.cpu0.iew.lsq.thread0.squashedLoads 13179956 # Number of loads squashed 796system.cpu0.iew.lsq.thread0.ignoredResponses 18072 # Number of memory responses ignored because the instruction is squashed 797system.cpu0.iew.lsq.thread0.memOrderViolation 162311 # Number of memory ordering violations 798system.cpu0.iew.lsq.thread0.squashedStores 5715015 # Number of stores squashed 799system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 800system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 801system.cpu0.iew.lsq.thread0.rescheduledLoads 3005258 # Number of loads that were rescheduled 802system.cpu0.iew.lsq.thread0.cacheBlocked 4976098 # Number of times an access to memory failed due to the cache being blocked 803system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 804system.cpu0.iew.iewSquashCycles 5329407 # Number of cycles IEW is squashing 805system.cpu0.iew.iewBlockCycles 8694006 # Number of cycles IEW is blocking 806system.cpu0.iew.iewUnblockCycles 1907824 # Number of cycles IEW is unblocking 807system.cpu0.iew.iewDispatchedInsts 605581185 # Number of instructions dispatched to IQ 808system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 809system.cpu0.iew.iewDispLoadInsts 107690406 # Number of dispatched load instructions 810system.cpu0.iew.iewDispStoreInsts 90791382 # Number of dispatched store instructions 811system.cpu0.iew.iewDispNonSpecInsts 4430701 # Number of dispatched non-speculative instructions 812system.cpu0.iew.iewIQFullEvents 69738 # Number of times the IQ has become full, causing a stall 813system.cpu0.iew.iewLSQFullEvents 1753830 # Number of times the LSQ has become full, causing a stall 814system.cpu0.iew.memOrderViolationEvents 162311 # Number of memory order violations 815system.cpu0.iew.predictedTakenIncorrect 2018069 # Number of branches that were predicted taken incorrectly 816system.cpu0.iew.predictedNotTakenIncorrect 3124602 # Number of branches that were predicted not taken incorrectly 817system.cpu0.iew.branchMispredicts 5142671 # Number of branch mispredicts detected at execute 818system.cpu0.iew.iewExecutedInsts 586012257 # Number of executed instructions 819system.cpu0.iew.iewExecLoadInsts 107766715 # Number of load instructions executed 820system.cpu0.iew.iewExecSquashedInsts 7557397 # Number of squashed instructions skipped in execute 821system.cpu0.iew.exec_swp 0 # number of swp insts executed 822system.cpu0.iew.exec_nop 135817 # number of nop insts executed 823system.cpu0.iew.exec_refs 195183772 # number of memory reference insts executed 824system.cpu0.iew.exec_branches 107644173 # Number of branches executed 825system.cpu0.iew.exec_stores 87417057 # Number of stores executed 826system.cpu0.iew.exec_rate 0.872488 # Inst execution rate 827system.cpu0.iew.wb_sent 577164047 # cumulative count of insts sent to commit 828system.cpu0.iew.wb_count 576362718 # cumulative count of insts written-back 829system.cpu0.iew.wb_producers 283557258 # num instructions producing a value 830system.cpu0.iew.wb_consumers 461921851 # num instructions consuming a value 831system.cpu0.iew.wb_rate 0.858122 # insts written-back per cycle 832system.cpu0.iew.wb_fanout 0.613864 # average fanout of values written-back 833system.cpu0.commit.commitSquashedInsts 48922079 # The number of squashed insts skipped by commit 834system.cpu0.commit.commitNonSpecStalls 6745775 # The number of times commit has been forced to stall to communicate backwards 835system.cpu0.commit.branchMispredicts 4784510 # The number of times a branch was mispredicted 836system.cpu0.commit.committed_per_cycle::samples 638061728 # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::mean 0.861165 # Number of insts commited each cycle 838system.cpu0.commit.committed_per_cycle::stdev 1.699392 # Number of insts commited each cycle 839system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 840system.cpu0.commit.committed_per_cycle::0 421096864 66.00% 66.00% # Number of insts commited each cycle 841system.cpu0.commit.committed_per_cycle::1 93116977 14.59% 80.59% # Number of insts commited each cycle 842system.cpu0.commit.committed_per_cycle::2 56739989 8.89% 89.48% # Number of insts commited each cycle 843system.cpu0.commit.committed_per_cycle::3 18882229 2.96% 92.44% # Number of insts commited each cycle 844system.cpu0.commit.committed_per_cycle::4 13609968 2.13% 94.57% # Number of insts commited each cycle 845system.cpu0.commit.committed_per_cycle::5 9457933 1.48% 96.06% # Number of insts commited each cycle 846system.cpu0.commit.committed_per_cycle::6 6466471 1.01% 97.07% # Number of insts commited each cycle 847system.cpu0.commit.committed_per_cycle::7 3826133 0.60% 97.67% # Number of insts commited each cycle 848system.cpu0.commit.committed_per_cycle::8 14865164 2.33% 100.00% # Number of insts commited each cycle 849system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 850system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 851system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 852system.cpu0.commit.committed_per_cycle::total 638061728 # Number of insts commited each cycle 853system.cpu0.commit.committedInsts 461890383 # Number of instructions committed 854system.cpu0.commit.committedOps 549476248 # Number of ops (including micro ops) committed 855system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 856system.cpu0.commit.refs 179586814 # Number of memory references committed 857system.cpu0.commit.loads 94510447 # Number of loads committed 858system.cpu0.commit.membars 4189650 # Number of memory barriers committed 859system.cpu0.commit.branches 102007560 # Number of branches committed 860system.cpu0.commit.fp_insts 412941 # Number of committed floating point instructions. 861system.cpu0.commit.int_insts 511246578 # Number of committed integer instructions. 862system.cpu0.commit.function_calls 15004572 # Number of function calls committed. 863system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 864system.cpu0.commit.op_class_0::IntAlu 368489017 67.06% 67.06% # Class of committed instruction 865system.cpu0.commit.op_class_0::IntMult 1298564 0.24% 67.30% # Class of committed instruction 866system.cpu0.commit.op_class_0::IntDiv 64848 0.01% 67.31% # Class of committed instruction 867system.cpu0.commit.op_class_0::FloatAdd 8 0.00% 67.31% # Class of committed instruction 868system.cpu0.commit.op_class_0::FloatCmp 13 0.00% 67.31% # Class of committed instruction 869system.cpu0.commit.op_class_0::FloatCvt 21 0.00% 67.31% # Class of committed instruction 870system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.31% # Class of committed instruction 871system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 67.31% # Class of committed instruction 872system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.31% # Class of committed instruction 873system.cpu0.commit.op_class_0::FloatMisc 36963 0.01% 67.32% # Class of committed instruction 874system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.32% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.32% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.32% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.32% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.32% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.32% # Class of committed instruction 880system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.32% # Class of committed instruction 881system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.32% # Class of committed instruction 882system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.32% # Class of committed instruction 883system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.32% # Class of committed instruction 884system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.32% # Class of committed instruction 885system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.32% # Class of committed instruction 886system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.32% # Class of committed instruction 887system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.32% # Class of committed instruction 888system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.32% # Class of committed instruction 889system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.32% # Class of committed instruction 890system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.32% # Class of committed instruction 891system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 67.32% # Class of committed instruction 892system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.32% # Class of committed instruction 893system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.32% # Class of committed instruction 894system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.32% # Class of committed instruction 895system.cpu0.commit.op_class_0::MemRead 94459041 17.19% 84.51% # Class of committed instruction 896system.cpu0.commit.op_class_0::MemWrite 84751837 15.42% 99.93% # Class of committed instruction 897system.cpu0.commit.op_class_0::FloatMemRead 51406 0.01% 99.94% # Class of committed instruction 898system.cpu0.commit.op_class_0::FloatMemWrite 324530 0.06% 100.00% # Class of committed instruction 899system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 900system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 901system.cpu0.commit.op_class_0::total 549476248 # Class of committed instruction 902system.cpu0.commit.bw_lim_events 14865164 # number cycles where commit BW limit reached 903system.cpu0.rob.rob_reads 1217272285 # The number of ROB reads 904system.cpu0.rob.rob_writes 1206069871 # The number of ROB writes 905system.cpu0.timesIdled 983506 # Number of times that the entire CPU went into an idle state and unscheduled itself 906system.cpu0.idleCycles 24284471 # Total number of cycles that the CPU has spent unscheduled due to idling 907system.cpu0.quiesceCycles 94012190405 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 908system.cpu0.committedInsts 461890383 # Number of Instructions Simulated 909system.cpu0.committedOps 549476248 # Number of Ops (including micro ops) Simulated 910system.cpu0.cpi 1.454146 # CPI: Cycles Per Instruction 911system.cpu0.cpi_total 1.454146 # CPI: Total CPI of All Threads 912system.cpu0.ipc 0.687689 # IPC: Instructions Per Cycle 913system.cpu0.ipc_total 0.687689 # IPC: Total IPC of All Threads 914system.cpu0.int_regfile_reads 689648120 # number of integer regfile reads 915system.cpu0.int_regfile_writes 419367317 # number of integer regfile writes 916system.cpu0.fp_regfile_reads 692130 # number of floating regfile reads 917system.cpu0.fp_regfile_writes 320584 # number of floating regfile writes 918system.cpu0.cc_regfile_reads 105285978 # number of cc regfile reads 919system.cpu0.cc_regfile_writes 105978286 # number of cc regfile writes 920system.cpu0.misc_regfile_reads 1168751660 # number of misc regfile reads 921system.cpu0.misc_regfile_writes 6863582 # number of misc regfile writes 922system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 923system.cpu0.dcache.tags.replacements 6620968 # number of replacements 924system.cpu0.dcache.tags.tagsinuse 481.361219 # Cycle average of tags in use 925system.cpu0.dcache.tags.total_refs 165967454 # Total number of references to valid blocks. 926system.cpu0.dcache.tags.sampled_refs 6621480 # Sample count of references to valid blocks. 927system.cpu0.dcache.tags.avg_refs 25.065009 # Average number of references to valid blocks. 928system.cpu0.dcache.tags.warmup_cycle 204144000 # Cycle when the warmup percentage was hit. 929system.cpu0.dcache.tags.occ_blocks::cpu0.data 481.361219 # Average occupied blocks per requestor 930system.cpu0.dcache.tags.occ_percent::cpu0.data 0.940159 # Average percentage of cache occupancy 931system.cpu0.dcache.tags.occ_percent::total 0.940159 # Average percentage of cache occupancy 932system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 933system.cpu0.dcache.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 934system.cpu0.dcache.tags.age_task_id_blocks_1024::1 433 # Occupied blocks per task id 935system.cpu0.dcache.tags.age_task_id_blocks_1024::2 62 # Occupied blocks per task id 936system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 937system.cpu0.dcache.tags.tag_accesses 372530825 # Number of tag accesses 938system.cpu0.dcache.tags.data_accesses 372530825 # Number of data accesses 939system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 940system.cpu0.dcache.ReadReq_hits::cpu0.data 87044023 # number of ReadReq hits 941system.cpu0.dcache.ReadReq_hits::total 87044023 # number of ReadReq hits 942system.cpu0.dcache.WriteReq_hits::cpu0.data 73673205 # number of WriteReq hits 943system.cpu0.dcache.WriteReq_hits::total 73673205 # number of WriteReq hits 944system.cpu0.dcache.SoftPFReq_hits::cpu0.data 219185 # number of SoftPFReq hits 945system.cpu0.dcache.SoftPFReq_hits::total 219185 # number of SoftPFReq hits 946system.cpu0.dcache.WriteLineReq_hits::cpu0.data 153997 # number of WriteLineReq hits 947system.cpu0.dcache.WriteLineReq_hits::total 153997 # number of WriteLineReq hits 948system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 2008223 # number of LoadLockedReq hits 949system.cpu0.dcache.LoadLockedReq_hits::total 2008223 # number of LoadLockedReq hits 950system.cpu0.dcache.StoreCondReq_hits::cpu0.data 2072988 # number of StoreCondReq hits 951system.cpu0.dcache.StoreCondReq_hits::total 2072988 # number of StoreCondReq hits 952system.cpu0.dcache.demand_hits::cpu0.data 160871225 # number of demand (read+write) hits 953system.cpu0.dcache.demand_hits::total 160871225 # number of demand (read+write) hits 954system.cpu0.dcache.overall_hits::cpu0.data 161090410 # number of overall hits 955system.cpu0.dcache.overall_hits::total 161090410 # number of overall hits 956system.cpu0.dcache.ReadReq_misses::cpu0.data 7470146 # number of ReadReq misses 957system.cpu0.dcache.ReadReq_misses::total 7470146 # number of ReadReq misses 958system.cpu0.dcache.WriteReq_misses::cpu0.data 8166848 # number of WriteReq misses 959system.cpu0.dcache.WriteReq_misses::total 8166848 # number of WriteReq misses 960system.cpu0.dcache.SoftPFReq_misses::cpu0.data 789396 # number of SoftPFReq misses 961system.cpu0.dcache.SoftPFReq_misses::total 789396 # number of SoftPFReq misses 962system.cpu0.dcache.WriteLineReq_misses::cpu0.data 800299 # number of WriteLineReq misses 963system.cpu0.dcache.WriteLineReq_misses::total 800299 # number of WriteLineReq misses 964system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 307874 # number of LoadLockedReq misses 965system.cpu0.dcache.LoadLockedReq_misses::total 307874 # number of LoadLockedReq misses 966system.cpu0.dcache.StoreCondReq_misses::cpu0.data 202740 # number of StoreCondReq misses 967system.cpu0.dcache.StoreCondReq_misses::total 202740 # number of StoreCondReq misses 968system.cpu0.dcache.demand_misses::cpu0.data 16437293 # number of demand (read+write) misses 969system.cpu0.dcache.demand_misses::total 16437293 # number of demand (read+write) misses 970system.cpu0.dcache.overall_misses::cpu0.data 17226689 # number of overall misses 971system.cpu0.dcache.overall_misses::total 17226689 # number of overall misses 972system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 120830384000 # number of ReadReq miss cycles 973system.cpu0.dcache.ReadReq_miss_latency::total 120830384000 # number of ReadReq miss cycles 974system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 166078687815 # number of WriteReq miss cycles 975system.cpu0.dcache.WriteReq_miss_latency::total 166078687815 # number of WriteReq miss cycles 976system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 29848601951 # number of WriteLineReq miss cycles 977system.cpu0.dcache.WriteLineReq_miss_latency::total 29848601951 # number of WriteLineReq miss cycles 978system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4689476000 # number of LoadLockedReq miss cycles 979system.cpu0.dcache.LoadLockedReq_miss_latency::total 4689476000 # number of LoadLockedReq miss cycles 980system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4883927500 # number of StoreCondReq miss cycles 981system.cpu0.dcache.StoreCondReq_miss_latency::total 4883927500 # number of StoreCondReq miss cycles 982system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2141000 # number of StoreCondFailReq miss cycles 983system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2141000 # number of StoreCondFailReq miss cycles 984system.cpu0.dcache.demand_miss_latency::cpu0.data 316757673766 # number of demand (read+write) miss cycles 985system.cpu0.dcache.demand_miss_latency::total 316757673766 # number of demand (read+write) miss cycles 986system.cpu0.dcache.overall_miss_latency::cpu0.data 316757673766 # number of overall miss cycles 987system.cpu0.dcache.overall_miss_latency::total 316757673766 # number of overall miss cycles 988system.cpu0.dcache.ReadReq_accesses::cpu0.data 94514169 # number of ReadReq accesses(hits+misses) 989system.cpu0.dcache.ReadReq_accesses::total 94514169 # number of ReadReq accesses(hits+misses) 990system.cpu0.dcache.WriteReq_accesses::cpu0.data 81840053 # number of WriteReq accesses(hits+misses) 991system.cpu0.dcache.WriteReq_accesses::total 81840053 # number of WriteReq accesses(hits+misses) 992system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 1008581 # number of SoftPFReq accesses(hits+misses) 993system.cpu0.dcache.SoftPFReq_accesses::total 1008581 # number of SoftPFReq accesses(hits+misses) 994system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 954296 # number of WriteLineReq accesses(hits+misses) 995system.cpu0.dcache.WriteLineReq_accesses::total 954296 # number of WriteLineReq accesses(hits+misses) 996system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2316097 # number of LoadLockedReq accesses(hits+misses) 997system.cpu0.dcache.LoadLockedReq_accesses::total 2316097 # number of LoadLockedReq accesses(hits+misses) 998system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2275728 # number of StoreCondReq accesses(hits+misses) 999system.cpu0.dcache.StoreCondReq_accesses::total 2275728 # number of StoreCondReq accesses(hits+misses) 1000system.cpu0.dcache.demand_accesses::cpu0.data 177308518 # number of demand (read+write) accesses 1001system.cpu0.dcache.demand_accesses::total 177308518 # number of demand (read+write) accesses 1002system.cpu0.dcache.overall_accesses::cpu0.data 178317099 # number of overall (read+write) accesses 1003system.cpu0.dcache.overall_accesses::total 178317099 # number of overall (read+write) accesses 1004system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079037 # miss rate for ReadReq accesses 1005system.cpu0.dcache.ReadReq_miss_rate::total 0.079037 # miss rate for ReadReq accesses 1006system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099790 # miss rate for WriteReq accesses 1007system.cpu0.dcache.WriteReq_miss_rate::total 0.099790 # miss rate for WriteReq accesses 1008system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.782680 # miss rate for SoftPFReq accesses 1009system.cpu0.dcache.SoftPFReq_miss_rate::total 0.782680 # miss rate for SoftPFReq accesses 1010system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.838628 # miss rate for WriteLineReq accesses 1011system.cpu0.dcache.WriteLineReq_miss_rate::total 0.838628 # miss rate for WriteLineReq accesses 1012system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132928 # miss rate for LoadLockedReq accesses 1013system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132928 # miss rate for LoadLockedReq accesses 1014system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.089088 # miss rate for StoreCondReq accesses 1015system.cpu0.dcache.StoreCondReq_miss_rate::total 0.089088 # miss rate for StoreCondReq accesses 1016system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092704 # miss rate for demand accesses 1017system.cpu0.dcache.demand_miss_rate::total 0.092704 # miss rate for demand accesses 1018system.cpu0.dcache.overall_miss_rate::cpu0.data 0.096607 # miss rate for overall accesses 1019system.cpu0.dcache.overall_miss_rate::total 0.096607 # miss rate for overall accesses 1020system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16175.103405 # average ReadReq miss latency 1021system.cpu0.dcache.ReadReq_avg_miss_latency::total 16175.103405 # average ReadReq miss latency 1022system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20335.714319 # average WriteReq miss latency 1023system.cpu0.dcache.WriteReq_avg_miss_latency::total 20335.714319 # average WriteReq miss latency 1024system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 37296.812755 # average WriteLineReq miss latency 1025system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 37296.812755 # average WriteLineReq miss latency 1026system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15231.802621 # average LoadLockedReq miss latency 1027system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15231.802621 # average LoadLockedReq miss latency 1028system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24089.609845 # average StoreCondReq miss latency 1029system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24089.609845 # average StoreCondReq miss latency 1030system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1031system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1032system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19270.671501 # average overall miss latency 1033system.cpu0.dcache.demand_avg_miss_latency::total 19270.671501 # average overall miss latency 1034system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18387.612023 # average overall miss latency 1035system.cpu0.dcache.overall_avg_miss_latency::total 18387.612023 # average overall miss latency 1036system.cpu0.dcache.blocked_cycles::no_mshrs 9058407 # number of cycles access was blocked 1037system.cpu0.dcache.blocked_cycles::no_targets 25757393 # number of cycles access was blocked 1038system.cpu0.dcache.blocked::no_mshrs 741437 # number of cycles access was blocked 1039system.cpu0.dcache.blocked::no_targets 811492 # number of cycles access was blocked 1040system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.217366 # average number of cycles each access was blocked 1041system.cpu0.dcache.avg_blocked_cycles::no_targets 31.740785 # average number of cycles each access was blocked 1042system.cpu0.dcache.writebacks::writebacks 6621095 # number of writebacks 1043system.cpu0.dcache.writebacks::total 6621095 # number of writebacks 1044system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3832878 # number of ReadReq MSHR hits 1045system.cpu0.dcache.ReadReq_mshr_hits::total 3832878 # number of ReadReq MSHR hits 1046system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6557291 # number of WriteReq MSHR hits 1047system.cpu0.dcache.WriteReq_mshr_hits::total 6557291 # number of WriteReq MSHR hits 1048system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4455 # number of WriteLineReq MSHR hits 1049system.cpu0.dcache.WriteLineReq_mshr_hits::total 4455 # number of WriteLineReq MSHR hits 1050system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 156975 # number of LoadLockedReq MSHR hits 1051system.cpu0.dcache.LoadLockedReq_mshr_hits::total 156975 # number of LoadLockedReq MSHR hits 1052system.cpu0.dcache.demand_mshr_hits::cpu0.data 10394624 # number of demand (read+write) MSHR hits 1053system.cpu0.dcache.demand_mshr_hits::total 10394624 # number of demand (read+write) MSHR hits 1054system.cpu0.dcache.overall_mshr_hits::cpu0.data 10394624 # number of overall MSHR hits 1055system.cpu0.dcache.overall_mshr_hits::total 10394624 # number of overall MSHR hits 1056system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3637268 # number of ReadReq MSHR misses 1057system.cpu0.dcache.ReadReq_mshr_misses::total 3637268 # number of ReadReq MSHR misses 1058system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1609557 # number of WriteReq MSHR misses 1059system.cpu0.dcache.WriteReq_mshr_misses::total 1609557 # number of WriteReq MSHR misses 1060system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 782554 # number of SoftPFReq MSHR misses 1061system.cpu0.dcache.SoftPFReq_mshr_misses::total 782554 # number of SoftPFReq MSHR misses 1062system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 795844 # number of WriteLineReq MSHR misses 1063system.cpu0.dcache.WriteLineReq_mshr_misses::total 795844 # number of WriteLineReq MSHR misses 1064system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 150899 # number of LoadLockedReq MSHR misses 1065system.cpu0.dcache.LoadLockedReq_mshr_misses::total 150899 # number of LoadLockedReq MSHR misses 1066system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 202732 # number of StoreCondReq MSHR misses 1067system.cpu0.dcache.StoreCondReq_mshr_misses::total 202732 # number of StoreCondReq MSHR misses 1068system.cpu0.dcache.demand_mshr_misses::cpu0.data 6042669 # number of demand (read+write) MSHR misses 1069system.cpu0.dcache.demand_mshr_misses::total 6042669 # number of demand (read+write) MSHR misses 1070system.cpu0.dcache.overall_mshr_misses::cpu0.data 6825223 # number of overall MSHR misses 1071system.cpu0.dcache.overall_mshr_misses::total 6825223 # number of overall MSHR misses 1072system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable 1073system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15843 # number of ReadReq MSHR uncacheable 1074system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable 1075system.cpu0.dcache.WriteReq_mshr_uncacheable::total 17283 # number of WriteReq MSHR uncacheable 1076system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses 1077system.cpu0.dcache.overall_mshr_uncacheable_misses::total 33126 # number of overall MSHR uncacheable misses 1078system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 55872486000 # number of ReadReq MSHR miss cycles 1079system.cpu0.dcache.ReadReq_mshr_miss_latency::total 55872486000 # number of ReadReq MSHR miss cycles 1080system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 35889720367 # number of WriteReq MSHR miss cycles 1081system.cpu0.dcache.WriteReq_mshr_miss_latency::total 35889720367 # number of WriteReq MSHR miss cycles 1082system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18736140000 # number of SoftPFReq MSHR miss cycles 1083system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18736140000 # number of SoftPFReq MSHR miss cycles 1084system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 28877247951 # number of WriteLineReq MSHR miss cycles 1085system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 28877247951 # number of WriteLineReq MSHR miss cycles 1086system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 2069296000 # number of LoadLockedReq MSHR miss cycles 1087system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 2069296000 # number of LoadLockedReq MSHR miss cycles 1088system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4681247500 # number of StoreCondReq MSHR miss cycles 1089system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4681247500 # number of StoreCondReq MSHR miss cycles 1090system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2089000 # number of StoreCondFailReq MSHR miss cycles 1091system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2089000 # number of StoreCondFailReq MSHR miss cycles 1092system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 120639454318 # number of demand (read+write) MSHR miss cycles 1093system.cpu0.dcache.demand_mshr_miss_latency::total 120639454318 # number of demand (read+write) MSHR miss cycles 1094system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 139375594318 # number of overall MSHR miss cycles 1095system.cpu0.dcache.overall_mshr_miss_latency::total 139375594318 # number of overall MSHR miss cycles 1096system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2897214000 # number of ReadReq MSHR uncacheable cycles 1097system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2897214000 # number of ReadReq MSHR uncacheable cycles 1098system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2897214000 # number of overall MSHR uncacheable cycles 1099system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2897214000 # number of overall MSHR uncacheable cycles 1100system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038484 # mshr miss rate for ReadReq accesses 1101system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038484 # mshr miss rate for ReadReq accesses 1102system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019667 # mshr miss rate for WriteReq accesses 1103system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019667 # mshr miss rate for WriteReq accesses 1104system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.775896 # mshr miss rate for SoftPFReq accesses 1105system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.775896 # mshr miss rate for SoftPFReq accesses 1106system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.833959 # mshr miss rate for WriteLineReq accesses 1107system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.833959 # mshr miss rate for WriteLineReq accesses 1108system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.065152 # mshr miss rate for LoadLockedReq accesses 1109system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.065152 # mshr miss rate for LoadLockedReq accesses 1110system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.089084 # mshr miss rate for StoreCondReq accesses 1111system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.089084 # mshr miss rate for StoreCondReq accesses 1112system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034080 # mshr miss rate for demand accesses 1113system.cpu0.dcache.demand_mshr_miss_rate::total 0.034080 # mshr miss rate for demand accesses 1114system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038276 # mshr miss rate for overall accesses 1115system.cpu0.dcache.overall_mshr_miss_rate::total 0.038276 # mshr miss rate for overall accesses 1116system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15361.113341 # average ReadReq mshr miss latency 1117system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15361.113341 # average ReadReq mshr miss latency 1118system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22297.887162 # average WriteReq mshr miss latency 1119system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22297.887162 # average WriteReq mshr miss latency 1120system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23942.296634 # average SoftPFReq mshr miss latency 1121system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23942.296634 # average SoftPFReq mshr miss latency 1122system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 36285.060830 # average WriteLineReq mshr miss latency 1123system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 36285.060830 # average WriteLineReq mshr miss latency 1124system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13713.119371 # average LoadLockedReq mshr miss latency 1125system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13713.119371 # average LoadLockedReq mshr miss latency 1126system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23090.816941 # average StoreCondReq mshr miss latency 1127system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23090.816941 # average StoreCondReq mshr miss latency 1128system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1129system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1130system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19964.597485 # average overall mshr miss latency 1131system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19964.597485 # average overall mshr miss latency 1132system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20420.665276 # average overall mshr miss latency 1133system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20420.665276 # average overall mshr miss latency 1134system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182870.289718 # average ReadReq mshr uncacheable latency 1135system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182870.289718 # average ReadReq mshr uncacheable latency 1136system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87460.423836 # average overall mshr uncacheable latency 1137system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87460.423836 # average overall mshr uncacheable latency 1138system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 1139system.cpu0.icache.tags.replacements 6024041 # number of replacements 1140system.cpu0.icache.tags.tagsinuse 511.980173 # Cycle average of tags in use 1141system.cpu0.icache.tags.total_refs 202652654 # Total number of references to valid blocks. 1142system.cpu0.icache.tags.sampled_refs 6024553 # Sample count of references to valid blocks. 1143system.cpu0.icache.tags.avg_refs 33.637791 # Average number of references to valid blocks. 1144system.cpu0.icache.tags.warmup_cycle 11640760000 # Cycle when the warmup percentage was hit. 1145system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.980173 # Average occupied blocks per requestor 1146system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999961 # Average percentage of cache occupancy 1147system.cpu0.icache.tags.occ_percent::total 0.999961 # Average percentage of cache occupancy 1148system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1149system.cpu0.icache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 1150system.cpu0.icache.tags.age_task_id_blocks_1024::1 418 # Occupied blocks per task id 1151system.cpu0.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 1152system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1153system.cpu0.icache.tags.tag_accesses 424090067 # Number of tag accesses 1154system.cpu0.icache.tags.data_accesses 424090067 # Number of data accesses 1155system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 1156system.cpu0.icache.ReadReq_hits::cpu0.inst 202652654 # number of ReadReq hits 1157system.cpu0.icache.ReadReq_hits::total 202652654 # number of ReadReq hits 1158system.cpu0.icache.demand_hits::cpu0.inst 202652654 # number of demand (read+write) hits 1159system.cpu0.icache.demand_hits::total 202652654 # number of demand (read+write) hits 1160system.cpu0.icache.overall_hits::cpu0.inst 202652654 # number of overall hits 1161system.cpu0.icache.overall_hits::total 202652654 # number of overall hits 1162system.cpu0.icache.ReadReq_misses::cpu0.inst 6379961 # number of ReadReq misses 1163system.cpu0.icache.ReadReq_misses::total 6379961 # number of ReadReq misses 1164system.cpu0.icache.demand_misses::cpu0.inst 6379961 # number of demand (read+write) misses 1165system.cpu0.icache.demand_misses::total 6379961 # number of demand (read+write) misses 1166system.cpu0.icache.overall_misses::cpu0.inst 6379961 # number of overall misses 1167system.cpu0.icache.overall_misses::total 6379961 # number of overall misses 1168system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71606822648 # number of ReadReq miss cycles 1169system.cpu0.icache.ReadReq_miss_latency::total 71606822648 # number of ReadReq miss cycles 1170system.cpu0.icache.demand_miss_latency::cpu0.inst 71606822648 # number of demand (read+write) miss cycles 1171system.cpu0.icache.demand_miss_latency::total 71606822648 # number of demand (read+write) miss cycles 1172system.cpu0.icache.overall_miss_latency::cpu0.inst 71606822648 # number of overall miss cycles 1173system.cpu0.icache.overall_miss_latency::total 71606822648 # number of overall miss cycles 1174system.cpu0.icache.ReadReq_accesses::cpu0.inst 209032615 # number of ReadReq accesses(hits+misses) 1175system.cpu0.icache.ReadReq_accesses::total 209032615 # number of ReadReq accesses(hits+misses) 1176system.cpu0.icache.demand_accesses::cpu0.inst 209032615 # number of demand (read+write) accesses 1177system.cpu0.icache.demand_accesses::total 209032615 # number of demand (read+write) accesses 1178system.cpu0.icache.overall_accesses::cpu0.inst 209032615 # number of overall (read+write) accesses 1179system.cpu0.icache.overall_accesses::total 209032615 # number of overall (read+write) accesses 1180system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.030521 # miss rate for ReadReq accesses 1181system.cpu0.icache.ReadReq_miss_rate::total 0.030521 # miss rate for ReadReq accesses 1182system.cpu0.icache.demand_miss_rate::cpu0.inst 0.030521 # miss rate for demand accesses 1183system.cpu0.icache.demand_miss_rate::total 0.030521 # miss rate for demand accesses 1184system.cpu0.icache.overall_miss_rate::cpu0.inst 0.030521 # miss rate for overall accesses 1185system.cpu0.icache.overall_miss_rate::total 0.030521 # miss rate for overall accesses 1186system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11223.708522 # average ReadReq miss latency 1187system.cpu0.icache.ReadReq_avg_miss_latency::total 11223.708522 # average ReadReq miss latency 1188system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency 1189system.cpu0.icache.demand_avg_miss_latency::total 11223.708522 # average overall miss latency 1190system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11223.708522 # average overall miss latency 1191system.cpu0.icache.overall_avg_miss_latency::total 11223.708522 # average overall miss latency 1192system.cpu0.icache.blocked_cycles::no_mshrs 10553176 # number of cycles access was blocked 1193system.cpu0.icache.blocked_cycles::no_targets 2682 # number of cycles access was blocked 1194system.cpu0.icache.blocked::no_mshrs 731110 # number of cycles access was blocked 1195system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked 1196system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.434457 # average number of cycles each access was blocked 1197system.cpu0.icache.avg_blocked_cycles::no_targets 243.818182 # average number of cycles each access was blocked 1198system.cpu0.icache.writebacks::writebacks 6024041 # number of writebacks 1199system.cpu0.icache.writebacks::total 6024041 # number of writebacks 1200system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355124 # number of ReadReq MSHR hits 1201system.cpu0.icache.ReadReq_mshr_hits::total 355124 # number of ReadReq MSHR hits 1202system.cpu0.icache.demand_mshr_hits::cpu0.inst 355124 # number of demand (read+write) MSHR hits 1203system.cpu0.icache.demand_mshr_hits::total 355124 # number of demand (read+write) MSHR hits 1204system.cpu0.icache.overall_mshr_hits::cpu0.inst 355124 # number of overall MSHR hits 1205system.cpu0.icache.overall_mshr_hits::total 355124 # number of overall MSHR hits 1206system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6024837 # number of ReadReq MSHR misses 1207system.cpu0.icache.ReadReq_mshr_misses::total 6024837 # number of ReadReq MSHR misses 1208system.cpu0.icache.demand_mshr_misses::cpu0.inst 6024837 # number of demand (read+write) MSHR misses 1209system.cpu0.icache.demand_mshr_misses::total 6024837 # number of demand (read+write) MSHR misses 1210system.cpu0.icache.overall_mshr_misses::cpu0.inst 6024837 # number of overall MSHR misses 1211system.cpu0.icache.overall_mshr_misses::total 6024837 # number of overall MSHR misses 1212system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable 1213system.cpu0.icache.ReadReq_mshr_uncacheable::total 2093 # number of ReadReq MSHR uncacheable 1214system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses 1215system.cpu0.icache.overall_mshr_uncacheable_misses::total 2093 # number of overall MSHR uncacheable misses 1216system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64522792922 # number of ReadReq MSHR miss cycles 1217system.cpu0.icache.ReadReq_mshr_miss_latency::total 64522792922 # number of ReadReq MSHR miss cycles 1218system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64522792922 # number of demand (read+write) MSHR miss cycles 1219system.cpu0.icache.demand_mshr_miss_latency::total 64522792922 # number of demand (read+write) MSHR miss cycles 1220system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64522792922 # number of overall MSHR miss cycles 1221system.cpu0.icache.overall_mshr_miss_latency::total 64522792922 # number of overall MSHR miss cycles 1222system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 201228498 # number of ReadReq MSHR uncacheable cycles 1223system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 201228498 # number of ReadReq MSHR uncacheable cycles 1224system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 201228498 # number of overall MSHR uncacheable cycles 1225system.cpu0.icache.overall_mshr_uncacheable_latency::total 201228498 # number of overall MSHR uncacheable cycles 1226system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for ReadReq accesses 1227system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028822 # mshr miss rate for ReadReq accesses 1228system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for demand accesses 1229system.cpu0.icache.demand_mshr_miss_rate::total 0.028822 # mshr miss rate for demand accesses 1230system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028822 # mshr miss rate for overall accesses 1231system.cpu0.icache.overall_mshr_miss_rate::total 0.028822 # mshr miss rate for overall accesses 1232system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average ReadReq mshr miss latency 1233system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10709.466982 # average ReadReq mshr miss latency 1234system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency 1235system.cpu0.icache.demand_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency 1236system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10709.466982 # average overall mshr miss latency 1237system.cpu0.icache.overall_avg_mshr_miss_latency::total 10709.466982 # average overall mshr miss latency 1238system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 96143.572862 # average ReadReq mshr uncacheable latency 1239system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 96143.572862 # average ReadReq mshr uncacheable latency 1240system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 96143.572862 # average overall mshr uncacheable latency 1241system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 96143.572862 # average overall mshr uncacheable latency 1242system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 1243system.cpu0.l2cache.prefetcher.num_hwpf_issued 9077732 # number of hwpf issued 1244system.cpu0.l2cache.prefetcher.pfIdentified 9085476 # number of prefetch candidates identified 1245system.cpu0.l2cache.prefetcher.pfBufferHit 6999 # number of redundant prefetches already in prefetch queue 1246system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1247system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1248system.cpu0.l2cache.prefetcher.pfSpanPage 1224644 # number of prefetches not generated due to page crossing 1249system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 1250system.cpu0.l2cache.tags.replacements 2885626 # number of replacements 1251system.cpu0.l2cache.tags.tagsinuse 15865.684381 # Cycle average of tags in use 1252system.cpu0.l2cache.tags.total_refs 11160732 # Total number of references to valid blocks. 1253system.cpu0.l2cache.tags.sampled_refs 2901096 # Sample count of references to valid blocks. 1254system.cpu0.l2cache.tags.avg_refs 3.847074 # Average number of references to valid blocks. 1255system.cpu0.l2cache.tags.warmup_cycle 512573000 # Cycle when the warmup percentage was hit. 1256system.cpu0.l2cache.tags.occ_blocks::writebacks 15504.354139 # Average occupied blocks per requestor 1257system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 30.001688 # Average occupied blocks per requestor 1258system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 17.597153 # Average occupied blocks per requestor 1259system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000007 # Average occupied blocks per requestor 1260system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 313.731394 # Average occupied blocks per requestor 1261system.cpu0.l2cache.tags.occ_percent::writebacks 0.946311 # Average percentage of cache occupancy 1262system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001831 # Average percentage of cache occupancy 1263system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001074 # Average percentage of cache occupancy 1264system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy 1265system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.019149 # Average percentage of cache occupancy 1266system.cpu0.l2cache.tags.occ_percent::total 0.968365 # Average percentage of cache occupancy 1267system.cpu0.l2cache.tags.occ_task_id_blocks::1022 318 # Occupied blocks per task id 1268system.cpu0.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id 1269system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15041 # Occupied blocks per task id 1270system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 1271system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 120 # Occupied blocks per task id 1272system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 81 # Occupied blocks per task id 1273system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 114 # Occupied blocks per task id 1274system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 37 # Occupied blocks per task id 1275system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 43 # Occupied blocks per task id 1276system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id 1277system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id 1278system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id 1279system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 2178 # Occupied blocks per task id 1280system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7928 # Occupied blocks per task id 1281system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 2613 # Occupied blocks per task id 1282system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2218 # Occupied blocks per task id 1283system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.019409 # Percentage of cache occupancy per task id 1284system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id 1285system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.918030 # Percentage of cache occupancy per task id 1286system.cpu0.l2cache.tags.tag_accesses 441303495 # Number of tag accesses 1287system.cpu0.l2cache.tags.data_accesses 441303495 # Number of data accesses 1288system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 1289system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 661323 # number of ReadReq hits 1290system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 192664 # number of ReadReq hits 1291system.cpu0.l2cache.ReadReq_hits::total 853987 # number of ReadReq hits 1292system.cpu0.l2cache.WritebackDirty_hits::writebacks 4337132 # number of WritebackDirty hits 1293system.cpu0.l2cache.WritebackDirty_hits::total 4337132 # number of WritebackDirty hits 1294system.cpu0.l2cache.WritebackClean_hits::writebacks 8306124 # number of WritebackClean hits 1295system.cpu0.l2cache.WritebackClean_hits::total 8306124 # number of WritebackClean hits 1296system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 35 # number of UpgradeReq hits 1297system.cpu0.l2cache.UpgradeReq_hits::total 35 # number of UpgradeReq hits 1298system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 3 # number of SCUpgradeReq hits 1299system.cpu0.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits 1300system.cpu0.l2cache.ReadExReq_hits::cpu0.data 1063752 # number of ReadExReq hits 1301system.cpu0.l2cache.ReadExReq_hits::total 1063752 # number of ReadExReq hits 1302system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5420251 # number of ReadCleanReq hits 1303system.cpu0.l2cache.ReadCleanReq_hits::total 5420251 # number of ReadCleanReq hits 1304system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3451457 # number of ReadSharedReq hits 1305system.cpu0.l2cache.ReadSharedReq_hits::total 3451457 # number of ReadSharedReq hits 1306system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 175529 # number of InvalidateReq hits 1307system.cpu0.l2cache.InvalidateReq_hits::total 175529 # number of InvalidateReq hits 1308system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 661323 # number of demand (read+write) hits 1309system.cpu0.l2cache.demand_hits::cpu0.itb.walker 192664 # number of demand (read+write) hits 1310system.cpu0.l2cache.demand_hits::cpu0.inst 5420251 # number of demand (read+write) hits 1311system.cpu0.l2cache.demand_hits::cpu0.data 4515209 # number of demand (read+write) hits 1312system.cpu0.l2cache.demand_hits::total 10789447 # number of demand (read+write) hits 1313system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 661323 # number of overall hits 1314system.cpu0.l2cache.overall_hits::cpu0.itb.walker 192664 # number of overall hits 1315system.cpu0.l2cache.overall_hits::cpu0.inst 5420251 # number of overall hits 1316system.cpu0.l2cache.overall_hits::cpu0.data 4515209 # number of overall hits 1317system.cpu0.l2cache.overall_hits::total 10789447 # number of overall hits 1318system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 24436 # number of ReadReq misses 1319system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 12223 # number of ReadReq misses 1320system.cpu0.l2cache.ReadReq_misses::total 36659 # number of ReadReq misses 1321system.cpu0.l2cache.WritebackClean_misses::writebacks 1 # number of WritebackClean misses 1322system.cpu0.l2cache.WritebackClean_misses::total 1 # number of WritebackClean misses 1323system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 266353 # number of UpgradeReq misses 1324system.cpu0.l2cache.UpgradeReq_misses::total 266353 # number of UpgradeReq misses 1325system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 202724 # number of SCUpgradeReq misses 1326system.cpu0.l2cache.SCUpgradeReq_misses::total 202724 # number of SCUpgradeReq misses 1327system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 1328system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1329system.cpu0.l2cache.ReadExReq_misses::cpu0.data 288175 # number of ReadExReq misses 1330system.cpu0.l2cache.ReadExReq_misses::total 288175 # number of ReadExReq misses 1331system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 604135 # number of ReadCleanReq misses 1332system.cpu0.l2cache.ReadCleanReq_misses::total 604135 # number of ReadCleanReq misses 1333system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1115532 # number of ReadSharedReq misses 1334system.cpu0.l2cache.ReadSharedReq_misses::total 1115532 # number of ReadSharedReq misses 1335system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 620315 # number of InvalidateReq misses 1336system.cpu0.l2cache.InvalidateReq_misses::total 620315 # number of InvalidateReq misses 1337system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 24436 # number of demand (read+write) misses 1338system.cpu0.l2cache.demand_misses::cpu0.itb.walker 12223 # number of demand (read+write) misses 1339system.cpu0.l2cache.demand_misses::cpu0.inst 604135 # number of demand (read+write) misses 1340system.cpu0.l2cache.demand_misses::cpu0.data 1403707 # number of demand (read+write) misses 1341system.cpu0.l2cache.demand_misses::total 2044501 # number of demand (read+write) misses 1342system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 24436 # number of overall misses 1343system.cpu0.l2cache.overall_misses::cpu0.itb.walker 12223 # number of overall misses 1344system.cpu0.l2cache.overall_misses::cpu0.inst 604135 # number of overall misses 1345system.cpu0.l2cache.overall_misses::cpu0.data 1403707 # number of overall misses 1346system.cpu0.l2cache.overall_misses::total 2044501 # number of overall misses 1347system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 912274000 # number of ReadReq miss cycles 1348system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 596923500 # number of ReadReq miss cycles 1349system.cpu0.l2cache.ReadReq_miss_latency::total 1509197500 # number of ReadReq miss cycles 1350system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 951661000 # number of UpgradeReq miss cycles 1351system.cpu0.l2cache.UpgradeReq_miss_latency::total 951661000 # number of UpgradeReq miss cycles 1352system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 365355500 # number of SCUpgradeReq miss cycles 1353system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 365355500 # number of SCUpgradeReq miss cycles 1354system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2010499 # number of SCUpgradeFailReq miss cycles 1355system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2010499 # number of SCUpgradeFailReq miss cycles 1356system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 19225466000 # number of ReadExReq miss cycles 1357system.cpu0.l2cache.ReadExReq_miss_latency::total 19225466000 # number of ReadExReq miss cycles 1358system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22664217000 # number of ReadCleanReq miss cycles 1359system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22664217000 # number of ReadCleanReq miss cycles 1360system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 46789999492 # number of ReadSharedReq miss cycles 1361system.cpu0.l2cache.ReadSharedReq_miss_latency::total 46789999492 # number of ReadSharedReq miss cycles 1362system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 209000 # number of InvalidateReq miss cycles 1363system.cpu0.l2cache.InvalidateReq_miss_latency::total 209000 # number of InvalidateReq miss cycles 1364system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 912274000 # number of demand (read+write) miss cycles 1365system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 596923500 # number of demand (read+write) miss cycles 1366system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22664217000 # number of demand (read+write) miss cycles 1367system.cpu0.l2cache.demand_miss_latency::cpu0.data 66015465492 # number of demand (read+write) miss cycles 1368system.cpu0.l2cache.demand_miss_latency::total 90188879992 # number of demand (read+write) miss cycles 1369system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 912274000 # number of overall miss cycles 1370system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 596923500 # number of overall miss cycles 1371system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22664217000 # number of overall miss cycles 1372system.cpu0.l2cache.overall_miss_latency::cpu0.data 66015465492 # number of overall miss cycles 1373system.cpu0.l2cache.overall_miss_latency::total 90188879992 # number of overall miss cycles 1374system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 685759 # number of ReadReq accesses(hits+misses) 1375system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 204887 # number of ReadReq accesses(hits+misses) 1376system.cpu0.l2cache.ReadReq_accesses::total 890646 # number of ReadReq accesses(hits+misses) 1377system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4337132 # number of WritebackDirty accesses(hits+misses) 1378system.cpu0.l2cache.WritebackDirty_accesses::total 4337132 # number of WritebackDirty accesses(hits+misses) 1379system.cpu0.l2cache.WritebackClean_accesses::writebacks 8306125 # number of WritebackClean accesses(hits+misses) 1380system.cpu0.l2cache.WritebackClean_accesses::total 8306125 # number of WritebackClean accesses(hits+misses) 1381system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 266388 # number of UpgradeReq accesses(hits+misses) 1382system.cpu0.l2cache.UpgradeReq_accesses::total 266388 # number of UpgradeReq accesses(hits+misses) 1383system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 202727 # number of SCUpgradeReq accesses(hits+misses) 1384system.cpu0.l2cache.SCUpgradeReq_accesses::total 202727 # number of SCUpgradeReq accesses(hits+misses) 1385system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 1386system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 1387system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1351927 # number of ReadExReq accesses(hits+misses) 1388system.cpu0.l2cache.ReadExReq_accesses::total 1351927 # number of ReadExReq accesses(hits+misses) 1389system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6024386 # number of ReadCleanReq accesses(hits+misses) 1390system.cpu0.l2cache.ReadCleanReq_accesses::total 6024386 # number of ReadCleanReq accesses(hits+misses) 1391system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4566989 # number of ReadSharedReq accesses(hits+misses) 1392system.cpu0.l2cache.ReadSharedReq_accesses::total 4566989 # number of ReadSharedReq accesses(hits+misses) 1393system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 795844 # number of InvalidateReq accesses(hits+misses) 1394system.cpu0.l2cache.InvalidateReq_accesses::total 795844 # number of InvalidateReq accesses(hits+misses) 1395system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 685759 # number of demand (read+write) accesses 1396system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 204887 # number of demand (read+write) accesses 1397system.cpu0.l2cache.demand_accesses::cpu0.inst 6024386 # number of demand (read+write) accesses 1398system.cpu0.l2cache.demand_accesses::cpu0.data 5918916 # number of demand (read+write) accesses 1399system.cpu0.l2cache.demand_accesses::total 12833948 # number of demand (read+write) accesses 1400system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 685759 # number of overall (read+write) accesses 1401system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 204887 # number of overall (read+write) accesses 1402system.cpu0.l2cache.overall_accesses::cpu0.inst 6024386 # number of overall (read+write) accesses 1403system.cpu0.l2cache.overall_accesses::cpu0.data 5918916 # number of overall (read+write) accesses 1404system.cpu0.l2cache.overall_accesses::total 12833948 # number of overall (read+write) accesses 1405system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for ReadReq accesses 1406system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059657 # miss rate for ReadReq accesses 1407system.cpu0.l2cache.ReadReq_miss_rate::total 0.041160 # miss rate for ReadReq accesses 1408system.cpu0.l2cache.WritebackClean_miss_rate::writebacks 0.000000 # miss rate for WritebackClean accesses 1409system.cpu0.l2cache.WritebackClean_miss_rate::total 0.000000 # miss rate for WritebackClean accesses 1410system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999869 # miss rate for UpgradeReq accesses 1411system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999869 # miss rate for UpgradeReq accesses 1412system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999985 # miss rate for SCUpgradeReq accesses 1413system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999985 # miss rate for SCUpgradeReq accesses 1414system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1415system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1416system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.213159 # miss rate for ReadExReq accesses 1417system.cpu0.l2cache.ReadExReq_miss_rate::total 0.213159 # miss rate for ReadExReq accesses 1418system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.100282 # miss rate for ReadCleanReq accesses 1419system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.100282 # miss rate for ReadCleanReq accesses 1420system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.244260 # miss rate for ReadSharedReq accesses 1421system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.244260 # miss rate for ReadSharedReq accesses 1422system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.779443 # miss rate for InvalidateReq accesses 1423system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.779443 # miss rate for InvalidateReq accesses 1424system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for demand accesses 1425system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059657 # miss rate for demand accesses 1426system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.100282 # miss rate for demand accesses 1427system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.237156 # miss rate for demand accesses 1428system.cpu0.l2cache.demand_miss_rate::total 0.159304 # miss rate for demand accesses 1429system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035634 # miss rate for overall accesses 1430system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059657 # miss rate for overall accesses 1431system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.100282 # miss rate for overall accesses 1432system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.237156 # miss rate for overall accesses 1433system.cpu0.l2cache.overall_miss_rate::total 0.159304 # miss rate for overall accesses 1434system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average ReadReq miss latency 1435system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48836.087704 # average ReadReq miss latency 1436system.cpu0.l2cache.ReadReq_avg_miss_latency::total 41168.539786 # average ReadReq miss latency 1437system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3572.931411 # average UpgradeReq miss latency 1438system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3572.931411 # average UpgradeReq miss latency 1439system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1802.231112 # average SCUpgradeReq miss latency 1440system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1802.231112 # average SCUpgradeReq miss latency 1441system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 402099.800000 # average SCUpgradeFailReq miss latency 1442system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 402099.800000 # average SCUpgradeFailReq miss latency 1443system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 66714.551922 # average ReadExReq miss latency 1444system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 66714.551922 # average ReadExReq miss latency 1445system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37515.153070 # average ReadCleanReq miss latency 1446system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37515.153070 # average ReadCleanReq miss latency 1447system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41944.112309 # average ReadSharedReq miss latency 1448system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41944.112309 # average ReadSharedReq miss latency 1449system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 0.336926 # average InvalidateReq miss latency 1450system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 0.336926 # average InvalidateReq miss latency 1451system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average overall miss latency 1452system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48836.087704 # average overall miss latency 1453system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37515.153070 # average overall miss latency 1454system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 47029.376851 # average overall miss latency 1455system.cpu0.l2cache.demand_avg_miss_latency::total 44112.905786 # average overall miss latency 1456system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 37333.196923 # average overall miss latency 1457system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48836.087704 # average overall miss latency 1458system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37515.153070 # average overall miss latency 1459system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 47029.376851 # average overall miss latency 1460system.cpu0.l2cache.overall_avg_miss_latency::total 44112.905786 # average overall miss latency 1461system.cpu0.l2cache.blocked_cycles::no_mshrs 1145 # number of cycles access was blocked 1462system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1463system.cpu0.l2cache.blocked::no_mshrs 20 # number of cycles access was blocked 1464system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1465system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 57.250000 # average number of cycles each access was blocked 1466system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1467system.cpu0.l2cache.unused_prefetches 50024 # number of HardPF blocks evicted w/o reference 1468system.cpu0.l2cache.writebacks::writebacks 1896260 # number of writebacks 1469system.cpu0.l2cache.writebacks::total 1896260 # number of writebacks 1470system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 178 # number of ReadReq MSHR hits 1471system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 367 # number of ReadReq MSHR hits 1472system.cpu0.l2cache.ReadReq_mshr_hits::total 545 # number of ReadReq MSHR hits 1473system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 23776 # number of ReadExReq MSHR hits 1474system.cpu0.l2cache.ReadExReq_mshr_hits::total 23776 # number of ReadExReq MSHR hits 1475system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 3 # number of ReadCleanReq MSHR hits 1476system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 1477system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 5616 # number of ReadSharedReq MSHR hits 1478system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 5616 # number of ReadSharedReq MSHR hits 1479system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 3 # number of InvalidateReq MSHR hits 1480system.cpu0.l2cache.InvalidateReq_mshr_hits::total 3 # number of InvalidateReq MSHR hits 1481system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 178 # number of demand (read+write) MSHR hits 1482system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 367 # number of demand (read+write) MSHR hits 1483system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3 # number of demand (read+write) MSHR hits 1484system.cpu0.l2cache.demand_mshr_hits::cpu0.data 29392 # number of demand (read+write) MSHR hits 1485system.cpu0.l2cache.demand_mshr_hits::total 29940 # number of demand (read+write) MSHR hits 1486system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 178 # number of overall MSHR hits 1487system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 367 # number of overall MSHR hits 1488system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3 # number of overall MSHR hits 1489system.cpu0.l2cache.overall_mshr_hits::cpu0.data 29392 # number of overall MSHR hits 1490system.cpu0.l2cache.overall_mshr_hits::total 29940 # number of overall MSHR hits 1491system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 24258 # number of ReadReq MSHR misses 1492system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 11856 # number of ReadReq MSHR misses 1493system.cpu0.l2cache.ReadReq_mshr_misses::total 36114 # number of ReadReq MSHR misses 1494system.cpu0.l2cache.WritebackClean_mshr_misses::writebacks 1 # number of WritebackClean MSHR misses 1495system.cpu0.l2cache.WritebackClean_mshr_misses::total 1 # number of WritebackClean MSHR misses 1496system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 950932 # number of HardPFReq MSHR misses 1497system.cpu0.l2cache.HardPFReq_mshr_misses::total 950932 # number of HardPFReq MSHR misses 1498system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 266353 # number of UpgradeReq MSHR misses 1499system.cpu0.l2cache.UpgradeReq_mshr_misses::total 266353 # number of UpgradeReq MSHR misses 1500system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 202724 # number of SCUpgradeReq MSHR misses 1501system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 202724 # number of SCUpgradeReq MSHR misses 1502system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 1503system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 1504system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 264399 # number of ReadExReq MSHR misses 1505system.cpu0.l2cache.ReadExReq_mshr_misses::total 264399 # number of ReadExReq MSHR misses 1506system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 604132 # number of ReadCleanReq MSHR misses 1507system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 604132 # number of ReadCleanReq MSHR misses 1508system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1109916 # number of ReadSharedReq MSHR misses 1509system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1109916 # number of ReadSharedReq MSHR misses 1510system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 620312 # number of InvalidateReq MSHR misses 1511system.cpu0.l2cache.InvalidateReq_mshr_misses::total 620312 # number of InvalidateReq MSHR misses 1512system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 24258 # number of demand (read+write) MSHR misses 1513system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 11856 # number of demand (read+write) MSHR misses 1514system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 604132 # number of demand (read+write) MSHR misses 1515system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1374315 # number of demand (read+write) MSHR misses 1516system.cpu0.l2cache.demand_mshr_misses::total 2014561 # number of demand (read+write) MSHR misses 1517system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 24258 # number of overall MSHR misses 1518system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 11856 # number of overall MSHR misses 1519system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 604132 # number of overall MSHR misses 1520system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1374315 # number of overall MSHR misses 1521system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 950932 # number of overall MSHR misses 1522system.cpu0.l2cache.overall_mshr_misses::total 2965493 # number of overall MSHR misses 1523system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 2093 # number of ReadReq MSHR uncacheable 1524system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15843 # number of ReadReq MSHR uncacheable 1525system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 17936 # number of ReadReq MSHR uncacheable 1526system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 17283 # number of WriteReq MSHR uncacheable 1527system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 17283 # number of WriteReq MSHR uncacheable 1528system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 2093 # number of overall MSHR uncacheable misses 1529system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 33126 # number of overall MSHR uncacheable misses 1530system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 35219 # number of overall MSHR uncacheable misses 1531system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of ReadReq MSHR miss cycles 1532system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 519315500 # number of ReadReq MSHR miss cycles 1533system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1282733500 # number of ReadReq MSHR miss cycles 1534system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 66266397744 # number of HardPFReq MSHR miss cycles 1535system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 66266397744 # number of HardPFReq MSHR miss cycles 1536system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4978129498 # number of UpgradeReq MSHR miss cycles 1537system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4978129498 # number of UpgradeReq MSHR miss cycles 1538system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3157260491 # number of SCUpgradeReq MSHR miss cycles 1539system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3157260491 # number of SCUpgradeReq MSHR miss cycles 1540system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1698499 # number of SCUpgradeFailReq MSHR miss cycles 1541system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1698499 # number of SCUpgradeFailReq MSHR miss cycles 1542system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14042647500 # number of ReadExReq MSHR miss cycles 1543system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14042647500 # number of ReadExReq MSHR miss cycles 1544system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 19039385000 # number of ReadCleanReq MSHR miss cycles 1545system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 19039385000 # number of ReadCleanReq MSHR miss cycles 1546system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 39727406492 # number of ReadSharedReq MSHR miss cycles 1547system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 39727406492 # number of ReadSharedReq MSHR miss cycles 1548system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 22010835496 # number of InvalidateReq MSHR miss cycles 1549system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 22010835496 # number of InvalidateReq MSHR miss cycles 1550system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of demand (read+write) MSHR miss cycles 1551system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 519315500 # number of demand (read+write) MSHR miss cycles 1552system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 19039385000 # number of demand (read+write) MSHR miss cycles 1553system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 53770053992 # number of demand (read+write) MSHR miss cycles 1554system.cpu0.l2cache.demand_mshr_miss_latency::total 74092172492 # number of demand (read+write) MSHR miss cycles 1555system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 763418000 # number of overall MSHR miss cycles 1556system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 519315500 # number of overall MSHR miss cycles 1557system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 19039385000 # number of overall MSHR miss cycles 1558system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 53770053992 # number of overall MSHR miss cycles 1559system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 66266397744 # number of overall MSHR miss cycles 1560system.cpu0.l2cache.overall_mshr_miss_latency::total 140358570236 # number of overall MSHR miss cycles 1561system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 185530000 # number of ReadReq MSHR uncacheable cycles 1562system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2769951000 # number of ReadReq MSHR uncacheable cycles 1563system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 2955481000 # number of ReadReq MSHR uncacheable cycles 1564system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 185530000 # number of overall MSHR uncacheable cycles 1565system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2769951000 # number of overall MSHR uncacheable cycles 1566system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 2955481000 # number of overall MSHR uncacheable cycles 1567system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for ReadReq accesses 1568system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for ReadReq accesses 1569system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.040548 # mshr miss rate for ReadReq accesses 1570system.cpu0.l2cache.WritebackClean_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for WritebackClean accesses 1571system.cpu0.l2cache.WritebackClean_mshr_miss_rate::total 0.000000 # mshr miss rate for WritebackClean accesses 1572system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1573system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1574system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999869 # mshr miss rate for UpgradeReq accesses 1575system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999869 # mshr miss rate for UpgradeReq accesses 1576system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999985 # mshr miss rate for SCUpgradeReq accesses 1577system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999985 # mshr miss rate for SCUpgradeReq accesses 1578system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1579system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1580system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.195572 # mshr miss rate for ReadExReq accesses 1581system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.195572 # mshr miss rate for ReadExReq accesses 1582system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for ReadCleanReq accesses 1583system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.100281 # mshr miss rate for ReadCleanReq accesses 1584system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.243030 # mshr miss rate for ReadSharedReq accesses 1585system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.243030 # mshr miss rate for ReadSharedReq accesses 1586system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.779439 # mshr miss rate for InvalidateReq accesses 1587system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.779439 # mshr miss rate for InvalidateReq accesses 1588system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for demand accesses 1589system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for demand accesses 1590system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for demand accesses 1591system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for demand accesses 1592system.cpu0.l2cache.demand_mshr_miss_rate::total 0.156971 # mshr miss rate for demand accesses 1593system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035374 # mshr miss rate for overall accesses 1594system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057866 # mshr miss rate for overall accesses 1595system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.100281 # mshr miss rate for overall accesses 1596system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.232190 # mshr miss rate for overall accesses 1597system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1598system.cpu0.l2cache.overall_mshr_miss_rate::total 0.231066 # mshr miss rate for overall accesses 1599system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average ReadReq mshr miss latency 1600system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average ReadReq mshr miss latency 1601system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 35519.009248 # average ReadReq mshr miss latency 1602system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average HardPFReq mshr miss latency 1603system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 69685.737512 # average HardPFReq mshr miss latency 1604system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18689.969694 # average UpgradeReq mshr miss latency 1605system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18689.969694 # average UpgradeReq mshr miss latency 1606system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15574.182095 # average SCUpgradeReq mshr miss latency 1607system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15574.182095 # average SCUpgradeReq mshr miss latency 1608system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 339699.800000 # average SCUpgradeFailReq mshr miss latency 1609system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 339699.800000 # average SCUpgradeFailReq mshr miss latency 1610system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 53111.575687 # average ReadExReq mshr miss latency 1611system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 53111.575687 # average ReadExReq mshr miss latency 1612system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average ReadCleanReq mshr miss latency 1613system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31515.273152 # average ReadCleanReq mshr miss latency 1614system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35793.164971 # average ReadSharedReq mshr miss latency 1615system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35793.164971 # average ReadSharedReq mshr miss latency 1616system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 35483.491366 # average InvalidateReq mshr miss latency 1617system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 35483.491366 # average InvalidateReq mshr miss latency 1618system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency 1619system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency 1620system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency 1621system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency 1622system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36778.321675 # average overall mshr miss latency 1623system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 31470.772529 # average overall mshr miss latency 1624system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43801.914642 # average overall mshr miss latency 1625system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31515.273152 # average overall mshr miss latency 1626system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 39124.985169 # average overall mshr miss latency 1627system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 69685.737512 # average overall mshr miss latency 1628system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 47330.602445 # average overall mshr miss latency 1629system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average ReadReq mshr uncacheable latency 1630system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 174837.530771 # average ReadReq mshr uncacheable latency 1631system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164779.270740 # average ReadReq mshr uncacheable latency 1632system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88643.096034 # average overall mshr uncacheable latency 1633system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83618.637928 # average overall mshr uncacheable latency 1634system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 83917.232176 # average overall mshr uncacheable latency 1635system.cpu0.toL2Bus.snoop_filter.tot_requests 26242800 # Total number of requests made to the snoop filter. 1636system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13504787 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1637system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 4079 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1638system.cpu0.toL2Bus.snoop_filter.tot_snoops 709472 # Total number of snoops made to the snoop filter. 1639system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 709425 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1640system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 47 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1641system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 1642system.cpu0.toL2Bus.trans_dist::ReadReq 1004788 # Transaction distribution 1643system.cpu0.toL2Bus.trans_dist::ReadResp 11688716 # Transaction distribution 1644system.cpu0.toL2Bus.trans_dist::WriteReq 17283 # Transaction distribution 1645system.cpu0.toL2Bus.trans_dist::WriteResp 17283 # Transaction distribution 1646system.cpu0.toL2Bus.trans_dist::WritebackDirty 6246434 # Transaction distribution 1647system.cpu0.toL2Bus.trans_dist::WritebackClean 8308001 # Transaction distribution 1648system.cpu0.toL2Bus.trans_dist::CleanEvict 1424808 # Transaction distribution 1649system.cpu0.toL2Bus.trans_dist::HardPFReq 1208828 # Transaction distribution 1650system.cpu0.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution 1651system.cpu0.toL2Bus.trans_dist::UpgradeReq 455562 # Transaction distribution 1652system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 363537 # Transaction distribution 1653system.cpu0.toL2Bus.trans_dist::UpgradeResp 533487 # Transaction distribution 1654system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 75 # Transaction distribution 1655system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution 1656system.cpu0.toL2Bus.trans_dist::ReadExReq 1384860 # Transaction distribution 1657system.cpu0.toL2Bus.trans_dist::ReadExResp 1359346 # Transaction distribution 1658system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6024837 # Transaction distribution 1659system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5574197 # Transaction distribution 1660system.cpu0.toL2Bus.trans_dist::InvalidateReq 855548 # Transaction distribution 1661system.cpu0.toL2Bus.trans_dist::InvalidateResp 797069 # Transaction distribution 1662system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18077450 # Packet count per connected master and slave (bytes) 1663system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 21220350 # Packet count per connected master and slave (bytes) 1664system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 431264 # Packet count per connected master and slave (bytes) 1665system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1446232 # Packet count per connected master and slave (bytes) 1666system.cpu0.toL2Bus.pkt_count::total 41175296 # Packet count per connected master and slave (bytes) 1667system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 771132816 # Cumulative packet size per connected master and slave (bytes) 1668system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 809027527 # Cumulative packet size per connected master and slave (bytes) 1669system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1639096 # Cumulative packet size per connected master and slave (bytes) 1670system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5486072 # Cumulative packet size per connected master and slave (bytes) 1671system.cpu0.toL2Bus.pkt_size::total 1587285511 # Cumulative packet size per connected master and slave (bytes) 1672system.cpu0.toL2Bus.snoops 6254740 # Total snoops (count) 1673system.cpu0.toL2Bus.snoopTraffic 129367088 # Total snoop traffic (bytes) 1674system.cpu0.toL2Bus.snoop_fanout::samples 20223636 # Request fanout histogram 1675system.cpu0.toL2Bus.snoop_fanout::mean 0.054517 # Request fanout histogram 1676system.cpu0.toL2Bus.snoop_fanout::stdev 0.227045 # Request fanout histogram 1677system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1678system.cpu0.toL2Bus.snoop_fanout::0 19121152 94.55% 94.55% # Request fanout histogram 1679system.cpu0.toL2Bus.snoop_fanout::1 1102437 5.45% 100.00% # Request fanout histogram 1680system.cpu0.toL2Bus.snoop_fanout::2 47 0.00% 100.00% # Request fanout histogram 1681system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1682system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1683system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1684system.cpu0.toL2Bus.snoop_fanout::total 20223636 # Request fanout histogram 1685system.cpu0.toL2Bus.reqLayer0.occupancy 26091767715 # Layer occupancy (ticks) 1686system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1687system.cpu0.toL2Bus.snoopLayer0.occupancy 182386585 # Layer occupancy (ticks) 1688system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1689system.cpu0.toL2Bus.respLayer0.occupancy 9045827975 # Layer occupancy (ticks) 1690system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1691system.cpu0.toL2Bus.respLayer1.occupancy 9544267214 # Layer occupancy (ticks) 1692system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1693system.cpu0.toL2Bus.respLayer2.occupancy 226891962 # Layer occupancy (ticks) 1694system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1695system.cpu0.toL2Bus.respLayer3.occupancy 761324284 # Layer occupancy (ticks) 1696system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1697system.cpu1.branchPred.lookups 124325317 # Number of BP lookups 1698system.cpu1.branchPred.condPredicted 79272164 # Number of conditional branches predicted 1699system.cpu1.branchPred.condIncorrect 6778632 # Number of conditional branches incorrect 1700system.cpu1.branchPred.BTBLookups 83479161 # Number of BTB lookups 1701system.cpu1.branchPred.BTBHits 47841396 # Number of BTB hits 1702system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1703system.cpu1.branchPred.BTBHitPct 57.309388 # BTB Hit Percentage 1704system.cpu1.branchPred.usedRAS 17874464 # Number of times the RAS was used to get a target. 1705system.cpu1.branchPred.RASInCorrect 195085 # Number of incorrect RAS predictions. 1706system.cpu1.branchPred.indirectLookups 4411145 # Number of indirect predictor lookups. 1707system.cpu1.branchPred.indirectHits 2666966 # Number of indirect target hits. 1708system.cpu1.branchPred.indirectMisses 1744179 # Number of indirect misses. 1709system.cpu1.branchPredindirectMispredicted 432386 # Number of mispredicted indirect branches. 1710system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 1711system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1712system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1713system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1714system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1715system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1716system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1717system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1718system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1719system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1720system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1721system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1722system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1723system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1724system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1725system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1726system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1727system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1728system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1729system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1730system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1731system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1732system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1733system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1734system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1735system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1736system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1737system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1738system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1739system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1740system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 1741system.cpu1.dtb.walker.walks 580775 # Table walker walks requested 1742system.cpu1.dtb.walker.walksLong 580775 # Table walker walks initiated with long descriptors 1743system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 12302 # Level at which table walker walks with long descriptors terminate 1744system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 93041 # Level at which table walker walks with long descriptors terminate 1745system.cpu1.dtb.walker.walksSquashedBefore 266909 # Table walks squashed before starting 1746system.cpu1.dtb.walker.walkWaitTime::samples 313866 # Table walker wait (enqueue to first request) latency 1747system.cpu1.dtb.walker.walkWaitTime::mean 2454.023373 # Table walker wait (enqueue to first request) latency 1748system.cpu1.dtb.walker.walkWaitTime::stdev 13953.006998 # Table walker wait (enqueue to first request) latency 1749system.cpu1.dtb.walker.walkWaitTime::0-65535 311371 99.21% 99.21% # Table walker wait (enqueue to first request) latency 1750system.cpu1.dtb.walker.walkWaitTime::65536-131071 1689 0.54% 99.74% # Table walker wait (enqueue to first request) latency 1751system.cpu1.dtb.walker.walkWaitTime::131072-196607 507 0.16% 99.90% # Table walker wait (enqueue to first request) latency 1752system.cpu1.dtb.walker.walkWaitTime::196608-262143 189 0.06% 99.96% # Table walker wait (enqueue to first request) latency 1753system.cpu1.dtb.walker.walkWaitTime::262144-327679 54 0.02% 99.98% # Table walker wait (enqueue to first request) latency 1754system.cpu1.dtb.walker.walkWaitTime::327680-393215 44 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1755system.cpu1.dtb.walker.walkWaitTime::393216-458751 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1756system.cpu1.dtb.walker.walkWaitTime::458752-524287 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1757system.cpu1.dtb.walker.walkWaitTime::524288-589823 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1758system.cpu1.dtb.walker.walkWaitTime::589824-655359 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1759system.cpu1.dtb.walker.walkWaitTime::total 313866 # Table walker wait (enqueue to first request) latency 1760system.cpu1.dtb.walker.walkCompletionTime::samples 295327 # Table walker service (enqueue to completion) latency 1761system.cpu1.dtb.walker.walkCompletionTime::mean 21717.315044 # Table walker service (enqueue to completion) latency 1762system.cpu1.dtb.walker.walkCompletionTime::gmean 18678.510143 # Table walker service (enqueue to completion) latency 1763system.cpu1.dtb.walker.walkCompletionTime::stdev 17673.432878 # Table walker service (enqueue to completion) latency 1764system.cpu1.dtb.walker.walkCompletionTime::0-65535 292731 99.12% 99.12% # Table walker service (enqueue to completion) latency 1765system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1780 0.60% 99.72% # Table walker service (enqueue to completion) latency 1766system.cpu1.dtb.walker.walkCompletionTime::131072-196607 365 0.12% 99.85% # Table walker service (enqueue to completion) latency 1767system.cpu1.dtb.walker.walkCompletionTime::196608-262143 243 0.08% 99.93% # Table walker service (enqueue to completion) latency 1768system.cpu1.dtb.walker.walkCompletionTime::262144-327679 59 0.02% 99.95% # Table walker service (enqueue to completion) latency 1769system.cpu1.dtb.walker.walkCompletionTime::327680-393215 66 0.02% 99.97% # Table walker service (enqueue to completion) latency 1770system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.00% 99.98% # Table walker service (enqueue to completion) latency 1771system.cpu1.dtb.walker.walkCompletionTime::458752-524287 14 0.00% 99.98% # Table walker service (enqueue to completion) latency 1772system.cpu1.dtb.walker.walkCompletionTime::524288-589823 10 0.00% 99.98% # Table walker service (enqueue to completion) latency 1773system.cpu1.dtb.walker.walkCompletionTime::589824-655359 35 0.01% 100.00% # Table walker service (enqueue to completion) latency 1774system.cpu1.dtb.walker.walkCompletionTime::655360-720895 14 0.00% 100.00% # Table walker service (enqueue to completion) latency 1775system.cpu1.dtb.walker.walkCompletionTime::total 295327 # Table walker service (enqueue to completion) latency 1776system.cpu1.dtb.walker.walksPending::samples 389340230128 # Table walker pending requests distribution 1777system.cpu1.dtb.walker.walksPending::mean 0.666551 # Table walker pending requests distribution 1778system.cpu1.dtb.walker.walksPending::stdev 0.555298 # Table walker pending requests distribution 1779system.cpu1.dtb.walker.walksPending::0-1 388038620628 99.67% 99.67% # Table walker pending requests distribution 1780system.cpu1.dtb.walker.walksPending::2-3 674944000 0.17% 99.84% # Table walker pending requests distribution 1781system.cpu1.dtb.walker.walksPending::4-5 273419500 0.07% 99.91% # Table walker pending requests distribution 1782system.cpu1.dtb.walker.walksPending::6-7 140502000 0.04% 99.95% # Table walker pending requests distribution 1783system.cpu1.dtb.walker.walksPending::8-9 100194000 0.03% 99.97% # Table walker pending requests distribution 1784system.cpu1.dtb.walker.walksPending::10-11 59021000 0.02% 99.99% # Table walker pending requests distribution 1785system.cpu1.dtb.walker.walksPending::12-13 22755500 0.01% 99.99% # Table walker pending requests distribution 1786system.cpu1.dtb.walker.walksPending::14-15 30241000 0.01% 100.00% # Table walker pending requests distribution 1787system.cpu1.dtb.walker.walksPending::16-17 482500 0.00% 100.00% # Table walker pending requests distribution 1788system.cpu1.dtb.walker.walksPending::18-19 50000 0.00% 100.00% # Table walker pending requests distribution 1789system.cpu1.dtb.walker.walksPending::total 389340230128 # Table walker pending requests distribution 1790system.cpu1.dtb.walker.walkPageSizes::4K 93042 88.32% 88.32% # Table walker page sizes translated 1791system.cpu1.dtb.walker.walkPageSizes::2M 12302 11.68% 100.00% # Table walker page sizes translated 1792system.cpu1.dtb.walker.walkPageSizes::total 105344 # Table walker page sizes translated 1793system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 580775 # Table walker requests started/completed, data/inst 1794system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1795system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 580775 # Table walker requests started/completed, data/inst 1796system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 105344 # Table walker requests started/completed, data/inst 1797system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1798system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 105344 # Table walker requests started/completed, data/inst 1799system.cpu1.dtb.walker.walkRequestOrigin::total 686119 # Table walker requests started/completed, data/inst 1800system.cpu1.dtb.inst_hits 0 # ITB inst hits 1801system.cpu1.dtb.inst_misses 0 # ITB inst misses 1802system.cpu1.dtb.read_hits 97816184 # DTB read hits 1803system.cpu1.dtb.read_misses 397931 # DTB read misses 1804system.cpu1.dtb.write_hits 81264416 # DTB write hits 1805system.cpu1.dtb.write_misses 182844 # DTB write misses 1806system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 1807system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1808system.cpu1.dtb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID 1809system.cpu1.dtb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID 1810system.cpu1.dtb.flush_entries 36337 # Number of entries that have been flushed from TLB 1811system.cpu1.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions 1812system.cpu1.dtb.prefetch_faults 7662 # Number of TLB faults due to prefetch 1813system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1814system.cpu1.dtb.perms_faults 41901 # Number of TLB faults due to permissions restrictions 1815system.cpu1.dtb.read_accesses 98214115 # DTB read accesses 1816system.cpu1.dtb.write_accesses 81447260 # DTB write accesses 1817system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1818system.cpu1.dtb.hits 179080600 # DTB hits 1819system.cpu1.dtb.misses 580775 # DTB misses 1820system.cpu1.dtb.accesses 179661375 # DTB accesses 1821system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 1822system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1823system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1824system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1825system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1826system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1827system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1828system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1829system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1830system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1831system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1832system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1833system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1834system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1835system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1836system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1837system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1838system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1839system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1840system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1841system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1842system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1843system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1844system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1845system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1846system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1847system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1848system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1849system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1850system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1851system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 1852system.cpu1.itb.walker.walks 87135 # Table walker walks requested 1853system.cpu1.itb.walker.walksLong 87135 # Table walker walks initiated with long descriptors 1854system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1092 # Level at which table walker walks with long descriptors terminate 1855system.cpu1.itb.walker.walksLongTerminationLevel::Level3 62581 # Level at which table walker walks with long descriptors terminate 1856system.cpu1.itb.walker.walksSquashedBefore 10397 # Table walks squashed before starting 1857system.cpu1.itb.walker.walkWaitTime::samples 76738 # Table walker wait (enqueue to first request) latency 1858system.cpu1.itb.walker.walkWaitTime::mean 1034.422320 # Table walker wait (enqueue to first request) latency 1859system.cpu1.itb.walker.walkWaitTime::stdev 9201.232348 # Table walker wait (enqueue to first request) latency 1860system.cpu1.itb.walker.walkWaitTime::0-65535 76494 99.68% 99.68% # Table walker wait (enqueue to first request) latency 1861system.cpu1.itb.walker.walkWaitTime::65536-131071 186 0.24% 99.92% # Table walker wait (enqueue to first request) latency 1862system.cpu1.itb.walker.walkWaitTime::131072-196607 34 0.04% 99.97% # Table walker wait (enqueue to first request) latency 1863system.cpu1.itb.walker.walkWaitTime::196608-262143 9 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1864system.cpu1.itb.walker.walkWaitTime::262144-327679 6 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1865system.cpu1.itb.walker.walkWaitTime::327680-393215 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1866system.cpu1.itb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1867system.cpu1.itb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1868system.cpu1.itb.walker.walkWaitTime::total 76738 # Table walker wait (enqueue to first request) latency 1869system.cpu1.itb.walker.walkCompletionTime::samples 74070 # Table walker service (enqueue to completion) latency 1870system.cpu1.itb.walker.walkCompletionTime::mean 25472.262724 # Table walker service (enqueue to completion) latency 1871system.cpu1.itb.walker.walkCompletionTime::gmean 22851.948587 # Table walker service (enqueue to completion) latency 1872system.cpu1.itb.walker.walkCompletionTime::stdev 20227.385308 # Table walker service (enqueue to completion) latency 1873system.cpu1.itb.walker.walkCompletionTime::0-65535 72813 98.30% 98.30% # Table walker service (enqueue to completion) latency 1874system.cpu1.itb.walker.walkCompletionTime::65536-131071 775 1.05% 99.35% # Table walker service (enqueue to completion) latency 1875system.cpu1.itb.walker.walkCompletionTime::131072-196607 316 0.43% 99.78% # Table walker service (enqueue to completion) latency 1876system.cpu1.itb.walker.walkCompletionTime::196608-262143 87 0.12% 99.89% # Table walker service (enqueue to completion) latency 1877system.cpu1.itb.walker.walkCompletionTime::262144-327679 33 0.04% 99.94% # Table walker service (enqueue to completion) latency 1878system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.03% 99.96% # Table walker service (enqueue to completion) latency 1879system.cpu1.itb.walker.walkCompletionTime::393216-458751 8 0.01% 99.98% # Table walker service (enqueue to completion) latency 1880system.cpu1.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.98% # Table walker service (enqueue to completion) latency 1881system.cpu1.itb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency 1882system.cpu1.itb.walker.walkCompletionTime::total 74070 # Table walker service (enqueue to completion) latency 1883system.cpu1.itb.walker.walksPending::samples 329207699984 # Table walker pending requests distribution 1884system.cpu1.itb.walker.walksPending::mean 0.888226 # Table walker pending requests distribution 1885system.cpu1.itb.walker.walksPending::stdev 0.315322 # Table walker pending requests distribution 1886system.cpu1.itb.walker.walksPending::0 36820179964 11.18% 11.18% # Table walker pending requests distribution 1887system.cpu1.itb.walker.walksPending::1 292365319520 88.81% 99.99% # Table walker pending requests distribution 1888system.cpu1.itb.walker.walksPending::2 21267000 0.01% 100.00% # Table walker pending requests distribution 1889system.cpu1.itb.walker.walksPending::3 903500 0.00% 100.00% # Table walker pending requests distribution 1890system.cpu1.itb.walker.walksPending::4 30000 0.00% 100.00% # Table walker pending requests distribution 1891system.cpu1.itb.walker.walksPending::total 329207699984 # Table walker pending requests distribution 1892system.cpu1.itb.walker.walkPageSizes::4K 62581 98.28% 98.28% # Table walker page sizes translated 1893system.cpu1.itb.walker.walkPageSizes::2M 1092 1.72% 100.00% # Table walker page sizes translated 1894system.cpu1.itb.walker.walkPageSizes::total 63673 # Table walker page sizes translated 1895system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1896system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 87135 # Table walker requests started/completed, data/inst 1897system.cpu1.itb.walker.walkRequestOrigin_Requested::total 87135 # Table walker requests started/completed, data/inst 1898system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1899system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 63673 # Table walker requests started/completed, data/inst 1900system.cpu1.itb.walker.walkRequestOrigin_Completed::total 63673 # Table walker requests started/completed, data/inst 1901system.cpu1.itb.walker.walkRequestOrigin::total 150808 # Table walker requests started/completed, data/inst 1902system.cpu1.itb.inst_hits 190777093 # ITB inst hits 1903system.cpu1.itb.inst_misses 87135 # ITB inst misses 1904system.cpu1.itb.read_hits 0 # DTB read hits 1905system.cpu1.itb.read_misses 0 # DTB read misses 1906system.cpu1.itb.write_hits 0 # DTB write hits 1907system.cpu1.itb.write_misses 0 # DTB write misses 1908system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 1909system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1910system.cpu1.itb.flush_tlb_mva_asid 47990 # Number of times TLB was flushed by MVA & ASID 1911system.cpu1.itb.flush_tlb_asid 1104 # Number of times TLB was flushed by ASID 1912system.cpu1.itb.flush_entries 25727 # Number of entries that have been flushed from TLB 1913system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1914system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1915system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1916system.cpu1.itb.perms_faults 222647 # Number of TLB faults due to permissions restrictions 1917system.cpu1.itb.read_accesses 0 # DTB read accesses 1918system.cpu1.itb.write_accesses 0 # DTB write accesses 1919system.cpu1.itb.inst_accesses 190864228 # ITB inst accesses 1920system.cpu1.itb.hits 190777093 # DTB hits 1921system.cpu1.itb.misses 87135 # DTB misses 1922system.cpu1.itb.accesses 190864228 # DTB accesses 1923system.cpu1.numPwrStateTransitions 27368 # Number of power state transitions 1924system.cpu1.pwrStateClkGateDist::samples 13684 # Distribution of time spent in the clock gated state 1925system.cpu1.pwrStateClkGateDist::mean 3437541610.585575 # Distribution of time spent in the clock gated state 1926system.cpu1.pwrStateClkGateDist::stdev 87855050570.390015 # Distribution of time spent in the clock gated state 1927system.cpu1.pwrStateClkGateDist::underflows 3277 23.95% 23.95% # Distribution of time spent in the clock gated state 1928system.cpu1.pwrStateClkGateDist::1000-5e+10 10379 75.85% 99.80% # Distribution of time spent in the clock gated state 1929system.cpu1.pwrStateClkGateDist::5e+10-1e+11 4 0.03% 99.82% # Distribution of time spent in the clock gated state 1930system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 1931system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state 1932system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state 1933system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 2 0.01% 99.89% # Distribution of time spent in the clock gated state 1934system.cpu1.pwrStateClkGateDist::8.5e+11-9e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 1935system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state 1936system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1937system.cpu1.pwrStateClkGateDist::max_value 7351150614736 # Distribution of time spent in the clock gated state 1938system.cpu1.pwrStateClkGateDist::total 13684 # Distribution of time spent in the clock gated state 1939system.cpu1.pwrStateResidencyTicks::ON 302603854747 # Cumulative time (in ticks) in various power states 1940system.cpu1.pwrStateResidencyTicks::CLK_GATED 47039319399253 # Cumulative time (in ticks) in various power states 1941system.cpu1.numCycles 605218102 # number of cpu cycles simulated 1942system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1943system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1944system.cpu1.fetch.icacheStallCycles 90677216 # Number of cycles fetch is stalled on an Icache miss 1945system.cpu1.fetch.Insts 553360207 # Number of instructions fetch has processed 1946system.cpu1.fetch.Branches 124325317 # Number of branches that fetch encountered 1947system.cpu1.fetch.predictedBranches 68382826 # Number of branches that fetch has predicted taken 1948system.cpu1.fetch.Cycles 474472155 # Number of cycles fetch has run and was not squashing or blocked 1949system.cpu1.fetch.SquashCycles 14605284 # Number of cycles fetch has spent squashing 1950system.cpu1.fetch.TlbCycles 1912826 # Number of cycles fetch has spent waiting for tlb 1951system.cpu1.fetch.MiscStallCycles 316489 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1952system.cpu1.fetch.PendingTrapStallCycles 6235887 # Number of stall cycles due to pending traps 1953system.cpu1.fetch.PendingQuiesceStallCycles 776312 # Number of stall cycles due to pending quiesce instructions 1954system.cpu1.fetch.IcacheWaitRetryStallCycles 869780 # Number of stall cycles due to full MSHR 1955system.cpu1.fetch.CacheLines 190532631 # Number of cache lines fetched 1956system.cpu1.fetch.IcacheSquashes 1731041 # Number of outstanding Icache misses that were squashed 1957system.cpu1.fetch.ItlbSquashes 28903 # Number of outstanding ITLB misses that were squashed 1958system.cpu1.fetch.rateDist::samples 582563307 # Number of instructions fetched each cycle (Total) 1959system.cpu1.fetch.rateDist::mean 1.126942 # Number of instructions fetched each cycle (Total) 1960system.cpu1.fetch.rateDist::stdev 1.253057 # Number of instructions fetched each cycle (Total) 1961system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1962system.cpu1.fetch.rateDist::0 272142185 46.71% 46.71% # Number of instructions fetched each cycle (Total) 1963system.cpu1.fetch.rateDist::1 117259342 20.13% 66.84% # Number of instructions fetched each cycle (Total) 1964system.cpu1.fetch.rateDist::2 40229436 6.91% 73.75% # Number of instructions fetched each cycle (Total) 1965system.cpu1.fetch.rateDist::3 152932344 26.25% 100.00% # Number of instructions fetched each cycle (Total) 1966system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1967system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1968system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1969system.cpu1.fetch.rateDist::total 582563307 # Number of instructions fetched each cycle (Total) 1970system.cpu1.fetch.branchRate 0.205422 # Number of branch fetches per cycle 1971system.cpu1.fetch.rate 0.914315 # Number of inst fetches per cycle 1972system.cpu1.decode.IdleCycles 100710093 # Number of cycles decode is idle 1973system.cpu1.decode.BlockedCycles 231252575 # Number of cycles decode is blocked 1974system.cpu1.decode.RunCycles 221227930 # Number of cycles decode is running 1975system.cpu1.decode.UnblockCycles 24164908 # Number of cycles decode is unblocking 1976system.cpu1.decode.SquashCycles 5207801 # Number of cycles decode is squashing 1977system.cpu1.decode.BranchResolved 44439760 # Number of times decode resolved a branch 1978system.cpu1.decode.BranchMispred 2135059 # Number of times decode detected a branch misprediction 1979system.cpu1.decode.DecodedInsts 575305987 # Number of instructions handled by decode 1980system.cpu1.decode.SquashedInsts 23412205 # Number of squashed instructions handled by decode 1981system.cpu1.rename.SquashCycles 5207801 # Number of cycles rename is squashing 1982system.cpu1.rename.IdleCycles 129334574 # Number of cycles rename is idle 1983system.cpu1.rename.BlockCycles 47434760 # Number of cycles rename is blocking 1984system.cpu1.rename.serializeStallCycles 137391497 # count of cycles rename stalled for serializing inst 1985system.cpu1.rename.RunCycles 216168101 # Number of cycles rename is running 1986system.cpu1.rename.UnblockCycles 47026574 # Number of cycles rename is unblocking 1987system.cpu1.rename.RenamedInsts 558184675 # Number of instructions processed by rename 1988system.cpu1.rename.SquashedInsts 6143864 # Number of squashed instructions processed by rename 1989system.cpu1.rename.ROBFullEvents 9881225 # Number of times rename has blocked due to ROB full 1990system.cpu1.rename.IQFullEvents 309237 # Number of times rename has blocked due to IQ full 1991system.cpu1.rename.LQFullEvents 251476 # Number of times rename has blocked due to LQ full 1992system.cpu1.rename.SQFullEvents 25589786 # Number of times rename has blocked due to SQ full 1993system.cpu1.rename.FullRegisterEvents 13193 # Number of times there has been no free registers 1994system.cpu1.rename.RenamedOperands 510403185 # Number of destination operands rename has renamed 1995system.cpu1.rename.RenameLookups 786411891 # Number of register rename lookups that rename has made 1996system.cpu1.rename.int_rename_lookups 655895321 # Number of integer rename lookups 1997system.cpu1.rename.fp_rename_lookups 811726 # Number of floating rename lookups 1998system.cpu1.rename.CommittedMaps 453487095 # Number of HB maps that are committed 1999system.cpu1.rename.UndoneMaps 56916084 # Number of HB maps that are undone due to squashing 2000system.cpu1.rename.serializingInsts 6219044 # count of serializing insts renamed 2001system.cpu1.rename.tempSerializingInsts 4304916 # count of temporary serializing insts renamed 2002system.cpu1.rename.skidInsts 51458924 # count of insts added to the skid buffer 2003system.cpu1.memDep0.insertedLoads 98128925 # Number of loads inserted to the mem dependence unit. 2004system.cpu1.memDep0.insertedStores 84474197 # Number of stores inserted to the mem dependence unit. 2005system.cpu1.memDep0.conflictingLoads 8967706 # Number of conflicting loads. 2006system.cpu1.memDep0.conflictingStores 7764120 # Number of conflicting stores. 2007system.cpu1.iq.iqInstsAdded 545083370 # Number of instructions added to the IQ (excludes non-spec) 2008system.cpu1.iq.iqNonSpecInstsAdded 6336595 # Number of non-speculative instructions added to the IQ 2009system.cpu1.iq.iqInstsIssued 540345314 # Number of instructions issued 2010system.cpu1.iq.iqSquashedInstsIssued 2650065 # Number of squashed instructions issued 2011system.cpu1.iq.iqSquashedInstsExamined 53579246 # Number of squashed instructions iterated over during squash; mainly for profiling 2012system.cpu1.iq.iqSquashedOperandsExamined 34592760 # Number of squashed operands that are examined and possibly removed from graph 2013system.cpu1.iq.iqSquashedNonSpecRemoved 257601 # Number of squashed non-spec instructions that were removed 2014system.cpu1.iq.issued_per_cycle::samples 582563307 # Number of insts issued each cycle 2015system.cpu1.iq.issued_per_cycle::mean 0.927531 # Number of insts issued each cycle 2016system.cpu1.iq.issued_per_cycle::stdev 1.122571 # Number of insts issued each cycle 2017system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2018system.cpu1.iq.issued_per_cycle::0 303220433 52.05% 52.05% # Number of insts issued each cycle 2019system.cpu1.iq.issued_per_cycle::1 97196070 16.68% 68.73% # Number of insts issued each cycle 2020system.cpu1.iq.issued_per_cycle::2 110913519 19.04% 87.77% # Number of insts issued each cycle 2021system.cpu1.iq.issued_per_cycle::3 63614426 10.92% 98.69% # Number of insts issued each cycle 2022system.cpu1.iq.issued_per_cycle::4 7615367 1.31% 100.00% # Number of insts issued each cycle 2023system.cpu1.iq.issued_per_cycle::5 3492 0.00% 100.00% # Number of insts issued each cycle 2024system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2025system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2026system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2027system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2028system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2029system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 2030system.cpu1.iq.issued_per_cycle::total 582563307 # Number of insts issued each cycle 2031system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2032system.cpu1.iq.fu_full::IntAlu 57271310 43.60% 43.60% # attempts to use FU when none available 2033system.cpu1.iq.fu_full::IntMult 51119 0.04% 43.64% # attempts to use FU when none available 2034system.cpu1.iq.fu_full::IntDiv 18601 0.01% 43.65% # attempts to use FU when none available 2035system.cpu1.iq.fu_full::FloatAdd 0 0.00% 43.65% # attempts to use FU when none available 2036system.cpu1.iq.fu_full::FloatCmp 0 0.00% 43.65% # attempts to use FU when none available 2037system.cpu1.iq.fu_full::FloatCvt 0 0.00% 43.65% # attempts to use FU when none available 2038system.cpu1.iq.fu_full::FloatMult 0 0.00% 43.65% # attempts to use FU when none available 2039system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available 2040system.cpu1.iq.fu_full::FloatDiv 0 0.00% 43.65% # attempts to use FU when none available 2041system.cpu1.iq.fu_full::FloatMisc 112 0.00% 43.65% # attempts to use FU when none available 2042system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 43.65% # attempts to use FU when none available 2043system.cpu1.iq.fu_full::SimdAdd 0 0.00% 43.65% # attempts to use FU when none available 2044system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 43.65% # attempts to use FU when none available 2045system.cpu1.iq.fu_full::SimdAlu 0 0.00% 43.65% # attempts to use FU when none available 2046system.cpu1.iq.fu_full::SimdCmp 0 0.00% 43.65% # attempts to use FU when none available 2047system.cpu1.iq.fu_full::SimdCvt 0 0.00% 43.65% # attempts to use FU when none available 2048system.cpu1.iq.fu_full::SimdMisc 0 0.00% 43.65% # attempts to use FU when none available 2049system.cpu1.iq.fu_full::SimdMult 0 0.00% 43.65% # attempts to use FU when none available 2050system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 43.65% # attempts to use FU when none available 2051system.cpu1.iq.fu_full::SimdShift 0 0.00% 43.65% # attempts to use FU when none available 2052system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 43.65% # attempts to use FU when none available 2053system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 43.65% # attempts to use FU when none available 2054system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 43.65% # attempts to use FU when none available 2055system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 43.65% # attempts to use FU when none available 2056system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 43.65% # attempts to use FU when none available 2057system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 43.65% # attempts to use FU when none available 2058system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 43.65% # attempts to use FU when none available 2059system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 43.65% # attempts to use FU when none available 2060system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 43.65% # attempts to use FU when none available 2061system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.65% # attempts to use FU when none available 2062system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 43.65% # attempts to use FU when none available 2063system.cpu1.iq.fu_full::MemRead 35025270 26.66% 70.31% # attempts to use FU when none available 2064system.cpu1.iq.fu_full::MemWrite 38581798 29.37% 99.68% # attempts to use FU when none available 2065system.cpu1.iq.fu_full::FloatMemRead 47664 0.04% 99.72% # attempts to use FU when none available 2066system.cpu1.iq.fu_full::FloatMemWrite 368619 0.28% 100.00% # attempts to use FU when none available 2067system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2068system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2069system.cpu1.iq.FU_type_0::No_OpClass 76 0.00% 0.00% # Type of FU issued 2070system.cpu1.iq.FU_type_0::IntAlu 355477037 65.79% 65.79% # Type of FU issued 2071system.cpu1.iq.FU_type_0::IntMult 1278002 0.24% 66.02% # Type of FU issued 2072system.cpu1.iq.FU_type_0::IntDiv 69863 0.01% 66.04% # Type of FU issued 2073system.cpu1.iq.FU_type_0::FloatAdd 8 0.00% 66.04% # Type of FU issued 2074system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.04% # Type of FU issued 2075system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.04% # Type of FU issued 2076system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.04% # Type of FU issued 2077system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 66.04% # Type of FU issued 2078system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.04% # Type of FU issued 2079system.cpu1.iq.FU_type_0::FloatMisc 79928 0.01% 66.05% # Type of FU issued 2080system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.05% # Type of FU issued 2081system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.05% # Type of FU issued 2082system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.05% # Type of FU issued 2083system.cpu1.iq.FU_type_0::SimdAlu 1 0.00% 66.05% # Type of FU issued 2084system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.05% # Type of FU issued 2085system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.05% # Type of FU issued 2086system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.05% # Type of FU issued 2087system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.05% # Type of FU issued 2088system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.05% # Type of FU issued 2089system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.05% # Type of FU issued 2090system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.05% # Type of FU issued 2091system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.05% # Type of FU issued 2092system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.05% # Type of FU issued 2093system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.05% # Type of FU issued 2094system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.05% # Type of FU issued 2095system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.05% # Type of FU issued 2096system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.05% # Type of FU issued 2097system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.05% # Type of FU issued 2098system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.05% # Type of FU issued 2099system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.05% # Type of FU issued 2100system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.05% # Type of FU issued 2101system.cpu1.iq.FU_type_0::MemRead 100880874 18.67% 84.72% # Type of FU issued 2102system.cpu1.iq.FU_type_0::MemWrite 82125393 15.20% 99.92% # Type of FU issued 2103system.cpu1.iq.FU_type_0::FloatMemRead 69486 0.01% 99.93% # Type of FU issued 2104system.cpu1.iq.FU_type_0::FloatMemWrite 364646 0.07% 100.00% # Type of FU issued 2105system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2106system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2107system.cpu1.iq.FU_type_0::total 540345314 # Type of FU issued 2108system.cpu1.iq.rate 0.892811 # Inst issue rate 2109system.cpu1.iq.fu_busy_cnt 131364493 # FU busy when requested 2110system.cpu1.iq.fu_busy_rate 0.243112 # FU busy rate (busy events/executed inst) 2111system.cpu1.iq.int_inst_queue_reads 1795817951 # Number of integer instruction queue reads 2112system.cpu1.iq.int_inst_queue_writes 604594628 # Number of integer instruction queue writes 2113system.cpu1.iq.int_inst_queue_wakeup_accesses 523100921 # Number of integer instruction queue wakeup accesses 2114system.cpu1.iq.fp_inst_queue_reads 1450540 # Number of floating instruction queue reads 2115system.cpu1.iq.fp_inst_queue_writes 543567 # Number of floating instruction queue writes 2116system.cpu1.iq.fp_inst_queue_wakeup_accesses 507957 # Number of floating instruction queue wakeup accesses 2117system.cpu1.iq.int_alu_accesses 670779267 # Number of integer alu accesses 2118system.cpu1.iq.fp_alu_accesses 930464 # Number of floating point alu accesses 2119system.cpu1.iew.lsq.thread0.forwLoads 2614124 # Number of loads that had data forwarded from stores 2120system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2121system.cpu1.iew.lsq.thread0.squashedLoads 12461558 # Number of loads squashed 2122system.cpu1.iew.lsq.thread0.ignoredResponses 17016 # Number of memory responses ignored because the instruction is squashed 2123system.cpu1.iew.lsq.thread0.memOrderViolation 140230 # Number of memory ordering violations 2124system.cpu1.iew.lsq.thread0.squashedStores 5490502 # Number of stores squashed 2125system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2126system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2127system.cpu1.iew.lsq.thread0.rescheduledLoads 2570995 # Number of loads that were rescheduled 2128system.cpu1.iew.lsq.thread0.cacheBlocked 4304841 # Number of times an access to memory failed due to the cache being blocked 2129system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2130system.cpu1.iew.iewSquashCycles 5207801 # Number of cycles IEW is squashing 2131system.cpu1.iew.iewBlockCycles 6764064 # Number of cycles IEW is blocking 2132system.cpu1.iew.iewUnblockCycles 1538743 # Number of cycles IEW is unblocking 2133system.cpu1.iew.iewDispatchedInsts 551558167 # Number of instructions dispatched to IQ 2134system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2135system.cpu1.iew.iewDispLoadInsts 98128925 # Number of dispatched load instructions 2136system.cpu1.iew.iewDispStoreInsts 84474197 # Number of dispatched store instructions 2137system.cpu1.iew.iewDispNonSpecInsts 4043182 # Number of dispatched non-speculative instructions 2138system.cpu1.iew.iewIQFullEvents 70701 # Number of times the IQ has become full, causing a stall 2139system.cpu1.iew.iewLSQFullEvents 1397089 # Number of times the LSQ has become full, causing a stall 2140system.cpu1.iew.memOrderViolationEvents 140230 # Number of memory order violations 2141system.cpu1.iew.predictedTakenIncorrect 1929682 # Number of branches that were predicted taken incorrectly 2142system.cpu1.iew.predictedNotTakenIncorrect 3114694 # Number of branches that were predicted not taken incorrectly 2143system.cpu1.iew.branchMispredicts 5044376 # Number of branch mispredicts detected at execute 2144system.cpu1.iew.iewExecutedInsts 532413736 # Number of executed instructions 2145system.cpu1.iew.iewExecLoadInsts 97811900 # Number of load instructions executed 2146system.cpu1.iew.iewExecSquashedInsts 7363284 # Number of squashed instructions skipped in execute 2147system.cpu1.iew.exec_swp 0 # number of swp insts executed 2148system.cpu1.iew.exec_nop 138202 # number of nop insts executed 2149system.cpu1.iew.exec_refs 179076621 # number of memory reference insts executed 2150system.cpu1.iew.exec_branches 97312103 # Number of branches executed 2151system.cpu1.iew.exec_stores 81264721 # Number of stores executed 2152system.cpu1.iew.exec_rate 0.879706 # Inst execution rate 2153system.cpu1.iew.wb_sent 524373694 # cumulative count of insts sent to commit 2154system.cpu1.iew.wb_count 523608878 # cumulative count of insts written-back 2155system.cpu1.iew.wb_producers 254758095 # num instructions producing a value 2156system.cpu1.iew.wb_consumers 415275761 # num instructions consuming a value 2157system.cpu1.iew.wb_rate 0.865157 # insts written-back per cycle 2158system.cpu1.iew.wb_fanout 0.613467 # average fanout of values written-back 2159system.cpu1.commit.commitSquashedInsts 46732947 # The number of squashed insts skipped by commit 2160system.cpu1.commit.commitNonSpecStalls 6078994 # The number of times commit has been forced to stall to communicate backwards 2161system.cpu1.commit.branchMispredicts 4683791 # The number of times a branch was mispredicted 2162system.cpu1.commit.committed_per_cycle::samples 573586803 # Number of insts commited each cycle 2163system.cpu1.commit.committed_per_cycle::mean 0.867943 # Number of insts commited each cycle 2164system.cpu1.commit.committed_per_cycle::stdev 1.693393 # Number of insts commited each cycle 2165system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2166system.cpu1.commit.committed_per_cycle::0 375218582 65.42% 65.42% # Number of insts commited each cycle 2167system.cpu1.commit.committed_per_cycle::1 85397429 14.89% 80.30% # Number of insts commited each cycle 2168system.cpu1.commit.committed_per_cycle::2 52348334 9.13% 89.43% # Number of insts commited each cycle 2169system.cpu1.commit.committed_per_cycle::3 17503204 3.05% 92.48% # Number of insts commited each cycle 2170system.cpu1.commit.committed_per_cycle::4 12415456 2.16% 94.65% # Number of insts commited each cycle 2171system.cpu1.commit.committed_per_cycle::5 8370820 1.46% 96.11% # Number of insts commited each cycle 2172system.cpu1.commit.committed_per_cycle::6 5748485 1.00% 97.11% # Number of insts commited each cycle 2173system.cpu1.commit.committed_per_cycle::7 3445775 0.60% 97.71% # Number of insts commited each cycle 2174system.cpu1.commit.committed_per_cycle::8 13138718 2.29% 100.00% # Number of insts commited each cycle 2175system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2176system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2177system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2178system.cpu1.commit.committed_per_cycle::total 573586803 # Number of insts commited each cycle 2179system.cpu1.commit.committedInsts 416374803 # Number of instructions committed 2180system.cpu1.commit.committedOps 497840712 # Number of ops (including micro ops) committed 2181system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2182system.cpu1.commit.refs 164651061 # Number of memory references committed 2183system.cpu1.commit.loads 85667366 # Number of loads committed 2184system.cpu1.commit.membars 3698541 # Number of memory barriers committed 2185system.cpu1.commit.branches 91988554 # Number of branches committed 2186system.cpu1.commit.fp_insts 499479 # Number of committed floating point instructions. 2187system.cpu1.commit.int_insts 463071817 # Number of committed integer instructions. 2188system.cpu1.commit.function_calls 13152854 # Number of function calls committed. 2189system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2190system.cpu1.commit.op_class_0::IntAlu 332017365 66.69% 66.69% # Class of committed instruction 2191system.cpu1.commit.op_class_0::IntMult 1043826 0.21% 66.90% # Class of committed instruction 2192system.cpu1.commit.op_class_0::IntDiv 55377 0.01% 66.91% # Class of committed instruction 2193system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 66.91% # Class of committed instruction 2194system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 66.91% # Class of committed instruction 2195system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 66.91% # Class of committed instruction 2196system.cpu1.commit.op_class_0::FloatMult 0 0.00% 66.91% # Class of committed instruction 2197system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 66.91% # Class of committed instruction 2198system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 66.91% # Class of committed instruction 2199system.cpu1.commit.op_class_0::FloatMisc 73083 0.01% 66.93% # Class of committed instruction 2200system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 66.93% # Class of committed instruction 2201system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 66.93% # Class of committed instruction 2202system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 66.93% # Class of committed instruction 2203system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 66.93% # Class of committed instruction 2204system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 66.93% # Class of committed instruction 2205system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 66.93% # Class of committed instruction 2206system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 66.93% # Class of committed instruction 2207system.cpu1.commit.op_class_0::SimdMult 0 0.00% 66.93% # Class of committed instruction 2208system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 66.93% # Class of committed instruction 2209system.cpu1.commit.op_class_0::SimdShift 0 0.00% 66.93% # Class of committed instruction 2210system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 66.93% # Class of committed instruction 2211system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 66.93% # Class of committed instruction 2212system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 66.93% # Class of committed instruction 2213system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 66.93% # Class of committed instruction 2214system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 66.93% # Class of committed instruction 2215system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 66.93% # Class of committed instruction 2216system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 66.93% # Class of committed instruction 2217system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 66.93% # Class of committed instruction 2218system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 66.93% # Class of committed instruction 2219system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.93% # Class of committed instruction 2220system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.93% # Class of committed instruction 2221system.cpu1.commit.op_class_0::MemRead 85601974 17.19% 84.12% # Class of committed instruction 2222system.cpu1.commit.op_class_0::MemWrite 78622691 15.79% 99.91% # Class of committed instruction 2223system.cpu1.commit.op_class_0::FloatMemRead 65392 0.01% 99.93% # Class of committed instruction 2224system.cpu1.commit.op_class_0::FloatMemWrite 361004 0.07% 100.00% # Class of committed instruction 2225system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2226system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2227system.cpu1.commit.op_class_0::total 497840712 # Class of committed instruction 2228system.cpu1.commit.bw_lim_events 13138718 # number cycles where commit BW limit reached 2229system.cpu1.rob.rob_reads 1100782906 # The number of ROB reads 2230system.cpu1.rob.rob_writes 1098088032 # The number of ROB writes 2231system.cpu1.timesIdled 993023 # Number of times that the entire CPU went into an idle state and unscheduled itself 2232system.cpu1.idleCycles 22654795 # Total number of cycles that the CPU has spent unscheduled due to idling 2233system.cpu1.quiesceCycles 94078628435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2234system.cpu1.committedInsts 416374803 # Number of Instructions Simulated 2235system.cpu1.committedOps 497840712 # Number of Ops (including micro ops) Simulated 2236system.cpu1.cpi 1.453542 # CPI: Cycles Per Instruction 2237system.cpu1.cpi_total 1.453542 # CPI: Total CPI of All Threads 2238system.cpu1.ipc 0.687975 # IPC: Instructions Per Cycle 2239system.cpu1.ipc_total 0.687975 # IPC: Total IPC of All Threads 2240system.cpu1.int_regfile_reads 625781479 # number of integer regfile reads 2241system.cpu1.int_regfile_writes 379830432 # number of integer regfile writes 2242system.cpu1.fp_regfile_reads 798661 # number of floating regfile reads 2243system.cpu1.fp_regfile_writes 473896 # number of floating regfile writes 2244system.cpu1.cc_regfile_reads 94918566 # number of cc regfile reads 2245system.cpu1.cc_regfile_writes 95638413 # number of cc regfile writes 2246system.cpu1.misc_regfile_reads 1053266822 # number of misc regfile reads 2247system.cpu1.misc_regfile_writes 6252018 # number of misc regfile writes 2248system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 2249system.cpu1.dcache.tags.replacements 5530000 # number of replacements 2250system.cpu1.dcache.tags.tagsinuse 456.074004 # Cycle average of tags in use 2251system.cpu1.dcache.tags.total_refs 153151228 # Total number of references to valid blocks. 2252system.cpu1.dcache.tags.sampled_refs 5530512 # Sample count of references to valid blocks. 2253system.cpu1.dcache.tags.avg_refs 27.692052 # Average number of references to valid blocks. 2254system.cpu1.dcache.tags.warmup_cycle 8516003368500 # Cycle when the warmup percentage was hit. 2255system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.074004 # Average occupied blocks per requestor 2256system.cpu1.dcache.tags.occ_percent::cpu1.data 0.890770 # Average percentage of cache occupancy 2257system.cpu1.dcache.tags.occ_percent::total 0.890770 # Average percentage of cache occupancy 2258system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2259system.cpu1.dcache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id 2260system.cpu1.dcache.tags.age_task_id_blocks_1024::1 402 # Occupied blocks per task id 2261system.cpu1.dcache.tags.age_task_id_blocks_1024::2 12 # Occupied blocks per task id 2262system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2263system.cpu1.dcache.tags.tag_accesses 341526918 # Number of tag accesses 2264system.cpu1.dcache.tags.data_accesses 341526918 # Number of data accesses 2265system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 2266system.cpu1.dcache.ReadReq_hits::cpu1.data 79602961 # number of ReadReq hits 2267system.cpu1.dcache.ReadReq_hits::total 79602961 # number of ReadReq hits 2268system.cpu1.dcache.WriteReq_hits::cpu1.data 68799990 # number of WriteReq hits 2269system.cpu1.dcache.WriteReq_hits::total 68799990 # number of WriteReq hits 2270system.cpu1.dcache.SoftPFReq_hits::cpu1.data 187687 # number of SoftPFReq hits 2271system.cpu1.dcache.SoftPFReq_hits::total 187687 # number of SoftPFReq hits 2272system.cpu1.dcache.WriteLineReq_hits::cpu1.data 159948 # number of WriteLineReq hits 2273system.cpu1.dcache.WriteLineReq_hits::total 159948 # number of WriteLineReq hits 2274system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1827869 # number of LoadLockedReq hits 2275system.cpu1.dcache.LoadLockedReq_hits::total 1827869 # number of LoadLockedReq hits 2276system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1836377 # number of StoreCondReq hits 2277system.cpu1.dcache.StoreCondReq_hits::total 1836377 # number of StoreCondReq hits 2278system.cpu1.dcache.demand_hits::cpu1.data 148562899 # number of demand (read+write) hits 2279system.cpu1.dcache.demand_hits::total 148562899 # number of demand (read+write) hits 2280system.cpu1.dcache.overall_hits::cpu1.data 148750586 # number of overall hits 2281system.cpu1.dcache.overall_hits::total 148750586 # number of overall hits 2282system.cpu1.dcache.ReadReq_misses::cpu1.data 6412648 # number of ReadReq misses 2283system.cpu1.dcache.ReadReq_misses::total 6412648 # number of ReadReq misses 2284system.cpu1.dcache.WriteReq_misses::cpu1.data 7514708 # number of WriteReq misses 2285system.cpu1.dcache.WriteReq_misses::total 7514708 # number of WriteReq misses 2286system.cpu1.dcache.SoftPFReq_misses::cpu1.data 707982 # number of SoftPFReq misses 2287system.cpu1.dcache.SoftPFReq_misses::total 707982 # number of SoftPFReq misses 2288system.cpu1.dcache.WriteLineReq_misses::cpu1.data 465981 # number of WriteLineReq misses 2289system.cpu1.dcache.WriteLineReq_misses::total 465981 # number of WriteLineReq misses 2290system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 246351 # number of LoadLockedReq misses 2291system.cpu1.dcache.LoadLockedReq_misses::total 246351 # number of LoadLockedReq misses 2292system.cpu1.dcache.StoreCondReq_misses::cpu1.data 195484 # number of StoreCondReq misses 2293system.cpu1.dcache.StoreCondReq_misses::total 195484 # number of StoreCondReq misses 2294system.cpu1.dcache.demand_misses::cpu1.data 14393337 # number of demand (read+write) misses 2295system.cpu1.dcache.demand_misses::total 14393337 # number of demand (read+write) misses 2296system.cpu1.dcache.overall_misses::cpu1.data 15101319 # number of overall misses 2297system.cpu1.dcache.overall_misses::total 15101319 # number of overall misses 2298system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 101710324000 # number of ReadReq miss cycles 2299system.cpu1.dcache.ReadReq_miss_latency::total 101710324000 # number of ReadReq miss cycles 2300system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 138164152559 # number of WriteReq miss cycles 2301system.cpu1.dcache.WriteReq_miss_latency::total 138164152559 # number of WriteReq miss cycles 2302system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10841403957 # number of WriteLineReq miss cycles 2303system.cpu1.dcache.WriteLineReq_miss_latency::total 10841403957 # number of WriteLineReq miss cycles 2304system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3505750500 # number of LoadLockedReq miss cycles 2305system.cpu1.dcache.LoadLockedReq_miss_latency::total 3505750500 # number of LoadLockedReq miss cycles 2306system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4668207500 # number of StoreCondReq miss cycles 2307system.cpu1.dcache.StoreCondReq_miss_latency::total 4668207500 # number of StoreCondReq miss cycles 2308system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2827500 # number of StoreCondFailReq miss cycles 2309system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2827500 # number of StoreCondFailReq miss cycles 2310system.cpu1.dcache.demand_miss_latency::cpu1.data 250715880516 # number of demand (read+write) miss cycles 2311system.cpu1.dcache.demand_miss_latency::total 250715880516 # number of demand (read+write) miss cycles 2312system.cpu1.dcache.overall_miss_latency::cpu1.data 250715880516 # number of overall miss cycles 2313system.cpu1.dcache.overall_miss_latency::total 250715880516 # number of overall miss cycles 2314system.cpu1.dcache.ReadReq_accesses::cpu1.data 86015609 # number of ReadReq accesses(hits+misses) 2315system.cpu1.dcache.ReadReq_accesses::total 86015609 # number of ReadReq accesses(hits+misses) 2316system.cpu1.dcache.WriteReq_accesses::cpu1.data 76314698 # number of WriteReq accesses(hits+misses) 2317system.cpu1.dcache.WriteReq_accesses::total 76314698 # number of WriteReq accesses(hits+misses) 2318system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 895669 # number of SoftPFReq accesses(hits+misses) 2319system.cpu1.dcache.SoftPFReq_accesses::total 895669 # number of SoftPFReq accesses(hits+misses) 2320system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 625929 # number of WriteLineReq accesses(hits+misses) 2321system.cpu1.dcache.WriteLineReq_accesses::total 625929 # number of WriteLineReq accesses(hits+misses) 2322system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2074220 # number of LoadLockedReq accesses(hits+misses) 2323system.cpu1.dcache.LoadLockedReq_accesses::total 2074220 # number of LoadLockedReq accesses(hits+misses) 2324system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2031861 # number of StoreCondReq accesses(hits+misses) 2325system.cpu1.dcache.StoreCondReq_accesses::total 2031861 # number of StoreCondReq accesses(hits+misses) 2326system.cpu1.dcache.demand_accesses::cpu1.data 162956236 # number of demand (read+write) accesses 2327system.cpu1.dcache.demand_accesses::total 162956236 # number of demand (read+write) accesses 2328system.cpu1.dcache.overall_accesses::cpu1.data 163851905 # number of overall (read+write) accesses 2329system.cpu1.dcache.overall_accesses::total 163851905 # number of overall (read+write) accesses 2330system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.074552 # miss rate for ReadReq accesses 2331system.cpu1.dcache.ReadReq_miss_rate::total 0.074552 # miss rate for ReadReq accesses 2332system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.098470 # miss rate for WriteReq accesses 2333system.cpu1.dcache.WriteReq_miss_rate::total 0.098470 # miss rate for WriteReq accesses 2334system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.790450 # miss rate for SoftPFReq accesses 2335system.cpu1.dcache.SoftPFReq_miss_rate::total 0.790450 # miss rate for SoftPFReq accesses 2336system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.744463 # miss rate for WriteLineReq accesses 2337system.cpu1.dcache.WriteLineReq_miss_rate::total 0.744463 # miss rate for WriteLineReq accesses 2338system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118768 # miss rate for LoadLockedReq accesses 2339system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118768 # miss rate for LoadLockedReq accesses 2340system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.096209 # miss rate for StoreCondReq accesses 2341system.cpu1.dcache.StoreCondReq_miss_rate::total 0.096209 # miss rate for StoreCondReq accesses 2342system.cpu1.dcache.demand_miss_rate::cpu1.data 0.088326 # miss rate for demand accesses 2343system.cpu1.dcache.demand_miss_rate::total 0.088326 # miss rate for demand accesses 2344system.cpu1.dcache.overall_miss_rate::cpu1.data 0.092164 # miss rate for overall accesses 2345system.cpu1.dcache.overall_miss_rate::total 0.092164 # miss rate for overall accesses 2346system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15860.893035 # average ReadReq miss latency 2347system.cpu1.dcache.ReadReq_avg_miss_latency::total 15860.893035 # average ReadReq miss latency 2348system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18385.831167 # average WriteReq miss latency 2349system.cpu1.dcache.WriteReq_avg_miss_latency::total 18385.831167 # average WriteReq miss latency 2350system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23265.763962 # average WriteLineReq miss latency 2351system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 23265.763962 # average WriteLineReq miss latency 2352system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14230.713494 # average LoadLockedReq miss latency 2353system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14230.713494 # average LoadLockedReq miss latency 2354system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23880.253627 # average StoreCondReq miss latency 2355system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23880.253627 # average StoreCondReq miss latency 2356system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2357system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2358system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17418.884899 # average overall miss latency 2359system.cpu1.dcache.demand_avg_miss_latency::total 17418.884899 # average overall miss latency 2360system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16602.250473 # average overall miss latency 2361system.cpu1.dcache.overall_avg_miss_latency::total 16602.250473 # average overall miss latency 2362system.cpu1.dcache.blocked_cycles::no_mshrs 2802154 # number of cycles access was blocked 2363system.cpu1.dcache.blocked_cycles::no_targets 21903502 # number of cycles access was blocked 2364system.cpu1.dcache.blocked::no_mshrs 386416 # number of cycles access was blocked 2365system.cpu1.dcache.blocked::no_targets 756136 # number of cycles access was blocked 2366system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.251651 # average number of cycles each access was blocked 2367system.cpu1.dcache.avg_blocked_cycles::no_targets 28.967675 # average number of cycles each access was blocked 2368system.cpu1.dcache.writebacks::writebacks 5530029 # number of writebacks 2369system.cpu1.dcache.writebacks::total 5530029 # number of writebacks 2370system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3294839 # number of ReadReq MSHR hits 2371system.cpu1.dcache.ReadReq_mshr_hits::total 3294839 # number of ReadReq MSHR hits 2372system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 6084278 # number of WriteReq MSHR hits 2373system.cpu1.dcache.WriteReq_mshr_hits::total 6084278 # number of WriteReq MSHR hits 2374system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3511 # number of WriteLineReq MSHR hits 2375system.cpu1.dcache.WriteLineReq_mshr_hits::total 3511 # number of WriteLineReq MSHR hits 2376system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 126189 # number of LoadLockedReq MSHR hits 2377system.cpu1.dcache.LoadLockedReq_mshr_hits::total 126189 # number of LoadLockedReq MSHR hits 2378system.cpu1.dcache.demand_mshr_hits::cpu1.data 9382628 # number of demand (read+write) MSHR hits 2379system.cpu1.dcache.demand_mshr_hits::total 9382628 # number of demand (read+write) MSHR hits 2380system.cpu1.dcache.overall_mshr_hits::cpu1.data 9382628 # number of overall MSHR hits 2381system.cpu1.dcache.overall_mshr_hits::total 9382628 # number of overall MSHR hits 2382system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3117809 # number of ReadReq MSHR misses 2383system.cpu1.dcache.ReadReq_mshr_misses::total 3117809 # number of ReadReq MSHR misses 2384system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1430430 # number of WriteReq MSHR misses 2385system.cpu1.dcache.WriteReq_mshr_misses::total 1430430 # number of WriteReq MSHR misses 2386system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 707901 # number of SoftPFReq MSHR misses 2387system.cpu1.dcache.SoftPFReq_mshr_misses::total 707901 # number of SoftPFReq MSHR misses 2388system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 462470 # number of WriteLineReq MSHR misses 2389system.cpu1.dcache.WriteLineReq_mshr_misses::total 462470 # number of WriteLineReq MSHR misses 2390system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 120162 # number of LoadLockedReq MSHR misses 2391system.cpu1.dcache.LoadLockedReq_mshr_misses::total 120162 # number of LoadLockedReq MSHR misses 2392system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 195479 # number of StoreCondReq MSHR misses 2393system.cpu1.dcache.StoreCondReq_mshr_misses::total 195479 # number of StoreCondReq MSHR misses 2394system.cpu1.dcache.demand_mshr_misses::cpu1.data 5010709 # number of demand (read+write) MSHR misses 2395system.cpu1.dcache.demand_mshr_misses::total 5010709 # number of demand (read+write) MSHR misses 2396system.cpu1.dcache.overall_mshr_misses::cpu1.data 5718610 # number of overall MSHR misses 2397system.cpu1.dcache.overall_mshr_misses::total 5718610 # number of overall MSHR misses 2398system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable 2399system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22964 # number of ReadReq MSHR uncacheable 2400system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable 2401system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable 2402system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses 2403system.cpu1.dcache.overall_mshr_uncacheable_misses::total 44370 # number of overall MSHR uncacheable misses 2404system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 44191154500 # number of ReadReq MSHR miss cycles 2405system.cpu1.dcache.ReadReq_mshr_miss_latency::total 44191154500 # number of ReadReq MSHR miss cycles 2406system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 27737660597 # number of WriteReq MSHR miss cycles 2407system.cpu1.dcache.WriteReq_mshr_miss_latency::total 27737660597 # number of WriteReq MSHR miss cycles 2408system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 17972389000 # number of SoftPFReq MSHR miss cycles 2409system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 17972389000 # number of SoftPFReq MSHR miss cycles 2410system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10263027957 # number of WriteLineReq MSHR miss cycles 2411system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10263027957 # number of WriteLineReq MSHR miss cycles 2412system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1602495500 # number of LoadLockedReq MSHR miss cycles 2413system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1602495500 # number of LoadLockedReq MSHR miss cycles 2414system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4472798500 # number of StoreCondReq MSHR miss cycles 2415system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4472798500 # number of StoreCondReq MSHR miss cycles 2416system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2757500 # number of StoreCondFailReq MSHR miss cycles 2417system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2757500 # number of StoreCondFailReq MSHR miss cycles 2418system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 82191843054 # number of demand (read+write) MSHR miss cycles 2419system.cpu1.dcache.demand_mshr_miss_latency::total 82191843054 # number of demand (read+write) MSHR miss cycles 2420system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 100164232054 # number of overall MSHR miss cycles 2421system.cpu1.dcache.overall_mshr_miss_latency::total 100164232054 # number of overall MSHR miss cycles 2422system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4057567500 # number of ReadReq MSHR uncacheable cycles 2423system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4057567500 # number of ReadReq MSHR uncacheable cycles 2424system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4057567500 # number of overall MSHR uncacheable cycles 2425system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4057567500 # number of overall MSHR uncacheable cycles 2426system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036247 # mshr miss rate for ReadReq accesses 2427system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036247 # mshr miss rate for ReadReq accesses 2428system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018744 # mshr miss rate for WriteReq accesses 2429system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018744 # mshr miss rate for WriteReq accesses 2430system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.790360 # mshr miss rate for SoftPFReq accesses 2431system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.790360 # mshr miss rate for SoftPFReq accesses 2432system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.738854 # mshr miss rate for WriteLineReq accesses 2433system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.738854 # mshr miss rate for WriteLineReq accesses 2434system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.057931 # mshr miss rate for LoadLockedReq accesses 2435system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.057931 # mshr miss rate for LoadLockedReq accesses 2436system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.096207 # mshr miss rate for StoreCondReq accesses 2437system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.096207 # mshr miss rate for StoreCondReq accesses 2438system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030749 # mshr miss rate for demand accesses 2439system.cpu1.dcache.demand_mshr_miss_rate::total 0.030749 # mshr miss rate for demand accesses 2440system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034901 # mshr miss rate for overall accesses 2441system.cpu1.dcache.overall_mshr_miss_rate::total 0.034901 # mshr miss rate for overall accesses 2442system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14173.785020 # average ReadReq mshr miss latency 2443system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14173.785020 # average ReadReq mshr miss latency 2444system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19391.134552 # average WriteReq mshr miss latency 2445system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19391.134552 # average WriteReq mshr miss latency 2446system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 25388.280282 # average SoftPFReq mshr miss latency 2447system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 25388.280282 # average SoftPFReq mshr miss latency 2448system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22191.770184 # average WriteLineReq mshr miss latency 2449system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 22191.770184 # average WriteLineReq mshr miss latency 2450system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13336.125397 # average LoadLockedReq mshr miss latency 2451system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13336.125397 # average LoadLockedReq mshr miss latency 2452system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.222535 # average StoreCondReq mshr miss latency 2453system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.222535 # average StoreCondReq mshr miss latency 2454system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2455system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2456system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16403.236160 # average overall mshr miss latency 2457system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16403.236160 # average overall mshr miss latency 2458system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17515.485766 # average overall mshr miss latency 2459system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17515.485766 # average overall mshr miss latency 2460system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176692.540498 # average ReadReq mshr uncacheable latency 2461system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176692.540498 # average ReadReq mshr uncacheable latency 2462system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91448.444895 # average overall mshr uncacheable latency 2463system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91448.444895 # average overall mshr uncacheable latency 2464system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 2465system.cpu1.icache.tags.replacements 6156366 # number of replacements 2466system.cpu1.icache.tags.tagsinuse 501.025645 # Cycle average of tags in use 2467system.cpu1.icache.tags.total_refs 184011394 # Total number of references to valid blocks. 2468system.cpu1.icache.tags.sampled_refs 6156878 # Sample count of references to valid blocks. 2469system.cpu1.icache.tags.avg_refs 29.887127 # Average number of references to valid blocks. 2470system.cpu1.icache.tags.warmup_cycle 8516343949500 # Cycle when the warmup percentage was hit. 2471system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.025645 # Average occupied blocks per requestor 2472system.cpu1.icache.tags.occ_percent::cpu1.inst 0.978566 # Average percentage of cache occupancy 2473system.cpu1.icache.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy 2474system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2475system.cpu1.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id 2476system.cpu1.icache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id 2477system.cpu1.icache.tags.age_task_id_blocks_1024::2 59 # Occupied blocks per task id 2478system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2479system.cpu1.icache.tags.tag_accesses 387206970 # Number of tag accesses 2480system.cpu1.icache.tags.data_accesses 387206970 # Number of data accesses 2481system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 2482system.cpu1.icache.ReadReq_hits::cpu1.inst 184011394 # number of ReadReq hits 2483system.cpu1.icache.ReadReq_hits::total 184011394 # number of ReadReq hits 2484system.cpu1.icache.demand_hits::cpu1.inst 184011394 # number of demand (read+write) hits 2485system.cpu1.icache.demand_hits::total 184011394 # number of demand (read+write) hits 2486system.cpu1.icache.overall_hits::cpu1.inst 184011394 # number of overall hits 2487system.cpu1.icache.overall_hits::total 184011394 # number of overall hits 2488system.cpu1.icache.ReadReq_misses::cpu1.inst 6513585 # number of ReadReq misses 2489system.cpu1.icache.ReadReq_misses::total 6513585 # number of ReadReq misses 2490system.cpu1.icache.demand_misses::cpu1.inst 6513585 # number of demand (read+write) misses 2491system.cpu1.icache.demand_misses::total 6513585 # number of demand (read+write) misses 2492system.cpu1.icache.overall_misses::cpu1.inst 6513585 # number of overall misses 2493system.cpu1.icache.overall_misses::total 6513585 # number of overall misses 2494system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 71534475691 # number of ReadReq miss cycles 2495system.cpu1.icache.ReadReq_miss_latency::total 71534475691 # number of ReadReq miss cycles 2496system.cpu1.icache.demand_miss_latency::cpu1.inst 71534475691 # number of demand (read+write) miss cycles 2497system.cpu1.icache.demand_miss_latency::total 71534475691 # number of demand (read+write) miss cycles 2498system.cpu1.icache.overall_miss_latency::cpu1.inst 71534475691 # number of overall miss cycles 2499system.cpu1.icache.overall_miss_latency::total 71534475691 # number of overall miss cycles 2500system.cpu1.icache.ReadReq_accesses::cpu1.inst 190524979 # number of ReadReq accesses(hits+misses) 2501system.cpu1.icache.ReadReq_accesses::total 190524979 # number of ReadReq accesses(hits+misses) 2502system.cpu1.icache.demand_accesses::cpu1.inst 190524979 # number of demand (read+write) accesses 2503system.cpu1.icache.demand_accesses::total 190524979 # number of demand (read+write) accesses 2504system.cpu1.icache.overall_accesses::cpu1.inst 190524979 # number of overall (read+write) accesses 2505system.cpu1.icache.overall_accesses::total 190524979 # number of overall (read+write) accesses 2506system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.034188 # miss rate for ReadReq accesses 2507system.cpu1.icache.ReadReq_miss_rate::total 0.034188 # miss rate for ReadReq accesses 2508system.cpu1.icache.demand_miss_rate::cpu1.inst 0.034188 # miss rate for demand accesses 2509system.cpu1.icache.demand_miss_rate::total 0.034188 # miss rate for demand accesses 2510system.cpu1.icache.overall_miss_rate::cpu1.inst 0.034188 # miss rate for overall accesses 2511system.cpu1.icache.overall_miss_rate::total 0.034188 # miss rate for overall accesses 2512system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10982.350839 # average ReadReq miss latency 2513system.cpu1.icache.ReadReq_avg_miss_latency::total 10982.350839 # average ReadReq miss latency 2514system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency 2515system.cpu1.icache.demand_avg_miss_latency::total 10982.350839 # average overall miss latency 2516system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10982.350839 # average overall miss latency 2517system.cpu1.icache.overall_avg_miss_latency::total 10982.350839 # average overall miss latency 2518system.cpu1.icache.blocked_cycles::no_mshrs 10659560 # number of cycles access was blocked 2519system.cpu1.icache.blocked_cycles::no_targets 1026 # number of cycles access was blocked 2520system.cpu1.icache.blocked::no_mshrs 770474 # number of cycles access was blocked 2521system.cpu1.icache.blocked::no_targets 4 # number of cycles access was blocked 2522system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.835068 # average number of cycles each access was blocked 2523system.cpu1.icache.avg_blocked_cycles::no_targets 256.500000 # average number of cycles each access was blocked 2524system.cpu1.icache.writebacks::writebacks 6156366 # number of writebacks 2525system.cpu1.icache.writebacks::total 6156366 # number of writebacks 2526system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 356573 # number of ReadReq MSHR hits 2527system.cpu1.icache.ReadReq_mshr_hits::total 356573 # number of ReadReq MSHR hits 2528system.cpu1.icache.demand_mshr_hits::cpu1.inst 356573 # number of demand (read+write) MSHR hits 2529system.cpu1.icache.demand_mshr_hits::total 356573 # number of demand (read+write) MSHR hits 2530system.cpu1.icache.overall_mshr_hits::cpu1.inst 356573 # number of overall MSHR hits 2531system.cpu1.icache.overall_mshr_hits::total 356573 # number of overall MSHR hits 2532system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 6157012 # number of ReadReq MSHR misses 2533system.cpu1.icache.ReadReq_mshr_misses::total 6157012 # number of ReadReq MSHR misses 2534system.cpu1.icache.demand_mshr_misses::cpu1.inst 6157012 # number of demand (read+write) MSHR misses 2535system.cpu1.icache.demand_mshr_misses::total 6157012 # number of demand (read+write) MSHR misses 2536system.cpu1.icache.overall_mshr_misses::cpu1.inst 6157012 # number of overall MSHR misses 2537system.cpu1.icache.overall_mshr_misses::total 6157012 # number of overall MSHR misses 2538system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2539system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 2540system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2541system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses 2542system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 64558641440 # number of ReadReq MSHR miss cycles 2543system.cpu1.icache.ReadReq_mshr_miss_latency::total 64558641440 # number of ReadReq MSHR miss cycles 2544system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 64558641440 # number of demand (read+write) MSHR miss cycles 2545system.cpu1.icache.demand_mshr_miss_latency::total 64558641440 # number of demand (read+write) MSHR miss cycles 2546system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 64558641440 # number of overall MSHR miss cycles 2547system.cpu1.icache.overall_mshr_miss_latency::total 64558641440 # number of overall MSHR miss cycles 2548system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7017998 # number of ReadReq MSHR uncacheable cycles 2549system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7017998 # number of ReadReq MSHR uncacheable cycles 2550system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7017998 # number of overall MSHR uncacheable cycles 2551system.cpu1.icache.overall_mshr_uncacheable_latency::total 7017998 # number of overall MSHR uncacheable cycles 2552system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for ReadReq accesses 2553system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.032316 # mshr miss rate for ReadReq accesses 2554system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for demand accesses 2555system.cpu1.icache.demand_mshr_miss_rate::total 0.032316 # mshr miss rate for demand accesses 2556system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.032316 # mshr miss rate for overall accesses 2557system.cpu1.icache.overall_mshr_miss_rate::total 0.032316 # mshr miss rate for overall accesses 2558system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average ReadReq mshr miss latency 2559system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10485.385028 # average ReadReq mshr miss latency 2560system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency 2561system.cpu1.icache.demand_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency 2562system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10485.385028 # average overall mshr miss latency 2563system.cpu1.icache.overall_avg_mshr_miss_latency::total 10485.385028 # average overall mshr miss latency 2564system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average ReadReq mshr uncacheable latency 2565system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 104746.238806 # average ReadReq mshr uncacheable latency 2566system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 104746.238806 # average overall mshr uncacheable latency 2567system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 104746.238806 # average overall mshr uncacheable latency 2568system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 2569system.cpu1.l2cache.prefetcher.num_hwpf_issued 7532579 # number of hwpf issued 2570system.cpu1.l2cache.prefetcher.pfIdentified 7540263 # number of prefetch candidates identified 2571system.cpu1.l2cache.prefetcher.pfBufferHit 6914 # number of redundant prefetches already in prefetch queue 2572system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2573system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2574system.cpu1.l2cache.prefetcher.pfSpanPage 905745 # number of prefetches not generated due to page crossing 2575system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 2576system.cpu1.l2cache.tags.replacements 2237289 # number of replacements 2577system.cpu1.l2cache.tags.tagsinuse 12906.637296 # Cycle average of tags in use 2578system.cpu1.l2cache.tags.total_refs 10683229 # Total number of references to valid blocks. 2579system.cpu1.l2cache.tags.sampled_refs 2253034 # Sample count of references to valid blocks. 2580system.cpu1.l2cache.tags.avg_refs 4.741708 # Average number of references to valid blocks. 2581system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2582system.cpu1.l2cache.tags.occ_blocks::writebacks 12598.343747 # Average occupied blocks per requestor 2583system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 34.232851 # Average occupied blocks per requestor 2584system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 25.792432 # Average occupied blocks per requestor 2585system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 248.268266 # Average occupied blocks per requestor 2586system.cpu1.l2cache.tags.occ_percent::writebacks 0.768942 # Average percentage of cache occupancy 2587system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002089 # Average percentage of cache occupancy 2588system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001574 # Average percentage of cache occupancy 2589system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.015153 # Average percentage of cache occupancy 2590system.cpu1.l2cache.tags.occ_percent::total 0.787759 # Average percentage of cache occupancy 2591system.cpu1.l2cache.tags.occ_task_id_blocks::1022 360 # Occupied blocks per task id 2592system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id 2593system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15324 # Occupied blocks per task id 2594system.cpu1.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id 2595system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 16 # Occupied blocks per task id 2596system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 163 # Occupied blocks per task id 2597system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 96 # Occupied blocks per task id 2598system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 79 # Occupied blocks per task id 2599system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 2600system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id 2601system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id 2602system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 2603system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 223 # Occupied blocks per task id 2604system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 2395 # Occupied blocks per task id 2605system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 7644 # Occupied blocks per task id 2606system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2882 # Occupied blocks per task id 2607system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2180 # Occupied blocks per task id 2608system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.021973 # Percentage of cache occupancy per task id 2609system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id 2610system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.935303 # Percentage of cache occupancy per task id 2611system.cpu1.l2cache.tags.tag_accesses 407515579 # Number of tag accesses 2612system.cpu1.l2cache.tags.data_accesses 407515579 # Number of data accesses 2613system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 2614system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 593172 # number of ReadReq hits 2615system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 194279 # number of ReadReq hits 2616system.cpu1.l2cache.ReadReq_hits::total 787451 # number of ReadReq hits 2617system.cpu1.l2cache.WritebackDirty_hits::writebacks 3518569 # number of WritebackDirty hits 2618system.cpu1.l2cache.WritebackDirty_hits::total 3518569 # number of WritebackDirty hits 2619system.cpu1.l2cache.WritebackClean_hits::writebacks 8164233 # number of WritebackClean hits 2620system.cpu1.l2cache.WritebackClean_hits::total 8164233 # number of WritebackClean hits 2621system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 105 # number of UpgradeReq hits 2622system.cpu1.l2cache.UpgradeReq_hits::total 105 # number of UpgradeReq hits 2623system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits 2624system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 2625system.cpu1.l2cache.ReadExReq_hits::cpu1.data 954506 # number of ReadExReq hits 2626system.cpu1.l2cache.ReadExReq_hits::total 954506 # number of ReadExReq hits 2627system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5573390 # number of ReadCleanReq hits 2628system.cpu1.l2cache.ReadCleanReq_hits::total 5573390 # number of ReadCleanReq hits 2629system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2940198 # number of ReadSharedReq hits 2630system.cpu1.l2cache.ReadSharedReq_hits::total 2940198 # number of ReadSharedReq hits 2631system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 209295 # number of InvalidateReq hits 2632system.cpu1.l2cache.InvalidateReq_hits::total 209295 # number of InvalidateReq hits 2633system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 593172 # number of demand (read+write) hits 2634system.cpu1.l2cache.demand_hits::cpu1.itb.walker 194279 # number of demand (read+write) hits 2635system.cpu1.l2cache.demand_hits::cpu1.inst 5573390 # number of demand (read+write) hits 2636system.cpu1.l2cache.demand_hits::cpu1.data 3894704 # number of demand (read+write) hits 2637system.cpu1.l2cache.demand_hits::total 10255545 # number of demand (read+write) hits 2638system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 593172 # number of overall hits 2639system.cpu1.l2cache.overall_hits::cpu1.itb.walker 194279 # number of overall hits 2640system.cpu1.l2cache.overall_hits::cpu1.inst 5573390 # number of overall hits 2641system.cpu1.l2cache.overall_hits::cpu1.data 3894704 # number of overall hits 2642system.cpu1.l2cache.overall_hits::total 10255545 # number of overall hits 2643system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 23430 # number of ReadReq misses 2644system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 10710 # number of ReadReq misses 2645system.cpu1.l2cache.ReadReq_misses::total 34140 # number of ReadReq misses 2646system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 228701 # number of UpgradeReq misses 2647system.cpu1.l2cache.UpgradeReq_misses::total 228701 # number of UpgradeReq misses 2648system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 195469 # number of SCUpgradeReq misses 2649system.cpu1.l2cache.SCUpgradeReq_misses::total 195469 # number of SCUpgradeReq misses 2650system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 9 # number of SCUpgradeFailReq misses 2651system.cpu1.l2cache.SCUpgradeFailReq_misses::total 9 # number of SCUpgradeFailReq misses 2652system.cpu1.l2cache.ReadExReq_misses::cpu1.data 254871 # number of ReadExReq misses 2653system.cpu1.l2cache.ReadExReq_misses::total 254871 # number of ReadExReq misses 2654system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 583583 # number of ReadCleanReq misses 2655system.cpu1.l2cache.ReadCleanReq_misses::total 583583 # number of ReadCleanReq misses 2656system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 1000824 # number of ReadSharedReq misses 2657system.cpu1.l2cache.ReadSharedReq_misses::total 1000824 # number of ReadSharedReq misses 2658system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 253175 # number of InvalidateReq misses 2659system.cpu1.l2cache.InvalidateReq_misses::total 253175 # number of InvalidateReq misses 2660system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 23430 # number of demand (read+write) misses 2661system.cpu1.l2cache.demand_misses::cpu1.itb.walker 10710 # number of demand (read+write) misses 2662system.cpu1.l2cache.demand_misses::cpu1.inst 583583 # number of demand (read+write) misses 2663system.cpu1.l2cache.demand_misses::cpu1.data 1255695 # number of demand (read+write) misses 2664system.cpu1.l2cache.demand_misses::total 1873418 # number of demand (read+write) misses 2665system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 23430 # number of overall misses 2666system.cpu1.l2cache.overall_misses::cpu1.itb.walker 10710 # number of overall misses 2667system.cpu1.l2cache.overall_misses::cpu1.inst 583583 # number of overall misses 2668system.cpu1.l2cache.overall_misses::cpu1.data 1255695 # number of overall misses 2669system.cpu1.l2cache.overall_misses::total 1873418 # number of overall misses 2670system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 794453000 # number of ReadReq miss cycles 2671system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 411582000 # number of ReadReq miss cycles 2672system.cpu1.l2cache.ReadReq_miss_latency::total 1206035000 # number of ReadReq miss cycles 2673system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 885247000 # number of UpgradeReq miss cycles 2674system.cpu1.l2cache.UpgradeReq_miss_latency::total 885247000 # number of UpgradeReq miss cycles 2675system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 309725000 # number of SCUpgradeReq miss cycles 2676system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 309725000 # number of SCUpgradeReq miss cycles 2677system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2651498 # number of SCUpgradeFailReq miss cycles 2678system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2651498 # number of SCUpgradeFailReq miss cycles 2679system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 13048454496 # number of ReadExReq miss cycles 2680system.cpu1.l2cache.ReadExReq_miss_latency::total 13048454496 # number of ReadExReq miss cycles 2681system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 21566356000 # number of ReadCleanReq miss cycles 2682system.cpu1.l2cache.ReadCleanReq_miss_latency::total 21566356000 # number of ReadCleanReq miss cycles 2683system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 38197437985 # number of ReadSharedReq miss cycles 2684system.cpu1.l2cache.ReadSharedReq_miss_latency::total 38197437985 # number of ReadSharedReq miss cycles 2685system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 1037000 # number of InvalidateReq miss cycles 2686system.cpu1.l2cache.InvalidateReq_miss_latency::total 1037000 # number of InvalidateReq miss cycles 2687system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 794453000 # number of demand (read+write) miss cycles 2688system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 411582000 # number of demand (read+write) miss cycles 2689system.cpu1.l2cache.demand_miss_latency::cpu1.inst 21566356000 # number of demand (read+write) miss cycles 2690system.cpu1.l2cache.demand_miss_latency::cpu1.data 51245892481 # number of demand (read+write) miss cycles 2691system.cpu1.l2cache.demand_miss_latency::total 74018283481 # number of demand (read+write) miss cycles 2692system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 794453000 # number of overall miss cycles 2693system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 411582000 # number of overall miss cycles 2694system.cpu1.l2cache.overall_miss_latency::cpu1.inst 21566356000 # number of overall miss cycles 2695system.cpu1.l2cache.overall_miss_latency::cpu1.data 51245892481 # number of overall miss cycles 2696system.cpu1.l2cache.overall_miss_latency::total 74018283481 # number of overall miss cycles 2697system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 616602 # number of ReadReq accesses(hits+misses) 2698system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 204989 # number of ReadReq accesses(hits+misses) 2699system.cpu1.l2cache.ReadReq_accesses::total 821591 # number of ReadReq accesses(hits+misses) 2700system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3518569 # number of WritebackDirty accesses(hits+misses) 2701system.cpu1.l2cache.WritebackDirty_accesses::total 3518569 # number of WritebackDirty accesses(hits+misses) 2702system.cpu1.l2cache.WritebackClean_accesses::writebacks 8164233 # number of WritebackClean accesses(hits+misses) 2703system.cpu1.l2cache.WritebackClean_accesses::total 8164233 # number of WritebackClean accesses(hits+misses) 2704system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 228806 # number of UpgradeReq accesses(hits+misses) 2705system.cpu1.l2cache.UpgradeReq_accesses::total 228806 # number of UpgradeReq accesses(hits+misses) 2706system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 195470 # number of SCUpgradeReq accesses(hits+misses) 2707system.cpu1.l2cache.SCUpgradeReq_accesses::total 195470 # number of SCUpgradeReq accesses(hits+misses) 2708system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 9 # number of SCUpgradeFailReq accesses(hits+misses) 2709system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 9 # number of SCUpgradeFailReq accesses(hits+misses) 2710system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1209377 # number of ReadExReq accesses(hits+misses) 2711system.cpu1.l2cache.ReadExReq_accesses::total 1209377 # number of ReadExReq accesses(hits+misses) 2712system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 6156973 # number of ReadCleanReq accesses(hits+misses) 2713system.cpu1.l2cache.ReadCleanReq_accesses::total 6156973 # number of ReadCleanReq accesses(hits+misses) 2714system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3941022 # number of ReadSharedReq accesses(hits+misses) 2715system.cpu1.l2cache.ReadSharedReq_accesses::total 3941022 # number of ReadSharedReq accesses(hits+misses) 2716system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 462470 # number of InvalidateReq accesses(hits+misses) 2717system.cpu1.l2cache.InvalidateReq_accesses::total 462470 # number of InvalidateReq accesses(hits+misses) 2718system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 616602 # number of demand (read+write) accesses 2719system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 204989 # number of demand (read+write) accesses 2720system.cpu1.l2cache.demand_accesses::cpu1.inst 6156973 # number of demand (read+write) accesses 2721system.cpu1.l2cache.demand_accesses::cpu1.data 5150399 # number of demand (read+write) accesses 2722system.cpu1.l2cache.demand_accesses::total 12128963 # number of demand (read+write) accesses 2723system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 616602 # number of overall (read+write) accesses 2724system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 204989 # number of overall (read+write) accesses 2725system.cpu1.l2cache.overall_accesses::cpu1.inst 6156973 # number of overall (read+write) accesses 2726system.cpu1.l2cache.overall_accesses::cpu1.data 5150399 # number of overall (read+write) accesses 2727system.cpu1.l2cache.overall_accesses::total 12128963 # number of overall (read+write) accesses 2728system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for ReadReq accesses 2729system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.052247 # miss rate for ReadReq accesses 2730system.cpu1.l2cache.ReadReq_miss_rate::total 0.041554 # miss rate for ReadReq accesses 2731system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999541 # miss rate for UpgradeReq accesses 2732system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999541 # miss rate for UpgradeReq accesses 2733system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses 2734system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses 2735system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2736system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2737system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.210746 # miss rate for ReadExReq accesses 2738system.cpu1.l2cache.ReadExReq_miss_rate::total 0.210746 # miss rate for ReadExReq accesses 2739system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.094784 # miss rate for ReadCleanReq accesses 2740system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.094784 # miss rate for ReadCleanReq accesses 2741system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.253950 # miss rate for ReadSharedReq accesses 2742system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.253950 # miss rate for ReadSharedReq accesses 2743system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.547441 # miss rate for InvalidateReq accesses 2744system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.547441 # miss rate for InvalidateReq accesses 2745system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for demand accesses 2746system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.052247 # miss rate for demand accesses 2747system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094784 # miss rate for demand accesses 2748system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.243805 # miss rate for demand accesses 2749system.cpu1.l2cache.demand_miss_rate::total 0.154458 # miss rate for demand accesses 2750system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.037999 # miss rate for overall accesses 2751system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.052247 # miss rate for overall accesses 2752system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094784 # miss rate for overall accesses 2753system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.243805 # miss rate for overall accesses 2754system.cpu1.l2cache.overall_miss_rate::total 0.154458 # miss rate for overall accesses 2755system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average ReadReq miss latency 2756system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 38429.691877 # average ReadReq miss latency 2757system.cpu1.l2cache.ReadReq_avg_miss_latency::total 35326.157001 # average ReadReq miss latency 2758system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 3870.761387 # average UpgradeReq miss latency 2759system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 3870.761387 # average UpgradeReq miss latency 2760system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1584.522354 # average SCUpgradeReq miss latency 2761system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1584.522354 # average SCUpgradeReq miss latency 2762system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 294610.888889 # average SCUpgradeFailReq miss latency 2763system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 294610.888889 # average SCUpgradeFailReq miss latency 2764system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 51196.309098 # average ReadExReq miss latency 2765system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 51196.309098 # average ReadExReq miss latency 2766system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36955.079226 # average ReadCleanReq miss latency 2767system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36955.079226 # average ReadCleanReq miss latency 2768system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 38165.989210 # average ReadSharedReq miss latency 2769system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 38165.989210 # average ReadSharedReq miss latency 2770system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 4.095981 # average InvalidateReq miss latency 2771system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 4.095981 # average InvalidateReq miss latency 2772system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average overall miss latency 2773system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 38429.691877 # average overall miss latency 2774system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36955.079226 # average overall miss latency 2775system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 40810.780071 # average overall miss latency 2776system.cpu1.l2cache.demand_avg_miss_latency::total 39509.753553 # average overall miss latency 2777system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 33907.511737 # average overall miss latency 2778system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 38429.691877 # average overall miss latency 2779system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36955.079226 # average overall miss latency 2780system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 40810.780071 # average overall miss latency 2781system.cpu1.l2cache.overall_avg_miss_latency::total 39509.753553 # average overall miss latency 2782system.cpu1.l2cache.blocked_cycles::no_mshrs 273 # number of cycles access was blocked 2783system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2784system.cpu1.l2cache.blocked::no_mshrs 6 # number of cycles access was blocked 2785system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2786system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 45.500000 # average number of cycles each access was blocked 2787system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2788system.cpu1.l2cache.unused_prefetches 45092 # number of HardPF blocks evicted w/o reference 2789system.cpu1.l2cache.writebacks::writebacks 1265703 # number of writebacks 2790system.cpu1.l2cache.writebacks::total 1265703 # number of writebacks 2791system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 89 # number of ReadReq MSHR hits 2792system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 277 # number of ReadReq MSHR hits 2793system.cpu1.l2cache.ReadReq_mshr_hits::total 366 # number of ReadReq MSHR hits 2794system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 14520 # number of ReadExReq MSHR hits 2795system.cpu1.l2cache.ReadExReq_mshr_hits::total 14520 # number of ReadExReq MSHR hits 2796system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 6 # number of ReadCleanReq MSHR hits 2797system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 6 # number of ReadCleanReq MSHR hits 2798system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4370 # number of ReadSharedReq MSHR hits 2799system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4370 # number of ReadSharedReq MSHR hits 2800system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 4 # number of InvalidateReq MSHR hits 2801system.cpu1.l2cache.InvalidateReq_mshr_hits::total 4 # number of InvalidateReq MSHR hits 2802system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 89 # number of demand (read+write) MSHR hits 2803system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 277 # number of demand (read+write) MSHR hits 2804system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 6 # number of demand (read+write) MSHR hits 2805system.cpu1.l2cache.demand_mshr_hits::cpu1.data 18890 # number of demand (read+write) MSHR hits 2806system.cpu1.l2cache.demand_mshr_hits::total 19262 # number of demand (read+write) MSHR hits 2807system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 89 # number of overall MSHR hits 2808system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 277 # number of overall MSHR hits 2809system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 6 # number of overall MSHR hits 2810system.cpu1.l2cache.overall_mshr_hits::cpu1.data 18890 # number of overall MSHR hits 2811system.cpu1.l2cache.overall_mshr_hits::total 19262 # number of overall MSHR hits 2812system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 23341 # number of ReadReq MSHR misses 2813system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 10433 # number of ReadReq MSHR misses 2814system.cpu1.l2cache.ReadReq_mshr_misses::total 33774 # number of ReadReq MSHR misses 2815system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of HardPFReq MSHR misses 2816system.cpu1.l2cache.HardPFReq_mshr_misses::total 793498 # number of HardPFReq MSHR misses 2817system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 228701 # number of UpgradeReq MSHR misses 2818system.cpu1.l2cache.UpgradeReq_mshr_misses::total 228701 # number of UpgradeReq MSHR misses 2819system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 195469 # number of SCUpgradeReq MSHR misses 2820system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 195469 # number of SCUpgradeReq MSHR misses 2821system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 9 # number of SCUpgradeFailReq MSHR misses 2822system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 9 # number of SCUpgradeFailReq MSHR misses 2823system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 240351 # number of ReadExReq MSHR misses 2824system.cpu1.l2cache.ReadExReq_mshr_misses::total 240351 # number of ReadExReq MSHR misses 2825system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 583577 # number of ReadCleanReq MSHR misses 2826system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 583577 # number of ReadCleanReq MSHR misses 2827system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 996454 # number of ReadSharedReq MSHR misses 2828system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 996454 # number of ReadSharedReq MSHR misses 2829system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 253171 # number of InvalidateReq MSHR misses 2830system.cpu1.l2cache.InvalidateReq_mshr_misses::total 253171 # number of InvalidateReq MSHR misses 2831system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 23341 # number of demand (read+write) MSHR misses 2832system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 10433 # number of demand (read+write) MSHR misses 2833system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 583577 # number of demand (read+write) MSHR misses 2834system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1236805 # number of demand (read+write) MSHR misses 2835system.cpu1.l2cache.demand_mshr_misses::total 1854156 # number of demand (read+write) MSHR misses 2836system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 23341 # number of overall MSHR misses 2837system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 10433 # number of overall MSHR misses 2838system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 583577 # number of overall MSHR misses 2839system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1236805 # number of overall MSHR misses 2840system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 793498 # number of overall MSHR misses 2841system.cpu1.l2cache.overall_mshr_misses::total 2647654 # number of overall MSHR misses 2842system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2843system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22964 # number of ReadReq MSHR uncacheable 2844system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 23031 # number of ReadReq MSHR uncacheable 2845system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21406 # number of WriteReq MSHR uncacheable 2846system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21406 # number of WriteReq MSHR uncacheable 2847system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2848system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 44370 # number of overall MSHR uncacheable misses 2849system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 44437 # number of overall MSHR uncacheable misses 2850system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of ReadReq MSHR miss cycles 2851system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 343913500 # number of ReadReq MSHR miss cycles 2852system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 996811500 # number of ReadReq MSHR miss cycles 2853system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of HardPFReq MSHR miss cycles 2854system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 46156066571 # number of HardPFReq MSHR miss cycles 2855system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4295864494 # number of UpgradeReq MSHR miss cycles 2856system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4295864494 # number of UpgradeReq MSHR miss cycles 2857system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3003825995 # number of SCUpgradeReq MSHR miss cycles 2858system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3003825995 # number of SCUpgradeReq MSHR miss cycles 2859system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2231498 # number of SCUpgradeFailReq MSHR miss cycles 2860system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2231498 # number of SCUpgradeFailReq MSHR miss cycles 2861system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9417872000 # number of ReadExReq MSHR miss cycles 2862system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9417872000 # number of ReadExReq MSHR miss cycles 2863system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 18064709000 # number of ReadCleanReq MSHR miss cycles 2864system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 18064709000 # number of ReadCleanReq MSHR miss cycles 2865system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 31901371985 # number of ReadSharedReq MSHR miss cycles 2866system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 31901371985 # number of ReadSharedReq MSHR miss cycles 2867system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6217720498 # number of InvalidateReq MSHR miss cycles 2868system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6217720498 # number of InvalidateReq MSHR miss cycles 2869system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of demand (read+write) MSHR miss cycles 2870system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 343913500 # number of demand (read+write) MSHR miss cycles 2871system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 18064709000 # number of demand (read+write) MSHR miss cycles 2872system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 41319243985 # number of demand (read+write) MSHR miss cycles 2873system.cpu1.l2cache.demand_mshr_miss_latency::total 60380764485 # number of demand (read+write) MSHR miss cycles 2874system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 652898000 # number of overall MSHR miss cycles 2875system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 343913500 # number of overall MSHR miss cycles 2876system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 18064709000 # number of overall MSHR miss cycles 2877system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 41319243985 # number of overall MSHR miss cycles 2878system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 46156066571 # number of overall MSHR miss cycles 2879system.cpu1.l2cache.overall_mshr_miss_latency::total 106536831056 # number of overall MSHR miss cycles 2880system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6514500 # number of ReadReq MSHR uncacheable cycles 2881system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3873635500 # number of ReadReq MSHR uncacheable cycles 2882system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3880150000 # number of ReadReq MSHR uncacheable cycles 2883system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6514500 # number of overall MSHR uncacheable cycles 2884system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3873635500 # number of overall MSHR uncacheable cycles 2885system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3880150000 # number of overall MSHR uncacheable cycles 2886system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for ReadReq accesses 2887system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for ReadReq accesses 2888system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041108 # mshr miss rate for ReadReq accesses 2889system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2890system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2891system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999541 # mshr miss rate for UpgradeReq accesses 2892system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999541 # mshr miss rate for UpgradeReq accesses 2893system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses 2894system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses 2895system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2896system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2897system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.198740 # mshr miss rate for ReadExReq accesses 2898system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.198740 # mshr miss rate for ReadExReq accesses 2899system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for ReadCleanReq accesses 2900system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094783 # mshr miss rate for ReadCleanReq accesses 2901system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.252842 # mshr miss rate for ReadSharedReq accesses 2902system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.252842 # mshr miss rate for ReadSharedReq accesses 2903system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.547432 # mshr miss rate for InvalidateReq accesses 2904system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.547432 # mshr miss rate for InvalidateReq accesses 2905system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for demand accesses 2906system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for demand accesses 2907system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for demand accesses 2908system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for demand accesses 2909system.cpu1.l2cache.demand_mshr_miss_rate::total 0.152870 # mshr miss rate for demand accesses 2910system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.037854 # mshr miss rate for overall accesses 2911system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.050895 # mshr miss rate for overall accesses 2912system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.094783 # mshr miss rate for overall accesses 2913system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.240138 # mshr miss rate for overall accesses 2914system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2915system.cpu1.l2cache.overall_mshr_miss_rate::total 0.218292 # mshr miss rate for overall accesses 2916system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average ReadReq mshr miss latency 2917system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average ReadReq mshr miss latency 2918system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 29514.167703 # average ReadReq mshr miss latency 2919system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average HardPFReq mshr miss latency 2920system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 58167.842352 # average HardPFReq mshr miss latency 2921system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18783.759118 # average UpgradeReq mshr miss latency 2922system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18783.759118 # average UpgradeReq mshr miss latency 2923system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15367.275604 # average SCUpgradeReq mshr miss latency 2924system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15367.275604 # average SCUpgradeReq mshr miss latency 2925system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 247944.222222 # average SCUpgradeFailReq mshr miss latency 2926system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 247944.222222 # average SCUpgradeFailReq mshr miss latency 2927system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 39183.826986 # average ReadExReq mshr miss latency 2928system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 39183.826986 # average ReadExReq mshr miss latency 2929system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average ReadCleanReq mshr miss latency 2930system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30955.142166 # average ReadCleanReq mshr miss latency 2931system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 32014.896809 # average ReadSharedReq mshr miss latency 2932system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 32014.896809 # average ReadSharedReq mshr miss latency 2933system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 24559.370931 # average InvalidateReq mshr miss latency 2934system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 24559.370931 # average InvalidateReq mshr miss latency 2935system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency 2936system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency 2937system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency 2938system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency 2939system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32565.094029 # average overall mshr miss latency 2940system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 27972.152007 # average overall mshr miss latency 2941system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 32964.008435 # average overall mshr miss latency 2942system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30955.142166 # average overall mshr miss latency 2943system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 33408.050570 # average overall mshr miss latency 2944system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 58167.842352 # average overall mshr miss latency 2945system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 40238.199952 # average overall mshr miss latency 2946system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average ReadReq mshr uncacheable latency 2947system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168682.960286 # average ReadReq mshr uncacheable latency 2948system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 168475.098780 # average ReadReq mshr uncacheable latency 2949system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 97231.343284 # average overall mshr uncacheable latency 2950system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87303.031327 # average overall mshr uncacheable latency 2951system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87318.000765 # average overall mshr uncacheable latency 2952system.cpu1.toL2Bus.snoop_filter.tot_requests 24247915 # Total number of requests made to the snoop filter. 2953system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12479959 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2954system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 8015 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2955system.cpu1.toL2Bus.snoop_filter.tot_snoops 603053 # Total number of snoops made to the snoop filter. 2956system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 602834 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2957system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 219 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2958system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 2959system.cpu1.toL2Bus.trans_dist::ReadReq 936644 # Transaction distribution 2960system.cpu1.toL2Bus.trans_dist::ReadResp 11117136 # Transaction distribution 2961system.cpu1.toL2Bus.trans_dist::WriteReq 21406 # Transaction distribution 2962system.cpu1.toL2Bus.trans_dist::WriteResp 21406 # Transaction distribution 2963system.cpu1.toL2Bus.trans_dist::WritebackDirty 4809330 # Transaction distribution 2964system.cpu1.toL2Bus.trans_dist::WritebackClean 8167824 # Transaction distribution 2965system.cpu1.toL2Bus.trans_dist::CleanEvict 1368728 # Transaction distribution 2966system.cpu1.toL2Bus.trans_dist::HardPFReq 1012133 # Transaction distribution 2967system.cpu1.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution 2968system.cpu1.toL2Bus.trans_dist::UpgradeReq 404751 # Transaction distribution 2969system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 355876 # Transaction distribution 2970system.cpu1.toL2Bus.trans_dist::UpgradeResp 480511 # Transaction distribution 2971system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution 2972system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution 2973system.cpu1.toL2Bus.trans_dist::ReadExReq 1238980 # Transaction distribution 2974system.cpu1.toL2Bus.trans_dist::ReadExResp 1214897 # Transaction distribution 2975system.cpu1.toL2Bus.trans_dist::ReadCleanReq 6157012 # Transaction distribution 2976system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4940216 # Transaction distribution 2977system.cpu1.toL2Bus.trans_dist::InvalidateReq 522762 # Transaction distribution 2978system.cpu1.toL2Bus.trans_dist::InvalidateResp 463422 # Transaction distribution 2979system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 18470485 # Packet count per connected master and slave (bytes) 2980system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17838362 # Packet count per connected master and slave (bytes) 2981system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 429531 # Packet count per connected master and slave (bytes) 2982system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1305673 # Packet count per connected master and slave (bytes) 2983system.cpu1.toL2Bus.pkt_count::total 38044051 # Packet count per connected master and slave (bytes) 2984system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 788054768 # Cumulative packet size per connected master and slave (bytes) 2985system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 689328153 # Cumulative packet size per connected master and slave (bytes) 2986system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1639912 # Cumulative packet size per connected master and slave (bytes) 2987system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4932816 # Cumulative packet size per connected master and slave (bytes) 2988system.cpu1.toL2Bus.pkt_size::total 1483955649 # Cumulative packet size per connected master and slave (bytes) 2989system.cpu1.toL2Bus.snoops 5334462 # Total snoops (count) 2990system.cpu1.toL2Bus.snoopTraffic 88980784 # Total snoop traffic (bytes) 2991system.cpu1.toL2Bus.snoop_fanout::samples 18249337 # Request fanout histogram 2992system.cpu1.toL2Bus.snoop_fanout::mean 0.053626 # Request fanout histogram 2993system.cpu1.toL2Bus.snoop_fanout::stdev 0.225332 # Request fanout histogram 2994system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2995system.cpu1.toL2Bus.snoop_fanout::0 17270909 94.64% 94.64% # Request fanout histogram 2996system.cpu1.toL2Bus.snoop_fanout::1 978209 5.36% 100.00% # Request fanout histogram 2997system.cpu1.toL2Bus.snoop_fanout::2 219 0.00% 100.00% # Request fanout histogram 2998system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2999system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3000system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3001system.cpu1.toL2Bus.snoop_fanout::total 18249337 # Request fanout histogram 3002system.cpu1.toL2Bus.reqLayer0.occupancy 24116423481 # Layer occupancy (ticks) 3003system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 3004system.cpu1.toL2Bus.snoopLayer0.occupancy 160883108 # Layer occupancy (ticks) 3005system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3006system.cpu1.toL2Bus.respLayer0.occupancy 9241921761 # Layer occupancy (ticks) 3007system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3008system.cpu1.toL2Bus.respLayer1.occupancy 8211674528 # Layer occupancy (ticks) 3009system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3010system.cpu1.toL2Bus.respLayer2.occupancy 224968642 # Layer occupancy (ticks) 3011system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 3012system.cpu1.toL2Bus.respLayer3.occupancy 690043535 # Layer occupancy (ticks) 3013system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 3014system.iobus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3015system.iobus.trans_dist::ReadReq 40285 # Transaction distribution 3016system.iobus.trans_dist::ReadResp 40285 # Transaction distribution 3017system.iobus.trans_dist::WriteReq 136579 # Transaction distribution 3018system.iobus.trans_dist::WriteResp 136579 # Transaction distribution 3019system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47524 # Packet count per connected master and slave (bytes) 3020system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 3021system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 3022system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 3023system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 3024system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 3025system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 3026system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 3027system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 3028system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 3029system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 3030system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29548 # Packet count per connected master and slave (bytes) 3031system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 3032system.iobus.pkt_count_system.bridge.master::total 122406 # Packet count per connected master and slave (bytes) 3033system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231242 # Packet count per connected master and slave (bytes) 3034system.iobus.pkt_count_system.realview.ide.dma::total 231242 # Packet count per connected master and slave (bytes) 3035system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 3036system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 3037system.iobus.pkt_count::total 353728 # Packet count per connected master and slave (bytes) 3038system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47544 # Cumulative packet size per connected master and slave (bytes) 3039system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 3040system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 3041system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 3042system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 3043system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 3044system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3045system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3046system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3047system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 3048system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3049system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17558 # Cumulative packet size per connected master and slave (bytes) 3050system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 3051system.iobus.pkt_size_system.bridge.master::total 155536 # Cumulative packet size per connected master and slave (bytes) 3052system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338984 # Cumulative packet size per connected master and slave (bytes) 3053system.iobus.pkt_size_system.realview.ide.dma::total 7338984 # Cumulative packet size per connected master and slave (bytes) 3054system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 3055system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 3056system.iobus.pkt_size::total 7496606 # Cumulative packet size per connected master and slave (bytes) 3057system.iobus.reqLayer0.occupancy 36861002 # Layer occupancy (ticks) 3058system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 3059system.iobus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) 3060system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 3061system.iobus.reqLayer2.occupancy 327000 # Layer occupancy (ticks) 3062system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 3063system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) 3064system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 3065system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 3066system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 3067system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) 3068system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 3069system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) 3070system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 3071system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) 3072system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 3073system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 3074system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 3075system.iobus.reqLayer16.occupancy 14000 # Layer occupancy (ticks) 3076system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 3077system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) 3078system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 3079system.iobus.reqLayer23.occupancy 24160506 # Layer occupancy (ticks) 3080system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 3081system.iobus.reqLayer24.occupancy 36392501 # Layer occupancy (ticks) 3082system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 3083system.iobus.reqLayer25.occupancy 570209840 # Layer occupancy (ticks) 3084system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3085system.iobus.respLayer0.occupancy 92558000 # Layer occupancy (ticks) 3086system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3087system.iobus.respLayer3.occupancy 147938000 # Layer occupancy (ticks) 3088system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3089system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3090system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 3091system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3092system.iocache.tags.replacements 115633 # number of replacements 3093system.iocache.tags.tagsinuse 11.369333 # Cycle average of tags in use 3094system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 3095system.iocache.tags.sampled_refs 115649 # Sample count of references to valid blocks. 3096system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 3097system.iocache.tags.warmup_cycle 9154282048000 # Cycle when the warmup percentage was hit. 3098system.iocache.tags.occ_blocks::realview.ethernet 7.419555 # Average occupied blocks per requestor 3099system.iocache.tags.occ_blocks::realview.ide 3.949778 # Average occupied blocks per requestor 3100system.iocache.tags.occ_percent::realview.ethernet 0.463722 # Average percentage of cache occupancy 3101system.iocache.tags.occ_percent::realview.ide 0.246861 # Average percentage of cache occupancy 3102system.iocache.tags.occ_percent::total 0.710583 # Average percentage of cache occupancy 3103system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3104system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3105system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3106system.iocache.tags.tag_accesses 1040946 # Number of tag accesses 3107system.iocache.tags.data_accesses 1040946 # Number of data accesses 3108system.iocache.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3109system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 3110system.iocache.ReadReq_misses::realview.ide 8893 # number of ReadReq misses 3111system.iocache.ReadReq_misses::total 8930 # number of ReadReq misses 3112system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3113system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3114system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3115system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3116system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 3117system.iocache.demand_misses::realview.ide 115621 # number of demand (read+write) misses 3118system.iocache.demand_misses::total 115661 # number of demand (read+write) misses 3119system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 3120system.iocache.overall_misses::realview.ide 115621 # number of overall misses 3121system.iocache.overall_misses::total 115661 # number of overall misses 3122system.iocache.ReadReq_miss_latency::realview.ethernet 5192500 # number of ReadReq miss cycles 3123system.iocache.ReadReq_miss_latency::realview.ide 1787370736 # number of ReadReq miss cycles 3124system.iocache.ReadReq_miss_latency::total 1792563236 # number of ReadReq miss cycles 3125system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 3126system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 3127system.iocache.WriteLineReq_miss_latency::realview.ide 12950575604 # number of WriteLineReq miss cycles 3128system.iocache.WriteLineReq_miss_latency::total 12950575604 # number of WriteLineReq miss cycles 3129system.iocache.demand_miss_latency::realview.ethernet 5561500 # number of demand (read+write) miss cycles 3130system.iocache.demand_miss_latency::realview.ide 14737946340 # number of demand (read+write) miss cycles 3131system.iocache.demand_miss_latency::total 14743507840 # number of demand (read+write) miss cycles 3132system.iocache.overall_miss_latency::realview.ethernet 5561500 # number of overall miss cycles 3133system.iocache.overall_miss_latency::realview.ide 14737946340 # number of overall miss cycles 3134system.iocache.overall_miss_latency::total 14743507840 # number of overall miss cycles 3135system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 3136system.iocache.ReadReq_accesses::realview.ide 8893 # number of ReadReq accesses(hits+misses) 3137system.iocache.ReadReq_accesses::total 8930 # number of ReadReq accesses(hits+misses) 3138system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3139system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3140system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 3141system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 3142system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 3143system.iocache.demand_accesses::realview.ide 115621 # number of demand (read+write) accesses 3144system.iocache.demand_accesses::total 115661 # number of demand (read+write) accesses 3145system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 3146system.iocache.overall_accesses::realview.ide 115621 # number of overall (read+write) accesses 3147system.iocache.overall_accesses::total 115661 # number of overall (read+write) accesses 3148system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3149system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3150system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3151system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3152system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3153system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3154system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3155system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3156system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3157system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3158system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3159system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3160system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3161system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140337.837838 # average ReadReq miss latency 3162system.iocache.ReadReq_avg_miss_latency::realview.ide 200986.251659 # average ReadReq miss latency 3163system.iocache.ReadReq_avg_miss_latency::total 200734.964838 # average ReadReq miss latency 3164system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3165system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 3166system.iocache.WriteLineReq_avg_miss_latency::realview.ide 121341.874710 # average WriteLineReq miss latency 3167system.iocache.WriteLineReq_avg_miss_latency::total 121341.874710 # average WriteLineReq miss latency 3168system.iocache.demand_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency 3169system.iocache.demand_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency 3170system.iocache.demand_avg_miss_latency::total 127471.730661 # average overall miss latency 3171system.iocache.overall_avg_miss_latency::realview.ethernet 139037.500000 # average overall miss latency 3172system.iocache.overall_avg_miss_latency::realview.ide 127467.729392 # average overall miss latency 3173system.iocache.overall_avg_miss_latency::total 127471.730661 # average overall miss latency 3174system.iocache.blocked_cycles::no_mshrs 39227 # number of cycles access was blocked 3175system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3176system.iocache.blocked::no_mshrs 3536 # number of cycles access was blocked 3177system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3178system.iocache.avg_blocked_cycles::no_mshrs 11.093609 # average number of cycles each access was blocked 3179system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3180system.iocache.writebacks::writebacks 106710 # number of writebacks 3181system.iocache.writebacks::total 106710 # number of writebacks 3182system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 3183system.iocache.ReadReq_mshr_misses::realview.ide 8893 # number of ReadReq MSHR misses 3184system.iocache.ReadReq_mshr_misses::total 8930 # number of ReadReq MSHR misses 3185system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3186system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3187system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 3188system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 3189system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 3190system.iocache.demand_mshr_misses::realview.ide 115621 # number of demand (read+write) MSHR misses 3191system.iocache.demand_mshr_misses::total 115661 # number of demand (read+write) MSHR misses 3192system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 3193system.iocache.overall_mshr_misses::realview.ide 115621 # number of overall MSHR misses 3194system.iocache.overall_mshr_misses::total 115661 # number of overall MSHR misses 3195system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3342500 # number of ReadReq MSHR miss cycles 3196system.iocache.ReadReq_mshr_miss_latency::realview.ide 1342720736 # number of ReadReq MSHR miss cycles 3197system.iocache.ReadReq_mshr_miss_latency::total 1346063236 # number of ReadReq MSHR miss cycles 3198system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 3199system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 3200system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7608008190 # number of WriteLineReq MSHR miss cycles 3201system.iocache.WriteLineReq_mshr_miss_latency::total 7608008190 # number of WriteLineReq MSHR miss cycles 3202system.iocache.demand_mshr_miss_latency::realview.ethernet 3561500 # number of demand (read+write) MSHR miss cycles 3203system.iocache.demand_mshr_miss_latency::realview.ide 8950728926 # number of demand (read+write) MSHR miss cycles 3204system.iocache.demand_mshr_miss_latency::total 8954290426 # number of demand (read+write) MSHR miss cycles 3205system.iocache.overall_mshr_miss_latency::realview.ethernet 3561500 # number of overall MSHR miss cycles 3206system.iocache.overall_mshr_miss_latency::realview.ide 8950728926 # number of overall MSHR miss cycles 3207system.iocache.overall_mshr_miss_latency::total 8954290426 # number of overall MSHR miss cycles 3208system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3209system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3210system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3211system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3212system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3213system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3214system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3215system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3216system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3217system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3218system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3219system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3220system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3221system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90337.837838 # average ReadReq mshr miss latency 3222system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150986.251659 # average ReadReq mshr miss latency 3223system.iocache.ReadReq_avg_mshr_miss_latency::total 150734.964838 # average ReadReq mshr miss latency 3224system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 3225system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 3226system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 71284.088430 # average WriteLineReq mshr miss latency 3227system.iocache.WriteLineReq_avg_mshr_miss_latency::total 71284.088430 # average WriteLineReq mshr miss latency 3228system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency 3229system.iocache.demand_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency 3230system.iocache.demand_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency 3231system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89037.500000 # average overall mshr miss latency 3232system.iocache.overall_avg_mshr_miss_latency::realview.ide 77414.387750 # average overall mshr miss latency 3233system.iocache.overall_avg_mshr_miss_latency::total 77418.407467 # average overall mshr miss latency 3234system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3235system.l2c.tags.replacements 1858608 # number of replacements 3236system.l2c.tags.tagsinuse 65222.891140 # Cycle average of tags in use 3237system.l2c.tags.total_refs 7355255 # Total number of references to valid blocks. 3238system.l2c.tags.sampled_refs 1920213 # Sample count of references to valid blocks. 3239system.l2c.tags.avg_refs 3.830437 # Average number of references to valid blocks. 3240system.l2c.tags.warmup_cycle 1229429500 # Cycle when the warmup percentage was hit. 3241system.l2c.tags.occ_blocks::writebacks 10209.698759 # Average occupied blocks per requestor 3242system.l2c.tags.occ_blocks::cpu0.dtb.walker 401.592309 # Average occupied blocks per requestor 3243system.l2c.tags.occ_blocks::cpu0.itb.walker 445.016269 # Average occupied blocks per requestor 3244system.l2c.tags.occ_blocks::cpu0.inst 3734.616961 # Average occupied blocks per requestor 3245system.l2c.tags.occ_blocks::cpu0.data 21322.764244 # Average occupied blocks per requestor 3246system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 18260.159461 # Average occupied blocks per requestor 3247system.l2c.tags.occ_blocks::cpu1.dtb.walker 76.119212 # Average occupied blocks per requestor 3248system.l2c.tags.occ_blocks::cpu1.itb.walker 86.745152 # Average occupied blocks per requestor 3249system.l2c.tags.occ_blocks::cpu1.inst 3160.425498 # Average occupied blocks per requestor 3250system.l2c.tags.occ_blocks::cpu1.data 4267.065632 # Average occupied blocks per requestor 3251system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3258.687641 # Average occupied blocks per requestor 3252system.l2c.tags.occ_percent::writebacks 0.155788 # Average percentage of cache occupancy 3253system.l2c.tags.occ_percent::cpu0.dtb.walker 0.006128 # Average percentage of cache occupancy 3254system.l2c.tags.occ_percent::cpu0.itb.walker 0.006790 # Average percentage of cache occupancy 3255system.l2c.tags.occ_percent::cpu0.inst 0.056986 # Average percentage of cache occupancy 3256system.l2c.tags.occ_percent::cpu0.data 0.325360 # Average percentage of cache occupancy 3257system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.278628 # Average percentage of cache occupancy 3258system.l2c.tags.occ_percent::cpu1.dtb.walker 0.001161 # Average percentage of cache occupancy 3259system.l2c.tags.occ_percent::cpu1.itb.walker 0.001324 # Average percentage of cache occupancy 3260system.l2c.tags.occ_percent::cpu1.inst 0.048224 # Average percentage of cache occupancy 3261system.l2c.tags.occ_percent::cpu1.data 0.065110 # Average percentage of cache occupancy 3262system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.049724 # Average percentage of cache occupancy 3263system.l2c.tags.occ_percent::total 0.995222 # Average percentage of cache occupancy 3264system.l2c.tags.occ_task_id_blocks::1022 11759 # Occupied blocks per task id 3265system.l2c.tags.occ_task_id_blocks::1023 304 # Occupied blocks per task id 3266system.l2c.tags.occ_task_id_blocks::1024 49542 # Occupied blocks per task id 3267system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id 3268system.l2c.tags.age_task_id_blocks_1022::2 196 # Occupied blocks per task id 3269system.l2c.tags.age_task_id_blocks_1022::3 891 # Occupied blocks per task id 3270system.l2c.tags.age_task_id_blocks_1022::4 10670 # Occupied blocks per task id 3271system.l2c.tags.age_task_id_blocks_1023::1 12 # Occupied blocks per task id 3272system.l2c.tags.age_task_id_blocks_1023::4 292 # Occupied blocks per task id 3273system.l2c.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 3274system.l2c.tags.age_task_id_blocks_1024::1 367 # Occupied blocks per task id 3275system.l2c.tags.age_task_id_blocks_1024::2 2478 # Occupied blocks per task id 3276system.l2c.tags.age_task_id_blocks_1024::3 2877 # Occupied blocks per task id 3277system.l2c.tags.age_task_id_blocks_1024::4 43809 # Occupied blocks per task id 3278system.l2c.tags.occ_task_id_percent::1022 0.179428 # Percentage of cache occupancy per task id 3279system.l2c.tags.occ_task_id_percent::1023 0.004639 # Percentage of cache occupancy per task id 3280system.l2c.tags.occ_task_id_percent::1024 0.755951 # Percentage of cache occupancy per task id 3281system.l2c.tags.tag_accesses 84121444 # Number of tag accesses 3282system.l2c.tags.data_accesses 84121444 # Number of data accesses 3283system.l2c.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3284system.l2c.WritebackDirty_hits::writebacks 3161961 # number of WritebackDirty hits 3285system.l2c.WritebackDirty_hits::total 3161961 # number of WritebackDirty hits 3286system.l2c.UpgradeReq_hits::cpu0.data 218473 # number of UpgradeReq hits 3287system.l2c.UpgradeReq_hits::cpu1.data 178227 # number of UpgradeReq hits 3288system.l2c.UpgradeReq_hits::total 396700 # number of UpgradeReq hits 3289system.l2c.SCUpgradeReq_hits::cpu0.data 60416 # number of SCUpgradeReq hits 3290system.l2c.SCUpgradeReq_hits::cpu1.data 50161 # number of SCUpgradeReq hits 3291system.l2c.SCUpgradeReq_hits::total 110577 # number of SCUpgradeReq hits 3292system.l2c.ReadExReq_hits::cpu0.data 54320 # number of ReadExReq hits 3293system.l2c.ReadExReq_hits::cpu1.data 59150 # number of ReadExReq hits 3294system.l2c.ReadExReq_hits::total 113470 # number of ReadExReq hits 3295system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 13417 # number of ReadSharedReq hits 3296system.l2c.ReadSharedReq_hits::cpu0.itb.walker 5017 # number of ReadSharedReq hits 3297system.l2c.ReadSharedReq_hits::cpu0.inst 539007 # number of ReadSharedReq hits 3298system.l2c.ReadSharedReq_hits::cpu0.data 668528 # number of ReadSharedReq hits 3299system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 293105 # number of ReadSharedReq hits 3300system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 15148 # number of ReadSharedReq hits 3301system.l2c.ReadSharedReq_hits::cpu1.itb.walker 6130 # number of ReadSharedReq hits 3302system.l2c.ReadSharedReq_hits::cpu1.inst 525725 # number of ReadSharedReq hits 3303system.l2c.ReadSharedReq_hits::cpu1.data 626529 # number of ReadSharedReq hits 3304system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 298432 # number of ReadSharedReq hits 3305system.l2c.ReadSharedReq_hits::total 2991038 # number of ReadSharedReq hits 3306system.l2c.InvalidateReq_hits::cpu0.data 122623 # number of InvalidateReq hits 3307system.l2c.InvalidateReq_hits::cpu1.data 121091 # number of InvalidateReq hits 3308system.l2c.InvalidateReq_hits::total 243714 # number of InvalidateReq hits 3309system.l2c.demand_hits::cpu0.dtb.walker 13417 # number of demand (read+write) hits 3310system.l2c.demand_hits::cpu0.itb.walker 5017 # number of demand (read+write) hits 3311system.l2c.demand_hits::cpu0.inst 539007 # number of demand (read+write) hits 3312system.l2c.demand_hits::cpu0.data 722848 # number of demand (read+write) hits 3313system.l2c.demand_hits::cpu0.l2cache.prefetcher 293105 # number of demand (read+write) hits 3314system.l2c.demand_hits::cpu1.dtb.walker 15148 # number of demand (read+write) hits 3315system.l2c.demand_hits::cpu1.itb.walker 6130 # number of demand (read+write) hits 3316system.l2c.demand_hits::cpu1.inst 525725 # number of demand (read+write) hits 3317system.l2c.demand_hits::cpu1.data 685679 # number of demand (read+write) hits 3318system.l2c.demand_hits::cpu1.l2cache.prefetcher 298432 # number of demand (read+write) hits 3319system.l2c.demand_hits::total 3104508 # number of demand (read+write) hits 3320system.l2c.overall_hits::cpu0.dtb.walker 13417 # number of overall hits 3321system.l2c.overall_hits::cpu0.itb.walker 5017 # number of overall hits 3322system.l2c.overall_hits::cpu0.inst 539007 # number of overall hits 3323system.l2c.overall_hits::cpu0.data 722848 # number of overall hits 3324system.l2c.overall_hits::cpu0.l2cache.prefetcher 293105 # number of overall hits 3325system.l2c.overall_hits::cpu1.dtb.walker 15148 # number of overall hits 3326system.l2c.overall_hits::cpu1.itb.walker 6130 # number of overall hits 3327system.l2c.overall_hits::cpu1.inst 525725 # number of overall hits 3328system.l2c.overall_hits::cpu1.data 685679 # number of overall hits 3329system.l2c.overall_hits::cpu1.l2cache.prefetcher 298432 # number of overall hits 3330system.l2c.overall_hits::total 3104508 # number of overall hits 3331system.l2c.UpgradeReq_misses::cpu0.data 21614 # number of UpgradeReq misses 3332system.l2c.UpgradeReq_misses::cpu1.data 22773 # number of UpgradeReq misses 3333system.l2c.UpgradeReq_misses::total 44387 # number of UpgradeReq misses 3334system.l2c.SCUpgradeReq_misses::cpu0.data 1033 # number of SCUpgradeReq misses 3335system.l2c.SCUpgradeReq_misses::cpu1.data 1052 # number of SCUpgradeReq misses 3336system.l2c.SCUpgradeReq_misses::total 2085 # number of SCUpgradeReq misses 3337system.l2c.ReadExReq_misses::cpu0.data 96389 # number of ReadExReq misses 3338system.l2c.ReadExReq_misses::cpu1.data 53149 # number of ReadExReq misses 3339system.l2c.ReadExReq_misses::total 149538 # number of ReadExReq misses 3340system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3784 # number of ReadSharedReq misses 3341system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3652 # number of ReadSharedReq misses 3342system.l2c.ReadSharedReq_misses::cpu0.inst 65121 # number of ReadSharedReq misses 3343system.l2c.ReadSharedReq_misses::cpu0.data 199292 # number of ReadSharedReq misses 3344system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 394602 # number of ReadSharedReq misses 3345system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2497 # number of ReadSharedReq misses 3346system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1730 # number of ReadSharedReq misses 3347system.l2c.ReadSharedReq_misses::cpu1.inst 57847 # number of ReadSharedReq misses 3348system.l2c.ReadSharedReq_misses::cpu1.data 128371 # number of ReadSharedReq misses 3349system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 264210 # number of ReadSharedReq misses 3350system.l2c.ReadSharedReq_misses::total 1121106 # number of ReadSharedReq misses 3351system.l2c.InvalidateReq_misses::cpu0.data 461443 # number of InvalidateReq misses 3352system.l2c.InvalidateReq_misses::cpu1.data 96191 # number of InvalidateReq misses 3353system.l2c.InvalidateReq_misses::total 557634 # number of InvalidateReq misses 3354system.l2c.demand_misses::cpu0.dtb.walker 3784 # number of demand (read+write) misses 3355system.l2c.demand_misses::cpu0.itb.walker 3652 # number of demand (read+write) misses 3356system.l2c.demand_misses::cpu0.inst 65121 # number of demand (read+write) misses 3357system.l2c.demand_misses::cpu0.data 295681 # number of demand (read+write) misses 3358system.l2c.demand_misses::cpu0.l2cache.prefetcher 394602 # number of demand (read+write) misses 3359system.l2c.demand_misses::cpu1.dtb.walker 2497 # number of demand (read+write) misses 3360system.l2c.demand_misses::cpu1.itb.walker 1730 # number of demand (read+write) misses 3361system.l2c.demand_misses::cpu1.inst 57847 # number of demand (read+write) misses 3362system.l2c.demand_misses::cpu1.data 181520 # number of demand (read+write) misses 3363system.l2c.demand_misses::cpu1.l2cache.prefetcher 264210 # number of demand (read+write) misses 3364system.l2c.demand_misses::total 1270644 # number of demand (read+write) misses 3365system.l2c.overall_misses::cpu0.dtb.walker 3784 # number of overall misses 3366system.l2c.overall_misses::cpu0.itb.walker 3652 # number of overall misses 3367system.l2c.overall_misses::cpu0.inst 65121 # number of overall misses 3368system.l2c.overall_misses::cpu0.data 295681 # number of overall misses 3369system.l2c.overall_misses::cpu0.l2cache.prefetcher 394602 # number of overall misses 3370system.l2c.overall_misses::cpu1.dtb.walker 2497 # number of overall misses 3371system.l2c.overall_misses::cpu1.itb.walker 1730 # number of overall misses 3372system.l2c.overall_misses::cpu1.inst 57847 # number of overall misses 3373system.l2c.overall_misses::cpu1.data 181520 # number of overall misses 3374system.l2c.overall_misses::cpu1.l2cache.prefetcher 264210 # number of overall misses 3375system.l2c.overall_misses::total 1270644 # number of overall misses 3376system.l2c.UpgradeReq_miss_latency::cpu0.data 151083000 # number of UpgradeReq miss cycles 3377system.l2c.UpgradeReq_miss_latency::cpu1.data 144162500 # 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number of ReadSharedReq miss cycles 3389system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of ReadSharedReq miss cycles 3390system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 266793000 # number of ReadSharedReq miss cycles 3391system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 185648500 # number of ReadSharedReq miss cycles 3392system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6445588500 # number of ReadSharedReq miss cycles 3393system.l2c.ReadSharedReq_miss_latency::cpu1.data 15192688491 # number of ReadSharedReq miss cycles 3394system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of ReadSharedReq miss cycles 3395system.l2c.ReadSharedReq_miss_latency::total 153222588727 # number of ReadSharedReq miss cycles 3396system.l2c.demand_miss_latency::cpu0.dtb.walker 381693500 # number of demand (read+write) miss cycles 3397system.l2c.demand_miss_latency::cpu0.itb.walker 359292500 # number of demand (read+write) miss cycles 3398system.l2c.demand_miss_latency::cpu0.inst 7105700999 # number of demand (read+write) miss cycles 3399system.l2c.demand_miss_latency::cpu0.data 32253020489 # number of demand (read+write) miss cycles 3400system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of demand (read+write) miss cycles 3401system.l2c.demand_miss_latency::cpu1.dtb.walker 266793000 # number of demand (read+write) miss cycles 3402system.l2c.demand_miss_latency::cpu1.itb.walker 185648500 # number of demand (read+write) miss cycles 3403system.l2c.demand_miss_latency::cpu1.inst 6445588500 # number of demand (read+write) miss cycles 3404system.l2c.demand_miss_latency::cpu1.data 20937360488 # number of demand (read+write) miss cycles 3405system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of demand (read+write) miss cycles 3406system.l2c.demand_miss_latency::total 169362708717 # number of demand (read+write) miss cycles 3407system.l2c.overall_miss_latency::cpu0.dtb.walker 381693500 # number of overall miss cycles 3408system.l2c.overall_miss_latency::cpu0.itb.walker 359292500 # number of overall miss cycles 3409system.l2c.overall_miss_latency::cpu0.inst 7105700999 # number of overall miss cycles 3410system.l2c.overall_miss_latency::cpu0.data 32253020489 # number of overall miss cycles 3411system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 60806343315 # number of overall miss cycles 3412system.l2c.overall_miss_latency::cpu1.dtb.walker 266793000 # number of overall miss cycles 3413system.l2c.overall_miss_latency::cpu1.itb.walker 185648500 # number of overall miss cycles 3414system.l2c.overall_miss_latency::cpu1.inst 6445588500 # number of overall miss cycles 3415system.l2c.overall_miss_latency::cpu1.data 20937360488 # number of overall miss cycles 3416system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 40621267426 # number of overall miss cycles 3417system.l2c.overall_miss_latency::total 169362708717 # number of overall miss cycles 3418system.l2c.WritebackDirty_accesses::writebacks 3161961 # number of WritebackDirty accesses(hits+misses) 3419system.l2c.WritebackDirty_accesses::total 3161961 # number of WritebackDirty accesses(hits+misses) 3420system.l2c.UpgradeReq_accesses::cpu0.data 240087 # number of UpgradeReq accesses(hits+misses) 3421system.l2c.UpgradeReq_accesses::cpu1.data 201000 # number of UpgradeReq accesses(hits+misses) 3422system.l2c.UpgradeReq_accesses::total 441087 # number of UpgradeReq accesses(hits+misses) 3423system.l2c.SCUpgradeReq_accesses::cpu0.data 61449 # number of SCUpgradeReq accesses(hits+misses) 3424system.l2c.SCUpgradeReq_accesses::cpu1.data 51213 # number of SCUpgradeReq accesses(hits+misses) 3425system.l2c.SCUpgradeReq_accesses::total 112662 # number of SCUpgradeReq accesses(hits+misses) 3426system.l2c.ReadExReq_accesses::cpu0.data 150709 # number of ReadExReq accesses(hits+misses) 3427system.l2c.ReadExReq_accesses::cpu1.data 112299 # number of ReadExReq accesses(hits+misses) 3428system.l2c.ReadExReq_accesses::total 263008 # number of ReadExReq accesses(hits+misses) 3429system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 17201 # number of ReadSharedReq accesses(hits+misses) 3430system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 8669 # number of ReadSharedReq accesses(hits+misses) 3431system.l2c.ReadSharedReq_accesses::cpu0.inst 604128 # number of ReadSharedReq accesses(hits+misses) 3432system.l2c.ReadSharedReq_accesses::cpu0.data 867820 # number of ReadSharedReq accesses(hits+misses) 3433system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 687707 # number of ReadSharedReq accesses(hits+misses) 3434system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 17645 # number of ReadSharedReq accesses(hits+misses) 3435system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7860 # number of ReadSharedReq accesses(hits+misses) 3436system.l2c.ReadSharedReq_accesses::cpu1.inst 583572 # number of ReadSharedReq accesses(hits+misses) 3437system.l2c.ReadSharedReq_accesses::cpu1.data 754900 # number of ReadSharedReq accesses(hits+misses) 3438system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 562642 # number of ReadSharedReq accesses(hits+misses) 3439system.l2c.ReadSharedReq_accesses::total 4112144 # number of ReadSharedReq accesses(hits+misses) 3440system.l2c.InvalidateReq_accesses::cpu0.data 584066 # number of InvalidateReq accesses(hits+misses) 3441system.l2c.InvalidateReq_accesses::cpu1.data 217282 # number of InvalidateReq accesses(hits+misses) 3442system.l2c.InvalidateReq_accesses::total 801348 # number of InvalidateReq accesses(hits+misses) 3443system.l2c.demand_accesses::cpu0.dtb.walker 17201 # number of demand (read+write) accesses 3444system.l2c.demand_accesses::cpu0.itb.walker 8669 # number of demand (read+write) accesses 3445system.l2c.demand_accesses::cpu0.inst 604128 # number of demand (read+write) accesses 3446system.l2c.demand_accesses::cpu0.data 1018529 # number of demand (read+write) accesses 3447system.l2c.demand_accesses::cpu0.l2cache.prefetcher 687707 # number of demand (read+write) accesses 3448system.l2c.demand_accesses::cpu1.dtb.walker 17645 # number of demand (read+write) accesses 3449system.l2c.demand_accesses::cpu1.itb.walker 7860 # number of demand (read+write) accesses 3450system.l2c.demand_accesses::cpu1.inst 583572 # number of demand (read+write) accesses 3451system.l2c.demand_accesses::cpu1.data 867199 # number of demand (read+write) accesses 3452system.l2c.demand_accesses::cpu1.l2cache.prefetcher 562642 # number of demand (read+write) accesses 3453system.l2c.demand_accesses::total 4375152 # number of demand (read+write) accesses 3454system.l2c.overall_accesses::cpu0.dtb.walker 17201 # number of overall (read+write) accesses 3455system.l2c.overall_accesses::cpu0.itb.walker 8669 # number of overall (read+write) accesses 3456system.l2c.overall_accesses::cpu0.inst 604128 # number of overall (read+write) accesses 3457system.l2c.overall_accesses::cpu0.data 1018529 # number of overall (read+write) accesses 3458system.l2c.overall_accesses::cpu0.l2cache.prefetcher 687707 # number of overall (read+write) accesses 3459system.l2c.overall_accesses::cpu1.dtb.walker 17645 # number of overall (read+write) accesses 3460system.l2c.overall_accesses::cpu1.itb.walker 7860 # number of overall (read+write) accesses 3461system.l2c.overall_accesses::cpu1.inst 583572 # number of overall (read+write) accesses 3462system.l2c.overall_accesses::cpu1.data 867199 # number of overall (read+write) accesses 3463system.l2c.overall_accesses::cpu1.l2cache.prefetcher 562642 # number of overall (read+write) accesses 3464system.l2c.overall_accesses::total 4375152 # number of overall (read+write) accesses 3465system.l2c.UpgradeReq_miss_rate::cpu0.data 0.090026 # miss rate for UpgradeReq accesses 3466system.l2c.UpgradeReq_miss_rate::cpu1.data 0.113299 # miss rate for UpgradeReq accesses 3467system.l2c.UpgradeReq_miss_rate::total 0.100631 # miss rate for UpgradeReq accesses 3468system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.016811 # miss rate for SCUpgradeReq accesses 3469system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.020542 # miss rate for SCUpgradeReq accesses 3470system.l2c.SCUpgradeReq_miss_rate::total 0.018507 # miss rate for SCUpgradeReq accesses 3471system.l2c.ReadExReq_miss_rate::cpu0.data 0.639570 # miss rate for ReadExReq accesses 3472system.l2c.ReadExReq_miss_rate::cpu1.data 0.473281 # miss rate for ReadExReq accesses 3473system.l2c.ReadExReq_miss_rate::total 0.568568 # miss rate for ReadExReq accesses 3474system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for ReadSharedReq accesses 3475system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.421271 # miss rate for ReadSharedReq accesses 3476system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.107793 # miss rate for ReadSharedReq accesses 3477system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.229647 # miss rate for ReadSharedReq accesses 3478system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for ReadSharedReq accesses 3479system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for ReadSharedReq accesses 3480system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.220102 # miss rate for ReadSharedReq accesses 3481system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.099126 # miss rate for ReadSharedReq accesses 3482system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.170050 # miss rate for ReadSharedReq accesses 3483system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for ReadSharedReq accesses 3484system.l2c.ReadSharedReq_miss_rate::total 0.272633 # miss rate for ReadSharedReq accesses 3485system.l2c.InvalidateReq_miss_rate::cpu0.data 0.790053 # miss rate for InvalidateReq accesses 3486system.l2c.InvalidateReq_miss_rate::cpu1.data 0.442701 # miss rate for InvalidateReq accesses 3487system.l2c.InvalidateReq_miss_rate::total 0.695870 # miss rate for InvalidateReq accesses 3488system.l2c.demand_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for demand accesses 3489system.l2c.demand_miss_rate::cpu0.itb.walker 0.421271 # miss rate for demand accesses 3490system.l2c.demand_miss_rate::cpu0.inst 0.107793 # miss rate for demand accesses 3491system.l2c.demand_miss_rate::cpu0.data 0.290302 # miss rate for demand accesses 3492system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for demand accesses 3493system.l2c.demand_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for demand accesses 3494system.l2c.demand_miss_rate::cpu1.itb.walker 0.220102 # miss rate for demand accesses 3495system.l2c.demand_miss_rate::cpu1.inst 0.099126 # miss rate for demand accesses 3496system.l2c.demand_miss_rate::cpu1.data 0.209318 # miss rate for demand accesses 3497system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for demand accesses 3498system.l2c.demand_miss_rate::total 0.290423 # miss rate for demand accesses 3499system.l2c.overall_miss_rate::cpu0.dtb.walker 0.219987 # miss rate for overall accesses 3500system.l2c.overall_miss_rate::cpu0.itb.walker 0.421271 # miss rate for overall accesses 3501system.l2c.overall_miss_rate::cpu0.inst 0.107793 # miss rate for overall accesses 3502system.l2c.overall_miss_rate::cpu0.data 0.290302 # miss rate for overall accesses 3503system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.573794 # miss rate for overall accesses 3504system.l2c.overall_miss_rate::cpu1.dtb.walker 0.141513 # miss rate for overall accesses 3505system.l2c.overall_miss_rate::cpu1.itb.walker 0.220102 # miss rate for overall accesses 3506system.l2c.overall_miss_rate::cpu1.inst 0.099126 # miss rate for overall accesses 3507system.l2c.overall_miss_rate::cpu1.data 0.209318 # miss rate for overall accesses 3508system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.469588 # miss rate for overall accesses 3509system.l2c.overall_miss_rate::total 0.290423 # miss rate for overall accesses 3510system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6990.052744 # average UpgradeReq miss latency 3511system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6330.413209 # average UpgradeReq miss latency 3512system.l2c.UpgradeReq_avg_miss_latency::total 6651.620970 # average UpgradeReq miss latency 3513system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 8741.045499 # average SCUpgradeReq miss latency 3514system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 10123.574144 # average SCUpgradeReq miss latency 3515system.l2c.SCUpgradeReq_avg_miss_latency::total 9438.609113 # average SCUpgradeReq miss latency 3516system.l2c.ReadExReq_avg_miss_latency::cpu0.data 107848.903848 # average ReadExReq miss latency 3517system.l2c.ReadExReq_avg_miss_latency::cpu1.data 108086.172778 # average ReadExReq miss latency 3518system.l2c.ReadExReq_avg_miss_latency::total 107933.234295 # average ReadExReq miss latency 3519system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average ReadSharedReq miss latency 3520system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 98382.393209 # average ReadSharedReq miss latency 3521system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109115.354479 # average ReadSharedReq miss latency 3522system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 109676.115930 # average ReadSharedReq miss latency 3523system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average ReadSharedReq miss latency 3524system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average ReadSharedReq miss latency 3525system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 107311.271676 # average ReadSharedReq miss latency 3526system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 111424.767058 # average ReadSharedReq miss latency 3527system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 118349.849195 # average ReadSharedReq miss latency 3528system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average ReadSharedReq miss latency 3529system.l2c.ReadSharedReq_avg_miss_latency::total 136670.920258 # average ReadSharedReq miss latency 3530system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average overall miss latency 3531system.l2c.demand_avg_miss_latency::cpu0.itb.walker 98382.393209 # average overall miss latency 3532system.l2c.demand_avg_miss_latency::cpu0.inst 109115.354479 # average overall miss latency 3533system.l2c.demand_avg_miss_latency::cpu0.data 109080.463368 # average overall miss latency 3534system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average overall miss latency 3535system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average overall miss latency 3536system.l2c.demand_avg_miss_latency::cpu1.itb.walker 107311.271676 # average overall miss latency 3537system.l2c.demand_avg_miss_latency::cpu1.inst 111424.767058 # average overall miss latency 3538system.l2c.demand_avg_miss_latency::cpu1.data 115344.647907 # average overall miss latency 3539system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average overall miss latency 3540system.l2c.demand_avg_miss_latency::total 133288.874553 # average overall miss latency 3541system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100870.375264 # average overall miss latency 3542system.l2c.overall_avg_miss_latency::cpu0.itb.walker 98382.393209 # average overall miss latency 3543system.l2c.overall_avg_miss_latency::cpu0.inst 109115.354479 # average overall miss latency 3544system.l2c.overall_avg_miss_latency::cpu0.data 109080.463368 # average overall miss latency 3545system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 154095.375378 # average overall miss latency 3546system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 106845.414497 # average overall miss latency 3547system.l2c.overall_avg_miss_latency::cpu1.itb.walker 107311.271676 # average overall miss latency 3548system.l2c.overall_avg_miss_latency::cpu1.inst 111424.767058 # average overall miss latency 3549system.l2c.overall_avg_miss_latency::cpu1.data 115344.647907 # average overall miss latency 3550system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 153746.139154 # average overall miss latency 3551system.l2c.overall_avg_miss_latency::total 133288.874553 # average overall miss latency 3552system.l2c.blocked_cycles::no_mshrs 15677 # number of cycles access was blocked 3553system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3554system.l2c.blocked::no_mshrs 153 # number of cycles access was blocked 3555system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3556system.l2c.avg_blocked_cycles::no_mshrs 102.464052 # average number of cycles each access was blocked 3557system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3558system.l2c.writebacks::writebacks 1420191 # number of writebacks 3559system.l2c.writebacks::total 1420191 # number of writebacks 3560system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 100 # number of ReadSharedReq MSHR hits 3561system.l2c.ReadSharedReq_mshr_hits::cpu0.data 8 # number of ReadSharedReq MSHR hits 3562system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits 3563system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 184 # number of ReadSharedReq MSHR hits 3564system.l2c.ReadSharedReq_mshr_hits::cpu1.data 35 # number of ReadSharedReq MSHR hits 3565system.l2c.ReadSharedReq_mshr_hits::total 328 # number of ReadSharedReq MSHR hits 3566system.l2c.demand_mshr_hits::cpu0.inst 100 # number of demand (read+write) MSHR hits 3567system.l2c.demand_mshr_hits::cpu0.data 8 # number of demand (read+write) MSHR hits 3568system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 3569system.l2c.demand_mshr_hits::cpu1.inst 184 # number of demand (read+write) MSHR hits 3570system.l2c.demand_mshr_hits::cpu1.data 35 # number of demand (read+write) MSHR hits 3571system.l2c.demand_mshr_hits::total 328 # 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number of SCUpgradeReq MSHR misses 3584system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1052 # number of SCUpgradeReq MSHR misses 3585system.l2c.SCUpgradeReq_mshr_misses::total 2085 # number of SCUpgradeReq MSHR misses 3586system.l2c.ReadExReq_mshr_misses::cpu0.data 96389 # number of ReadExReq MSHR misses 3587system.l2c.ReadExReq_mshr_misses::cpu1.data 53149 # number of ReadExReq MSHR misses 3588system.l2c.ReadExReq_mshr_misses::total 149538 # number of ReadExReq MSHR misses 3589system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3784 # number of ReadSharedReq MSHR misses 3590system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3652 # number of ReadSharedReq MSHR misses 3591system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 65021 # number of ReadSharedReq MSHR misses 3592system.l2c.ReadSharedReq_mshr_misses::cpu0.data 199284 # number of ReadSharedReq MSHR misses 3593system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 394601 # number of ReadSharedReq MSHR misses 3594system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2497 # 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number of demand (read+write) MSHR miss cycles 3667system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 168348500 # number of demand (read+write) MSHR miss cycles 3668system.l2c.demand_mshr_miss_latency::cpu1.inst 5850563554 # number of demand (read+write) MSHR miss cycles 3669system.l2c.demand_mshr_miss_latency::cpu1.data 19117648706 # number of demand (read+write) MSHR miss cycles 3670system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 37978912479 # number of demand (read+write) MSHR miss cycles 3671system.l2c.demand_mshr_miss_latency::total 156624696867 # number of demand (read+write) MSHR miss cycles 3672system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 343853001 # number of overall MSHR miss cycles 3673system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 322772001 # number of overall MSHR miss cycles 3674system.l2c.overall_mshr_miss_latency::cpu0.inst 6445445567 # number of overall MSHR miss cycles 3675system.l2c.overall_mshr_miss_latency::cpu0.data 29295388118 # number of overall MSHR miss cycles 3676system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 56859943438 # number of overall MSHR miss cycles 3677system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 241821503 # number of overall MSHR miss cycles 3678system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 168348500 # number of overall MSHR miss cycles 3679system.l2c.overall_mshr_miss_latency::cpu1.inst 5850563554 # number of overall MSHR miss cycles 3680system.l2c.overall_mshr_miss_latency::cpu1.data 19117648706 # number of overall MSHR miss cycles 3681system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 37978912479 # number of overall MSHR miss cycles 3682system.l2c.overall_mshr_miss_latency::total 156624696867 # number of overall MSHR miss cycles 3683system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 147855500 # number of ReadReq MSHR uncacheable cycles 3684system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2484594002 # number of ReadReq MSHR uncacheable cycles 3685system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5308000 # number of ReadReq MSHR uncacheable cycles 3686system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3460097504 # number of ReadReq MSHR uncacheable cycles 3687system.l2c.ReadReq_mshr_uncacheable_latency::total 6097855006 # number of ReadReq MSHR uncacheable cycles 3688system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 147855500 # number of overall MSHR uncacheable cycles 3689system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2484594002 # number of overall MSHR uncacheable cycles 3690system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5308000 # number of overall MSHR uncacheable cycles 3691system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3460097504 # number of overall MSHR uncacheable cycles 3692system.l2c.overall_mshr_uncacheable_latency::total 6097855006 # number of overall MSHR uncacheable cycles 3693system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3694system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3695system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.090026 # mshr miss rate for UpgradeReq accesses 3696system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.113299 # mshr miss rate for UpgradeReq accesses 3697system.l2c.UpgradeReq_mshr_miss_rate::total 0.100631 # mshr miss rate for UpgradeReq accesses 3698system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.016811 # mshr miss rate for SCUpgradeReq accesses 3699system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.020542 # mshr miss rate for SCUpgradeReq accesses 3700system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.018507 # mshr miss rate for SCUpgradeReq accesses 3701system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.639570 # mshr miss rate for ReadExReq accesses 3702system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.473281 # mshr miss rate for ReadExReq accesses 3703system.l2c.ReadExReq_mshr_miss_rate::total 0.568568 # mshr miss rate for ReadExReq accesses 3704system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for ReadSharedReq accesses 3705system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for ReadSharedReq accesses 3706system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for ReadSharedReq accesses 3707system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.229637 # mshr miss rate for ReadSharedReq accesses 3708system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for ReadSharedReq accesses 3709system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for ReadSharedReq accesses 3710system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for ReadSharedReq accesses 3711system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for ReadSharedReq accesses 3712system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.170004 # mshr miss rate for ReadSharedReq accesses 3713system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for ReadSharedReq accesses 3714system.l2c.ReadSharedReq_mshr_miss_rate::total 0.272553 # mshr miss rate for ReadSharedReq accesses 3715system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790053 # mshr miss rate for InvalidateReq accesses 3716system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.442701 # mshr miss rate for InvalidateReq accesses 3717system.l2c.InvalidateReq_mshr_miss_rate::total 0.695870 # mshr miss rate for InvalidateReq accesses 3718system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for demand accesses 3719system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for demand accesses 3720system.l2c.demand_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for demand accesses 3721system.l2c.demand_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for demand accesses 3722system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for demand accesses 3723system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for demand accesses 3724system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for demand accesses 3725system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for demand accesses 3726system.l2c.demand_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for demand accesses 3727system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for demand accesses 3728system.l2c.demand_mshr_miss_rate::total 0.290348 # mshr miss rate for demand accesses 3729system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.219987 # mshr miss rate for overall accesses 3730system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.421271 # mshr miss rate for overall accesses 3731system.l2c.overall_mshr_miss_rate::cpu0.inst 0.107628 # mshr miss rate for overall accesses 3732system.l2c.overall_mshr_miss_rate::cpu0.data 0.290294 # mshr miss rate for overall accesses 3733system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.573792 # mshr miss rate for overall accesses 3734system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141513 # mshr miss rate for overall accesses 3735system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.220102 # mshr miss rate for overall accesses 3736system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098810 # mshr miss rate for overall accesses 3737system.l2c.overall_mshr_miss_rate::cpu1.data 0.209277 # mshr miss rate for overall accesses 3738system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.469588 # mshr miss rate for overall accesses 3739system.l2c.overall_mshr_miss_rate::total 0.290348 # mshr miss rate for overall accesses 3740system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20261.288979 # average UpgradeReq mshr miss latency 3741system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20791.617178 # average UpgradeReq mshr miss latency 3742system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20533.376845 # average UpgradeReq mshr miss latency 3743system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24157.792836 # average SCUpgradeReq mshr miss latency 3744system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24591.730038 # average SCUpgradeReq mshr miss latency 3745system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24376.738609 # average SCUpgradeReq mshr miss latency 3746system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 97847.242341 # average ReadExReq mshr miss latency 3747system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 98082.342415 # average ReadExReq mshr miss latency 3748system.l2c.ReadExReq_avg_mshr_miss_latency::total 97930.801930 # average ReadExReq mshr miss latency 3749system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average ReadSharedReq mshr miss latency 3750system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average ReadSharedReq mshr miss latency 3751system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average ReadSharedReq mshr miss latency 3752system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 99676.794304 # average ReadSharedReq mshr miss latency 3753system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average ReadSharedReq mshr miss latency 3754system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average ReadSharedReq mshr miss latency 3755system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average ReadSharedReq mshr miss latency 3756system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average ReadSharedReq mshr miss latency 3757system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108345.828832 # average ReadSharedReq mshr miss latency 3758system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average ReadSharedReq mshr miss latency 3759system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126680.145941 # average ReadSharedReq mshr miss latency 3760system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24678.176440 # average InvalidateReq mshr miss latency 3761system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19608.216995 # average InvalidateReq mshr miss latency 3762system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23803.616300 # average InvalidateReq mshr miss latency 3763system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency 3764system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency 3765system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency 3766system.l2c.demand_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency 3767system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency 3768system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency 3769system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency 3770system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency 3771system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency 3772system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency 3773system.l2c.demand_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency 3774system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90870.243393 # average overall mshr miss latency 3775system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 88382.256572 # average overall mshr miss latency 3776system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99128.674844 # average overall mshr miss latency 3777system.l2c.overall_avg_mshr_miss_latency::cpu0.data 99080.362827 # average overall mshr miss latency 3778system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 144094.777859 # average overall mshr miss latency 3779system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 96844.814978 # average overall mshr miss latency 3780system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 97311.271676 # average overall mshr miss latency 3781system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 101461.310615 # average overall mshr miss latency 3782system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105340.103623 # average overall mshr miss latency 3783system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143745.174214 # average overall mshr miss latency 3784system.l2c.overall_avg_mshr_miss_latency::total 123295.854628 # average overall mshr miss latency 3785system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average ReadReq mshr uncacheable latency 3786system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 156825.980054 # average ReadReq mshr uncacheable latency 3787system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average ReadReq mshr uncacheable latency 3788system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150687.984670 # average ReadReq mshr uncacheable latency 3789system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 148855.242426 # average ReadReq mshr uncacheable latency 3790system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 70642.857143 # average overall mshr uncacheable latency 3791system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75004.347099 # average overall mshr uncacheable latency 3792system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 79223.880597 # average overall mshr uncacheable latency 3793system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 77986.330328 # average overall mshr uncacheable latency 3794system.l2c.overall_avg_mshr_uncacheable_latency::total 76554.284857 # average overall mshr uncacheable latency 3795system.membus.snoop_filter.tot_requests 4427188 # Total number of requests made to the snoop filter. 3796system.membus.snoop_filter.hit_single_requests 2544778 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3797system.membus.snoop_filter.hit_multi_requests 3484 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3798system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3799system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3800system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3801system.membus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3802system.membus.trans_dist::ReadReq 40965 # Transaction distribution 3803system.membus.trans_dist::ReadResp 1170673 # Transaction distribution 3804system.membus.trans_dist::WriteReq 38689 # Transaction distribution 3805system.membus.trans_dist::WriteResp 38689 # Transaction distribution 3806system.membus.trans_dist::WritebackDirty 1526901 # Transaction distribution 3807system.membus.trans_dist::CleanEvict 301973 # Transaction distribution 3808system.membus.trans_dist::UpgradeReq 291943 # Transaction distribution 3809system.membus.trans_dist::SCUpgradeReq 287508 # Transaction distribution 3810system.membus.trans_dist::UpgradeResp 8 # Transaction distribution 3811system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution 3812system.membus.trans_dist::ReadExReq 162891 # Transaction distribution 3813system.membus.trans_dist::ReadExResp 148894 # Transaction distribution 3814system.membus.trans_dist::ReadSharedReq 1129708 # Transaction distribution 3815system.membus.trans_dist::InvalidateReq 674487 # Transaction distribution 3816system.membus.trans_dist::InvalidateResp 26345 # Transaction distribution 3817system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122406 # Packet count per connected master and slave (bytes) 3818system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) 3819system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 27362 # Packet count per connected master and slave (bytes) 3820system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5422541 # Packet count per connected master and slave (bytes) 3821system.membus.pkt_count_system.l2c.mem_side::total 5572385 # Packet count per connected master and slave (bytes) 3822system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238081 # Packet count per connected master and slave (bytes) 3823system.membus.pkt_count_system.iocache.mem_side::total 238081 # Packet count per connected master and slave (bytes) 3824system.membus.pkt_count::total 5810466 # Packet count per connected master and slave (bytes) 3825system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155536 # Cumulative packet size per connected master and slave (bytes) 3826system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) 3827system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 54724 # Cumulative packet size per connected master and slave (bytes) 3828system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 172160384 # Cumulative packet size per connected master and slave (bytes) 3829system.membus.pkt_size_system.l2c.mem_side::total 172371200 # Cumulative packet size per connected master and slave (bytes) 3830system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7263808 # Cumulative packet size per connected master and slave (bytes) 3831system.membus.pkt_size_system.iocache.mem_side::total 7263808 # Cumulative packet size per connected master and slave (bytes) 3832system.membus.pkt_size::total 179635008 # Cumulative packet size per connected master and slave (bytes) 3833system.membus.snoops 585668 # Total snoops (count) 3834system.membus.snoopTraffic 182912 # Total snoop traffic (bytes) 3835system.membus.snoop_fanout::samples 2626196 # Request fanout histogram 3836system.membus.snoop_fanout::mean 0.011361 # Request fanout histogram 3837system.membus.snoop_fanout::stdev 0.105982 # Request fanout histogram 3838system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3839system.membus.snoop_fanout::0 2596359 98.86% 98.86% # Request fanout histogram 3840system.membus.snoop_fanout::1 29837 1.14% 100.00% # Request fanout histogram 3841system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3842system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3843system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3844system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3845system.membus.snoop_fanout::total 2626196 # Request fanout histogram 3846system.membus.reqLayer0.occupancy 97843991 # Layer occupancy (ticks) 3847system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3848system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) 3849system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3850system.membus.reqLayer2.occupancy 22899493 # Layer occupancy (ticks) 3851system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3852system.membus.reqLayer5.occupancy 10387724889 # Layer occupancy (ticks) 3853system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3854system.membus.respLayer2.occupancy 6773203746 # Layer occupancy (ticks) 3855system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3856system.membus.respLayer3.occupancy 76561844 # Layer occupancy (ticks) 3857system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3858system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3859system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3860system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3861system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3862system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3863system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3864system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3865system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3866system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3867system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3868system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3869system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3870system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3871system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3872system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3873system.realview.ethernet.txBytes 966 # Bytes Transmitted 3874system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3875system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3876system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3877system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3878system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3879system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3880system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3881system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3882system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3883system.realview.ethernet.totPackets 3 # Total Packets 3884system.realview.ethernet.totBytes 966 # Total Bytes 3885system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3886system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3887system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3888system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3889system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3890system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3891system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3892system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3893system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3894system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3895system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3896system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3897system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3898system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3899system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3900system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3901system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3902system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3903system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3904system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3905system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3906system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3907system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3908system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3909system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3910system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3911system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3912system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3913system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3914system.realview.ethernet.droppedPackets 0 # number of packets dropped 3915system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3916system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3917system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3918system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3919system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3920system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3921system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3922system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3923system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3924system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3925system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3926system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3927system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3928system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3929system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3930system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3931system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3932system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3933system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3934system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3935system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3936system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3937system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3938system.toL2Bus.snoop_filter.tot_requests 12840687 # Total number of requests made to the snoop filter. 3939system.toL2Bus.snoop_filter.hit_single_requests 6804210 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3940system.toL2Bus.snoop_filter.hit_multi_requests 2233432 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3941system.toL2Bus.snoop_filter.tot_snoops 286650 # Total number of snoops made to the snoop filter. 3942system.toL2Bus.snoop_filter.hit_single_snoops 259465 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3943system.toL2Bus.snoop_filter.hit_multi_snoops 27185 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3944system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47341923254000 # Cumulative time (in ticks) in various power states 3945system.toL2Bus.trans_dist::ReadReq 40967 # Transaction distribution 3946system.toL2Bus.trans_dist::ReadResp 4895074 # Transaction distribution 3947system.toL2Bus.trans_dist::WriteReq 38689 # Transaction distribution 3948system.toL2Bus.trans_dist::WriteResp 38689 # Transaction distribution 3949system.toL2Bus.trans_dist::WritebackDirty 4582152 # Transaction distribution 3950system.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 3951system.toL2Bus.trans_dist::CleanEvict 2976886 # Transaction distribution 3952system.toL2Bus.trans_dist::UpgradeReq 687999 # Transaction distribution 3953system.toL2Bus.trans_dist::SCUpgradeReq 398085 # Transaction distribution 3954system.toL2Bus.trans_dist::UpgradeResp 1086084 # Transaction distribution 3955system.toL2Bus.trans_dist::SCUpgradeFailReq 122 # Transaction distribution 3956system.toL2Bus.trans_dist::UpgradeFailResp 122 # Transaction distribution 3957system.toL2Bus.trans_dist::ReadExReq 311857 # Transaction distribution 3958system.toL2Bus.trans_dist::ReadExResp 311857 # Transaction distribution 3959system.toL2Bus.trans_dist::ReadSharedReq 4854758 # Transaction distribution 3960system.toL2Bus.trans_dist::InvalidateReq 900244 # Transaction distribution 3961system.toL2Bus.trans_dist::InvalidateResp 885499 # Transaction distribution 3962system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10402586 # Packet count per connected master and slave (bytes) 3963system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8325072 # Packet count per connected master and slave (bytes) 3964system.toL2Bus.pkt_count::total 18727658 # Packet count per connected master and slave (bytes) 3965system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 271068295 # Cumulative packet size per connected master and slave (bytes) 3966system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 211681017 # Cumulative packet size per connected master and slave (bytes) 3967system.toL2Bus.pkt_size::total 482749312 # Cumulative packet size per connected master and slave (bytes) 3968system.toL2Bus.snoops 3295138 # Total snoops (count) 3969system.toL2Bus.snoopTraffic 141512016 # Total snoop traffic (bytes) 3970system.toL2Bus.snoop_fanout::samples 9092383 # Request fanout histogram 3971system.toL2Bus.snoop_fanout::mean 0.348495 # Request fanout histogram 3972system.toL2Bus.snoop_fanout::stdev 0.482728 # Request fanout histogram 3973system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3974system.toL2Bus.snoop_fanout::0 5950920 65.45% 65.45% # Request fanout histogram 3975system.toL2Bus.snoop_fanout::1 3114278 34.25% 99.70% # Request fanout histogram 3976system.toL2Bus.snoop_fanout::2 27185 0.30% 100.00% # Request fanout histogram 3977system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3978system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3979system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3980system.toL2Bus.snoop_fanout::total 9092383 # Request fanout histogram 3981system.toL2Bus.reqLayer0.occupancy 10118543300 # Layer occupancy (ticks) 3982system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3983system.toL2Bus.snoopLayer0.occupancy 8937131 # Layer occupancy (ticks) 3984system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3985system.toL2Bus.respLayer0.occupancy 4714839859 # Layer occupancy (ticks) 3986system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3987system.toL2Bus.respLayer1.occupancy 4090244927 # Layer occupancy (ticks) 3988system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3989system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3990system.cpu0.kern.inst.quiesce 5530 # number of quiesce instructions executed 3991system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3992system.cpu1.kern.inst.quiesce 13684 # number of quiesce instructions executed 3993 3994---------- End Simulation Statistics ---------- 3995