Searched hist:2007 (Results 326 - 350 of 895) sorted by relevance

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/gem5/src/arch/x86/insts/
H A Dmicroop.cc5138:069bbeae1ef8 Sun Oct 07 21:16:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Significantly filled out misc regs.
5083:49559a8060e8 Wed Sep 19 21:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move the fp microops to their own file with their own base classes in C++ and python.
H A Dmicroldstop.hh5002:1b540e93ad34 Sun Aug 26 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Remove x86 code that attempted to fix misaligned accesses.
4867:2de05bc73640 Sat Aug 04 23:22:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make 64 bit unaligned accesses work as well as the other sizes.
There is a fundemental flaw in how unaligned accesses are supported, but this
is still an improvement.
4804:4a707cb7065b Mon Jul 30 16:23:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make disassembly use the final register index. Add bits to indicate whether or not register indexes should be "folded".
4767:5e55d650692e Fri Jul 27 01:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add functions to read and write to an exec context.
These functions take care of calling the thread contexts read and write functions with the right sized data type, and handle unaligned accesses.
4679:0b39fa8f5eb8 Sat Jul 14 20:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Pull some hard coded base classes out of the isa description.
/gem5/src/dev/sparc/
H A Diob.cc5103:391933804192 Mon Oct 01 02:55:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: fix sparc_fs booting with SimpleTimingCPU.
4918:3214e3694fb2 Fri Jul 27 02:15:00 EDT 2007 Nathan Binkert <nate@binkert.org> Merge python and x86 changes with cache branch
4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are
now encoded in cmd field.
4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
4216:c01745179a1f Tue Mar 13 00:05:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> fix interrupting during a quisce on sparc

src/arch/sparc/ua2005.cc:
fix interrupting when quisced. Since sticks correspond to instructions when not quisced we need to
check if were suspended and interrupt at the guess time
src/base/traceflags.py:
add trace flag for Iob
src/cpu/simple/base.cc:
Use Quisce instead of IPI trace flag
src/dev/sparc/iob.cc:
add some Dprintfs
4194:af4f6022394b Fri Mar 09 16:56:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> implement ipi stufff for SPARC

src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/arch/x86/utility.hh:
add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi
src/arch/sparc/isa/decoder.isa:
handle writable bits of strandstatus register in miscregfile
src/arch/sparc/miscregfile.hh:
some constants for the strand status register
src/arch/sparc/ua2005.cc:
properly implement the strand status register
src/dev/sparc/iob.cc:
implement ipi generation properly
src/sim/system.cc:
call into the ISA to start the CPU (or not)
4130:a611c874376e Sat Mar 03 22:45:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add a sparc fs regression

src/dev/sparc/iob.cc:
don't warn on cpu restart/idle/halt stuff
tests/SConscript:
add sparc target in test Sconscript
util/regress:
Add SPARC_FS target in regress
4104:10b99ef0a7ff Sat Mar 03 19:02:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Add Iob and remove the fake device

configs/common/FSConfig.py:
add an attachOnChipIO to force people to think about where "onchip" i/o should be connected in their hierarchy
H A DSConscript5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
4103:785279436bdd Sat Mar 03 17:22:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Implement Niagara I/O interface and rework interrupts

configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore
3914:e83101d984d5 Sun Jan 21 18:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add dumb time of day device
3898:42a529d97cf2 Tue Jan 09 22:16:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add memory mapped disk device

configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
add configuration for memory mapped disk
src/dev/sparc/SConscript:
add memory mapped disk to sconscript
H A Ddtod.cc4918:3214e3694fb2 Fri Jul 27 02:15:00 EDT 2007 Nathan Binkert <nate@binkert.org> Merge python and x86 changes with cache branch
4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are
now encoded in cmd field.
4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
3990:6a5fd06c76a0 Mon Jan 29 19:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> timegm() is a gnuism... replace with the code from the timegm() man page
3943:68e673d2db04 Sun Jan 28 13:26:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Stick the conversion of python to unix time with all of
the other param code so that other functions can use it
as well.
3914:e83101d984d5 Sun Jan 21 18:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add dumb time of day device
H A Dmm_disk.hh4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
4011:e6899d7ca5b1 Tue Feb 06 15:52:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> more fp fixes
fix unaligned accesses in mmaped disk device

src/arch/sparc/isa/decoder.isa:
get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
move the cexec into the aexec field
src/cpu/exetrace.cc:
copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
fix unaligned accesses in the memory mapped disk device
3898:42a529d97cf2 Tue Jan 09 22:16:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add memory mapped disk device

configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
add configuration for memory mapped disk
src/dev/sparc/SConscript:
add memory mapped disk to sconscript
/gem5/src/arch/x86/isa/
H A Doperands.isa5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs.
5291:5d38610cff05 Sun Dec 02 02:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the lgdt instruction.
5290:7dc3e8ee0a22 Sun Dec 02 02:00:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement wrbase and wrlimit for loading pseudo descriptors.
5289:ca5390e654b8 Sun Dec 02 02:00:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Separate the effective seg base and the "hidden" seg base.
5246:21f29e99e021 Tue Nov 13 04:31:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make microcode use presegmentation RIPs and the rest of m5 use post segmentation RIPS.
5241:a6602acdd046 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the wrcr microop which writes a control register, and some control register work.
5083:49559a8060e8 Wed Sep 19 21:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move the fp microops to their own file with their own base classes in C++ and python.
5082:82dd253231c8 Wed Sep 19 21:26:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in the foundation for x87 stack based fp registers.
5075:4ae876c5037d Thu Sep 13 19:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Total overhaul of the division instructions and microops.
5063:8eb72b1bd3c6 Thu Sep 06 19:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Rework the multiplication microops so that they work like they would in the patent.
/gem5/src/base/
H A Dbitfield.hh4680:09867d787df8 Sat Jul 14 20:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Move bitunion code into it's own file.
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
4649:899f745b3c21 Tue May 08 13:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix insertBits so it doesn't shift things into oblivion
4425:e94d396daad9 Wed May 09 00:01:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> bit_val was being used directly in the statement in return. If type B had fewer bits than last, bit_val << last would get the wrong answer.

src/base/bitfield.hh:
bit_val was being used directly in the statement in
return. If type B had fewer bits than last, bit_val << last would get
the wrong answer.
4275:8a37341c7507 Wed Mar 21 15:15:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Missed a const
4274:638f735c9bc7 Tue Mar 20 07:40:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fixed up some types and const placement, and added signed bitfields that sign extend themselves.
4262:e851cdcf279b Mon Mar 19 13:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Ditched read or write only subbitfields for now since they were proving difficult to implement. Allow component Bitfields to be instantiated without templates, clean up the implementation a little, and adjust the comments to match.
4261:0a667162b5fa Mon Mar 19 10:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> For the _BitfieldRO and _BitfieldWO classes, make sure the undesired operator is redefined as private.
4260:cb8a68017b41 Mon Mar 19 10:22:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Formatting fixes.
4259:ca1ca13665ba Mon Mar 19 10:20:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Lots and lots of comments.
H A Dtrace.cc4212:0d50e6c98d13 Mon Mar 12 17:23:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> remove the extern C around gdb helper functions. It's need needed for any new version of gdb to work and it causes at least mine to segfault
4074:f2c4afa8cd46 Sat Feb 17 23:32:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Default to tracing being disabled in C++, it will be turned
on in python. Fix the trace start code so it actually starts
when it is suppsed to. Make the Exec tracing stuff obey the
trace enabled flag.
4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since
its not all that useful. Fix a few bugs with python/C++
integration.
4042:dbd98b2264ed Fri Feb 09 17:39:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the Trace ParamContext and give python direct
access to enabling/disabling tracing. Command line is
unchanged except for the removal of --trace-cycle since
it's not so clear what that means.
4039:b910b61a52b9 Thu Feb 08 01:11:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Get rid of the gross operator,()/variadic macro hack
that made ccprintf and friends work, turn it into a
normal function (though it still has a slightly strange
implementation.) All instances of variadic macros
are not yet removed, but I know how, and it will happen.

One side effect of this new implementation is that a
cprintf statement can now only have 16 parameters, though
it's easy enough to raise this number if needed.
/gem5/src/arch/x86/
H A Dtypes.hh5251:8de83cada19d Thu Nov 15 14:17:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add CoreSpecific type to all archs
5138:069bbeae1ef8 Sun Oct 07 21:16:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Significantly filled out misc regs.
4863:b6dacc9a39ff Sat Aug 04 23:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
4803:e322a815fd25 Mon Jul 30 16:20:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Missed a file for adding a bit to indicate that an REX prefix was present.
4717:040769cb51b9 Fri Jul 20 17:57:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a bitfield to decode based on what prefixes are used.
4707:cc95d295c5ed Wed Jul 18 20:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix the overload which prints ExtMachInst in X86.
4680:09867d787df8 Sat Jul 14 20:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Move bitunion code into it's own file.
4601:38c989d15fef Wed Jun 20 11:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make memory instructions work better, add more macroop implementations, add an lea microop, move EmulEnv into it's own .cc and .hh.
4587:2c9a2534a489 Tue Jun 19 10:18:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Get rid of the immediate and displacement components of the EmulEnv struct and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops.
4569:8720f7848610 Thu Jun 14 09:50:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Put the mode in the ExtMachInst.
H A DX86TLB.py5245:d94bb8af9f76 Mon Nov 12 21:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Separate out the page table walker into it's own cc and hh.
5237:6c819dbe8045 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Work on the page table walker, TLB, and related faults.
5236:0050ad4fb3ef Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement a page table walker.
5124:3d8c50376609 Wed Oct 03 02:00:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
/gem5/src/arch/sparc/
H A Dtlb.cc5288:7dd5694453b3 Fri Nov 30 19:49:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Fixes for invalidateAll and demapAll in the SPARC TLBs.
5276:2f55b8e7f346 Mon Nov 19 22:47:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Serialization: Serialize SPARC PTEs last so their nameOut() calls don't interfere with other serialization in the TLB.
5100:7a0180040755 Fri Sep 28 13:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Rename cycles() function to ticks()
5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors.

SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
4996:e827e57a01f9 Sun Aug 26 23:15:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Make sure unaligned access are caught on cached translations as well.
4990:38d74405ddac Mon Aug 13 19:06:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Move tlb state into the tlb.
Each "strand" may need to have a private copy of this state, but I couldn't
find anywhere in the spec that said that after looking briefly.
This prevents writes to the thread context in o3 which was causing the
pipeline to be flushed and stopping any forward progress. The other ASI
accessible state will probably need to be accessed differently if/when we get
O3 full system up and running.
4989:3e9d532cf998 Mon Aug 13 19:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault ASI accesses work.
4918:3214e3694fb2 Fri Jul 27 02:15:00 EDT 2007 Nathan Binkert <nate@binkert.org> Merge python and x86 changes with cache branch
4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are
now encoded in cmd field.
/gem5/src/arch/x86/isa/microops/
H A Dlimmop.isa5188:974af6059943 Tue Oct 30 16:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Compile fixes for 32 bit/debug/opt.
4804:4a707cb7065b Mon Jul 30 16:23:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make disassembly use the final register index. Add bits to indicate whether or not register indexes should be "folded".
4792:ccab7ba2c6e5 Sun Jul 29 04:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make limm use merge and allow overriding the data size.
4693:ca44a1014212 Tue Jul 17 21:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make disassembled x86 register indices reflect their size.
This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.
4679:0b39fa8f5eb8 Sat Jul 14 20:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Pull some hard coded base classes out of the isa description.
4581:23166f771fa4 Mon Jun 18 10:15:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add in incomplete pick and merge functions which read and write pieces of registers, and fill out microcode disassembly.
4576:31f715613103 Thu Jun 14 16:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix limm.
4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent.

src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
4524:f051dcff22b3 Mon Jun 04 15:53:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make limm (load immediate) microop
H A Dspecop.isa5293:5ea2a6dc8f17 Sun Dec 02 02:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make the "fault" microop predicated.
5173:07204d59a328 Fri Oct 19 18:11:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Impelement the HLT instruction and fix the "halt" microop.
5172:4f0e76579e7c Fri Oct 19 18:10:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement a "halt" microop.
5163:f08b480df4c3 Fri Oct 19 01:40:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make the "fault" microop predicated.
4696:459853ed322c Wed Jul 18 19:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a generateDisassembly function to the MicroFault StaticInst.
4679:0b39fa8f5eb8 Sat Jul 14 20:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Pull some hard coded base classes out of the isa description.
4590:5c3813b700a3 Tue Jun 19 10:50:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Renovate the "fault" microop implementation.
4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent.

src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
4519:f8da6b45573f Mon Jun 04 11:59:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Reworking x86's microcode system. This is a work in progress, and X86 doesn't compile.

src/arch/x86/isa/decoder/one_byte_opcodes.isa:
src/arch/x86/isa/macroop.isa:
src/arch/x86/isa/main.isa:
src/arch/x86/isa/microasm.isa:
src/arch/x86/isa/microops/base.isa:
src/arch/x86/isa/microops/microops.isa:
src/arch/x86/isa/operands.isa:
src/arch/x86/isa/microops/regop.isa:
src/arch/x86/isa/microops/specop.isa:
Reworking x86's microcode system
H A Dldstop.isa5232:d3801ea2792e Mon Nov 12 17:37:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Various fixes to indexing segmentation related registers
5178:8914ea55a0c6 Mon Oct 22 17:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the cda microop which checks if an address is legal to write to.
5175:ee904e392de2 Sun Oct 21 21:44:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the stupd microop ("store with update", not "stupid") and use it in ENTER.
5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.
5118:f1b1cb6d0fbe Wed Oct 03 01:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the ldst microop and put it in existing microcode where appropriate.
5027:e96b8a4f4d96 Wed Aug 29 23:36:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add load and store microops that use the fp registers.
5002:1b540e93ad34 Sun Aug 26 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Remove x86 code that attempted to fix misaligned accesses.
4867:2de05bc73640 Sat Aug 04 23:22:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make 64 bit unaligned accesses work as well as the other sizes.
There is a fundemental flaw in how unaligned accesses are supported, but this
is still an improvement.
4863:b6dacc9a39ff Sat Aug 04 23:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
4834:9480bde3ae6a Wed Aug 01 03:49:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix for compilation bug with new cache code.
/gem5/util/
H A Dregress5247:fdbfa56f0b09 Tue Nov 13 21:45:00 EST 2007 Steve Reinhardt <stever@gmail.com> Add -k flag to util/regress.
5187:a0ff86ffdefe Fri Oct 26 17:32:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Regressions: Added X86_SE into the default list of builds.
4976:eb1067b3060c Mon Aug 13 23:45:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> fixup bad hand merge
4975:3fd697e69e06 Mon Aug 13 23:44:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Merge IGNORE_STYLE change and my change.
4961:31f1d816dc26 Mon Aug 13 23:40:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Regression: See if using subprocess instead of os.system and erroring immediately will stop regression randomly hanging.
4949:302707329b7e Sun Aug 12 12:56:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: If IGNORE_STYLE=True is set on the scons command line, ignore style.
Use this in the regress script to avoid issues with the checker.
4193:1363532bc464 Fri Mar 09 16:27:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> fix regress... SPARC_FS may not be in the builds so check for it
4169:b03a74834dfe Wed Mar 07 00:45:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> If we're running the quick tests, remove the SPARC_FS build since we don't have any quick SPARC_FS tests at the moment
4130:a611c874376e Sat Mar 03 22:45:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add a sparc fs regression

src/dev/sparc/iob.cc:
don't warn on cpu restart/idle/halt stuff
tests/SConscript:
add sparc target in test Sconscript
util/regress:
Add SPARC_FS target in regress
/gem5/configs/common/
H A Dcpu2000.py4555:7db37af44eb6 Sun Jun 10 16:57:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> the cmd argument is supposed to be an array of parameters, not one string
4271:13ea06ef646d Thu Mar 22 00:10:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix mcf benchmark object so it gets the arguments it expects.
4132:a4ed11288493 Mon Mar 05 06:00:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86
4116:f6e3dc4655e9 Fri Mar 02 22:34:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Keep around which input set was used for a benchmark, and make vortex work with SPARC.
4107:3ac1abf8e035 Tue Feb 27 05:37:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Fix issue with twolf where the presence or absence of two files, smred.sav or smred.sv2, would affect the outcome of the program. These names are based on the input file names which are in turn based on the input set selected. There may be more files like this generated for larger input sets, for example "mdred.sv3"
/gem5/src/arch/sparc/isa/
H A Ddecoder.isa5096:eb06635e06ac Tue Sep 25 23:11:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Remove parameter that was only ever set to one value.
5095:65cc3a615375 Tue Sep 25 23:10:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Remove some redundant code from some of the fp instructions.
5094:10b8551e3e3f Tue Sep 25 23:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Clean up of privileged instructions.
5093:7f20bc69fda5 Tue Sep 25 23:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Long overdue cleanup of the condition code handlers.
5091:662c1d7b4795 Tue Sep 25 23:05:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Clean up the branch instructions a bit.
4828:768d4cf6b0dc Tue Jul 31 20:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a flag to indicate an instruction triggers a syscall in SE mode.
4256:35bb4cc24b18 Sat Mar 17 21:23:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> The syntax used for twin stores was confusing the parser so it's now broken down farther.
4237:3493eb63512e Mon Mar 12 17:07:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix mulscc.
4235:945b78b3477b Mon Mar 12 01:47:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix the mnemonic and the branch displacement field size of the branch on floating point condition codes with prediction.
4224:7e828583f2cb Sun Mar 11 18:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make sttw and sttwa use the twin memory operations.
/gem5/src/arch/mips/linux/
H A Dlinux.cc5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
H A Dsystem.cc5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/arch/mips/
H A Dsystem.cc5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Dpagetable.hh5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Dutility.hh5267:5210230f1497 Fri Nov 16 21:31:00 EST 2007 Korey Sewell <ksewell@umich.edu> move initCPU, processInterrupts declaration to core_specific file.
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4846:1811b9542646 Wed Aug 01 19:57:00 EDT 2007 Nathan Binkert <nate@binkert.org> mips: make getArgument inline so mips will link properly
4836:404719c5ed86 Wed Aug 01 17:05:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Merge Gabe and my changes to arch/mips/utility.hh
4835:224d8f96e155 Wed Aug 01 16:55:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> MIPS: Cleaned up includes to break loops, and got rid of isa_traits.cc
Loops of header files including each other was causing compilation to fail. To fix it, a bunch of unnecessary includes were removed, and the code in isa_traits.cc which brought a bunch of include chains together was broken up and put in proximity to the header files that delcared it.
4826:259b996a6da6 Wed Aug 01 16:59:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Arguments: Get rid of duplicate code for the Arguments class in each architecture.
Move the argument files to src/sim and add a utility.cc file with a function
getArguments() that returns the given argument in the architecture specific fashion.
getArguments() was getArg() is the architecture specific Argument class and has had
all magic numbers replaced with meaningful constants. Also add a function to the
Argument class for testing if an argument is NULL.
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/arch/mips/utility.hh:
src/arch/x86/SConscript:
Hand merge
4194:af4f6022394b Fri Mar 09 16:56:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> implement ipi stufff for SPARC

src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/arch/x86/utility.hh:
add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi
src/arch/sparc/isa/decoder.isa:
handle writable bits of strandstatus register in miscregfile
src/arch/sparc/miscregfile.hh:
some constants for the strand status register
src/arch/sparc/ua2005.cc:
properly implement the strand status register
src/dev/sparc/iob.cc:
implement ipi generation properly
src/sim/system.cc:
call into the ISA to start the CPU (or not)
/gem5/src/arch/sparc/isa/formats/mem/
H A Dswap.isa5096:eb06635e06ac Tue Sep 25 23:11:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Remove parameter that was only ever set to one value.
4650:bb9977571ff4 Wed May 09 23:50:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into doughnut.mwconnections.com:/home/gblack/newmem-o3-micro
4648:173a212f5091 Tue May 08 09:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a hack to truncate addresses to 32 bits in SE. Paging should be changed to use the architecture's TLB, at which point this can be removed.
4412:e6e98db4f373 Fri Apr 27 16:59:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> gcc 4.1 claims that mem_data might be used uninitialized,
though I don't believe that's true. Placate it anyway.
4350:c3f402102507 Sat Apr 07 21:42:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Get the "hard" SPARC instructions working in o3. I don't like that the IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.
4040:eb894f3fc168 Mon Feb 12 13:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> rename store conditional stuff as extra data so it can be used for conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
Make atomic memory ops atomic
Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
add a post access code block
src/arch/sparc/isa/includes.isa:
need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
add support for twinloads
add support for swap and conditional swap instructions
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
Add support for atomic swap memory commands
src/mem/packet_access.hh:
Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
Add support for atomic swap memory commands
Rename sc code to extradata
/gem5/src/arch/mips/isa/
H A Dmain.isa5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode

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