1// Copyright (c) 2007-2008 The Hewlett-Packard Development Company 2// Copyright (c) 2015 Advanced Micro Devices, Inc. 3// All rights reserved. 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software 9// licensed hereunder. You may use the software subject to the license 10// terms below provided that you ensure that this notice is replicated 11// unmodified and in its entirety in all distributions of the software, 12// modified or unmodified, in source code or in binary form. 13// 14// Copyright (c) 2007 The Regents of The University of Michigan 15// Copyright (c) 2012 Mark D. Hill and David A. Wood 16// Copyright (c) 2012-2013 Advanced Micro Devices, Inc. 17// All rights reserved. 18// 19// Redistribution and use in source and binary forms, with or without 20// modification, are permitted provided that the following conditions are 21// met: redistributions of source code must retain the above copyright 22// notice, this list of conditions and the following disclaimer; 23// redistributions in binary form must reproduce the above copyright 24// notice, this list of conditions and the following disclaimer in the 25// documentation and/or other materials provided with the distribution; 26// neither the name of the copyright holders nor the names of its 27// contributors may be used to endorse or promote products derived from 28// this software without specific prior written permission. 29// 30// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 33// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 35// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 36// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 37// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 38// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 39// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 40// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41// 42// Authors: Gabe Black 43 44def operand_types {{ 45 'sb' : 'int8_t', 46 'ub' : 'uint8_t', 47 'sw' : 'int16_t', 48 'uw' : 'uint16_t', 49 'sdw' : 'int32_t', 50 'udw' : 'uint32_t', 51 'sqw' : 'int64_t', 52 'uqw' : 'uint64_t', 53 'u2qw' : 'std::array<uint64_t, 2>', 54 'sf' : 'float', 55 'df' : 'double', 56}}; 57 58let {{ 59 def foldInt(idx, foldBit, id): 60 return ('IntReg', 'uqw', 'INTREG_FOLDED(%s, %s)' % (idx, foldBit), 61 'IsInteger', id) 62 def intReg(idx, id): 63 return ('IntReg', 'uqw', idx, 'IsInteger', id) 64 def impIntReg(idx, id): 65 return ('IntReg', 'uqw', 'INTREG_IMPLICIT(%s)' % idx, 'IsInteger', id) 66 def floatReg(idx, id): 67 return ('FloatReg', 'df', idx, 'IsFloating', id) 68 def ccReg(idx, id): 69 return ('CCReg', 'uqw', idx, 'IsCC', id) 70 def controlReg(idx, id, ctype = 'uqw'): 71 return ('ControlReg', ctype, idx, 72 (None, None, ['IsSerializeAfter', 73 'IsSerializing', 74 'IsNonSpeculative']), 75 id) 76 def squashCheckReg(idx, id, check, ctype = 'uqw'): 77 return ('ControlReg', ctype, idx, 78 (None, None, ['((%s) ? ' % check+ \ 79 'IsSquashAfter : IsSerializeAfter)', 80 'IsSerializing', 81 'IsNonSpeculative']), 82 id) 83 def squashCReg(idx, id, ctype = 'uqw'): 84 return squashCheckReg(idx, id, 'true', ctype) 85 def squashCSReg(idx, id, ctype = 'uqw'): 86 return squashCheckReg(idx, id, 'dest == SEGMENT_REG_CS', ctype) 87 def squashCR0Reg(idx, id, ctype = 'uqw'): 88 return squashCheckReg(idx, id, 'dest == 0', ctype) 89}}; 90 91def operands {{ 92 'SrcReg1': foldInt('src1', 'foldOBit', 1), 93 'SSrcReg1': intReg('src1', 1), 94 'SrcReg2': foldInt('src2', 'foldOBit', 2), 95 'SSrcReg2': intReg('src2', 1), 96 'Index': foldInt('index', 'foldABit', 3), 97 'Base': foldInt('base', 'foldABit', 4), 98 'DestReg': foldInt('dest', 'foldOBit', 5), 99 'SDestReg': intReg('dest', 5), 100 'Data': foldInt('data', 'foldOBit', 6), 101 'DataLow': foldInt('dataLow', 'foldOBit', 6), 102 'DataHi': foldInt('dataHi', 'foldOBit', 6), 103 'ProdLow': impIntReg(0, 7), 104 'ProdHi': impIntReg(1, 8), 105 'Quotient': impIntReg(2, 9), 106 'Remainder': impIntReg(3, 10), 107 'Divisor': impIntReg(4, 11), 108 'DoubleBits': impIntReg(5, 11), 109 'Rax': intReg('(INTREG_RAX)', 12), 110 'Rbx': intReg('(INTREG_RBX)', 13), 111 'Rcx': intReg('(INTREG_RCX)', 14), 112 'Rdx': intReg('(INTREG_RDX)', 15), 113 'Rsp': intReg('(INTREG_RSP)', 16), 114 'Rbp': intReg('(INTREG_RBP)', 17), 115 'Rsi': intReg('(INTREG_RSI)', 18), 116 'Rdi': intReg('(INTREG_RDI)', 19), 117 'FpSrcReg1': floatReg('src1', 20), 118 'FpSrcReg2': floatReg('src2', 21), 119 'FpDestReg': floatReg('dest', 22), 120 'FpData': floatReg('data', 23), 121 'RIP': ('PCState', 'uqw', 'pc', 122 (None, None, 'IsControl'), 50), 123 'NRIP': ('PCState', 'uqw', 'npc', 124 (None, None, 'IsControl'), 50), 125 'nuIP': ('PCState', 'uqw', 'nupc', 126 (None, None, 'IsControl'), 50), 127 # These registers hold the condition code portion of the flag 128 # register. The nccFlagBits version holds the rest. 129 'ccFlagBits': ccReg('(CCREG_ZAPS)', 60), 130 'cfofBits': ccReg('(CCREG_CFOF)', 61), 131 'dfBit': ccReg('(CCREG_DF)', 62), 132 'ecfBit': ccReg('(CCREG_ECF)', 63), 133 'ezfBit': ccReg('(CCREG_EZF)', 64), 134 135 # These Pred registers are to be used where reading the portions of 136 # condition code registers is possibly optional, depending on how the 137 # check evaluates. There are two checks being specified, one tests if 138 # a register needs to be read, the other tests whether the register 139 # needs to be written to. It is unlikely that these would need to be 140 # used in the actual operation of the instruction. It is expected 141 # that these are used only in the flag code. 142 143 # Rationale behind the checks: at times, we need to partially update 144 # the condition code bits in a register. So we read the register even 145 # in the case when the all the bits will be written, or none of the 146 # bits will be written. The read predicate checks if any of the bits 147 # would be retained, the write predicate checks if any of the bits 148 # are being written. 149 150 'PredccFlagBits': ('CCReg', 'uqw', '(CCREG_ZAPS)', 'IsCC', 151 60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit 152 )) != (PFBit | AFBit | ZFBit | SFBit )) && 153 ((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''', 154 '((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'), 155 'PredcfofBits': ('CCReg', 'uqw', '(CCREG_CFOF)', 'IsCC', 156 61, None, None, '''(((ext & CFBit) == 0 || 157 (ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''', 158 '((ext & (CFBit | OFBit)) != 0)'), 159 'PreddfBit': ('CCReg', 'uqw', '(CCREG_DF)', 'IsCC', 160 62, None, None, '(false)', '((ext & DFBit) != 0)'), 161 'PredecfBit': ('CCReg', 'uqw', '(CCREG_ECF)', 'IsCC', 162 63, None, None, '(false)', '((ext & ECFBit) != 0)'), 163 'PredezfBit': ('CCReg', 'uqw', '(CCREG_EZF)', 'IsCC', 164 64, None, None, '(false)', '((ext & EZFBit) != 0)'), 165 166 # These register should needs to be more protected so that later 167 # instructions don't map their indexes with an old value. 168 'nccFlagBits': controlReg('MISCREG_RFLAGS', 65), 169 170 # Registers related to the state of x87 floating point unit. 171 'TOP': controlReg('MISCREG_X87_TOP', 66, ctype='ub'), 172 'FSW': controlReg('MISCREG_FSW', 67, ctype='uw'), 173 'FTW': controlReg('MISCREG_FTW', 68, ctype='uw'), 174 'FCW': controlReg('MISCREG_FCW', 69, ctype='uw'), 175 176 # The segment base as used by memory instructions. 177 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), 178 179 # Operands to get and set registers indexed by the operands of the 180 # original instruction. 181 'ControlDest': squashCR0Reg('MISCREG_CR(dest)', 100), 182 'ControlSrc1': controlReg('MISCREG_CR(src1)', 101), 183 'DebugDest': controlReg('MISCREG_DR(dest)', 102), 184 'DebugSrc1': controlReg('MISCREG_DR(src1)', 103), 185 'SegBaseDest': squashCSReg('MISCREG_SEG_BASE(dest)', 104), 186 'SegBaseSrc1': controlReg('MISCREG_SEG_BASE(src1)', 105), 187 'SegLimitDest': squashCSReg('MISCREG_SEG_LIMIT(dest)', 106), 188 'SegLimitSrc1': controlReg('MISCREG_SEG_LIMIT(src1)', 107), 189 'SegSelDest': controlReg('MISCREG_SEG_SEL(dest)', 108), 190 'SegSelSrc1': controlReg('MISCREG_SEG_SEL(src1)', 109), 191 'SegAttrDest': squashCSReg('MISCREG_SEG_ATTR(dest)', 110), 192 'SegAttrSrc1': controlReg('MISCREG_SEG_ATTR(src1)', 111), 193 194 # Operands to access specific control registers directly. 195 'EferOp': squashCReg('MISCREG_EFER', 200), 196 'CR4Op': controlReg('MISCREG_CR4', 201), 197 'DR7Op': controlReg('MISCREG_DR7', 202), 198 'LDTRBase': controlReg('MISCREG_TSL_BASE', 203), 199 'LDTRLimit': controlReg('MISCREG_TSL_LIMIT', 204), 200 'LDTRSel': controlReg('MISCREG_TSL', 205), 201 'GDTRBase': controlReg('MISCREG_TSG_BASE', 206), 202 'GDTRLimit': controlReg('MISCREG_TSG_LIMIT', 207), 203 'CSBase': squashCReg('MISCREG_CS_EFF_BASE', 208), 204 'CSAttr': squashCReg('MISCREG_CS_ATTR', 209), 205 'MiscRegDest': controlReg('dest', 210), 206 'MiscRegSrc1': controlReg('src1', 211), 207 'TscOp': controlReg('MISCREG_TSC', 212), 208 'M5Reg': squashCReg('MISCREG_M5_REG', 213), 209 'Mem': ('Mem', 'uqw', None, \ 210 ('IsMemRef', 'IsLoad', 'IsStore'), 300) 211}}; 212