Searched hist:2007 (Results 276 - 300 of 895) sorted by relevance

<<11121314151617181920>>

/gem5/src/arch/mips/
H A Dkernel_stats.hh5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
H A Dpagetable.cc5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/arch/x86/isa/
H A Dmacroop.isa5161:e7334f2d7bef Fri Oct 19 01:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the in/out instructions. These will still need support from the TLB and memory system.
5046:da031ef02439 Wed Sep 05 02:32:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add some SSE floating point/integer conversion microops.
5040:126e4510b5bb Sat Sep 01 01:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Major rework of how regop microops are generated.
The new implementation uses metaclass, and gives a lot more precise control
with a lot less verbosity. The flags/no flags reg/imm variants are all handled
by the same python class now which supplies a constructor to the right C++
class based on context.
5009:78d53ea88c74 Sun Aug 26 23:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make the microassembler accept lines which are just labels.
The labels on these lines will be associated with whatever the next microop
is.
4863:b6dacc9a39ff Sat Aug 04 23:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing segmentation support.
Make instructions observe segment prefixes, default segment rules, segment
base addresses.
Also fix some microcode and add sib and riprel "keywords" to the x86
specialization of the microassembler.
4746:7960a6867f55 Sun Jul 22 21:07:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the operand size reflect the size specifier on the operand tags, and implement NEG
4601:38c989d15fef Wed Jun 20 11:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make memory instructions work better, add more macroop implementations, add an lea microop, move EmulEnv into it's own .cc and .hh.
4587:2c9a2534a489 Tue Jun 19 10:18:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Get rid of the immediate and displacement components of the EmulEnv struct and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops.
4567:5c7b9832235d Thu Jun 14 09:47:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Get rid of some debug output and let macroops set headers in their constructor. The intention is to allow them to modify the emulation environment struct before it's used to construct its microops.
4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent.

src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
H A Dincludes.isa5118:f1b1cb6d0fbe Wed Oct 03 01:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the ldst microop and put it in existing microcode where appropriate.
5083:49559a8060e8 Wed Sep 19 21:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move the fp microops to their own file with their own base classes in C++ and python.
5058:be23162b7370 Thu Sep 06 19:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add SSE comparison instructions and microops and move some FP microops to be with the other ones.
5026:46dd8d55f6c9 Wed Aug 29 23:35:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add operands to handle floating point registers.
4685:e38f50632338 Tue Jul 17 16:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Actually include miscregs.hh
4679:0b39fa8f5eb8 Sat Jul 14 20:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Pull some hard coded base classes out of the isa description.
4619:b914b33406b8 Thu Jun 21 16:35:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Get rid of an unnecessary include file.
4616:99c9f2cbc4a8 Thu Jun 21 11:29:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Needed for last change set to work :P
4601:38c989d15fef Wed Jun 20 11:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make memory instructions work better, add more macroop implementations, add an lea microop, move EmulEnv into it's own .cc and .hh.
4543:4cbcab038791 Tue Jun 12 12:29:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Get rid of unnecessary namespace prototype.
/gem5/src/cpu/
H A Dnativetrace.cc5049:16a0724434b8 Wed Sep 05 02:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86/StateTrace: Make m5 and statetrace track mmx and xmm registers, and actually compare xmm.
5038:c996bb7f1a6d Fri Aug 31 16:02:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Get x86 to compile again after the simobject constructor change.
4830:aad1410a2b79 Wed Aug 01 03:01:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize the native tracing code.
Ignore different values or rcx and r11 after a syscall until either the local or remote value changes. Also change the codes organization somewhat.
4790:f71b033c83e1 Sun Jul 29 04:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix register ordering.
The correct order is unintuitively rax, rcx, rdx, rbx, etc, not rax, rbx, rcx, rdx.
4776:8c8407243a2c Sat Jul 28 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Turn the instruction tracing code into pluggable sim objects.
These need to be refined a little still and given parameters.
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/
H A Dmove.py5302:a1c79b171e23 Sun Dec 02 03:02:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make the 0xA0-0xA3 versions of mov use the right sized immediates.
5296:5caa774215cd Sun Dec 02 02:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement mov from control register.
5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs.
5241:a6602acdd046 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the wrcr microop which writes a control register, and some control register work.
5239:0920dfb94514 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.
5151:dec27c6c2b3b Fri Oct 12 23:08:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Added some new versions of MOV and a new argument type tag.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dconditional_move.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/dev/alpha/
H A DSConscript5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
H A Dtsunamireg.h4059:e9cef915589f Tue Feb 13 15:58:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Make mulitple consoles work and be distinguishable from each other

src/dev/alpha/tsunamireg.h:
get rid of things that aren't really tsunami registers
src/dev/platform.hh:
src/dev/uart.cc:
the uart pointer isn't used anymore
src/dev/simconsole.cc:
make the simconsole print something more useful to distinguish between various consoles in a single system
src/dev/uart8250.hh:
put the needed uart defines in here rather than including them from tsunamireg
src/python/m5/objects/T1000.py:
add a console to the T1000 config for the hypervisor
/gem5/src/arch/mips/isa/formats/
H A Dformats.isa5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
/gem5/src/arch/x86/isa/insts/general_purpose/control_transfer/
H A Dcall.py5176:43fb805e1b85 Sun Oct 21 21:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start using the stupd microop, and update statistics accordingly.
5119:a4469f2919f3 Wed Oct 03 01:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/system/
H A Dsegmentation.py5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs.
5292:a26311673ef0 Sun Dec 02 02:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the LIDT instruction.
5291:5d38610cff05 Sun Dec 02 02:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the lgdt instruction.
/gem5/src/cpu/simple/
H A DSConscript5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/
H A Dmove.py5123:cd30bb46e146 Wed Oct 03 01:58:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix places where movfp was used incorrectly.
5119:a4469f2919f3 Wed Oct 03 01:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/sim/
H A Dasync.cc4123:9c80390ea1bb Sat Mar 03 01:24:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Factor code out of main.cc and main.i into a bunch of files
so things are organized in a more sensible manner. Take apart
finalInit and expose the individual functions which are now
called from python. Make checkpointing a bit easier to use.
/gem5/src/arch/x86/
H A DSConsopts4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
/gem5/src/arch/x86/isa/insts/general_purpose/data_conversion/
H A Dendian_conversion.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/string/
H A Dscan_string.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/
H A Daddition.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Ddivision.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dmultiplication.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dsquare_root.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dsubtraction.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/compare/
H A Dcompare_and_write_minimum_or_maximum.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dcompare_and_write_rflags.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.

Completed in 77 milliseconds

<<11121314151617181920>>