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/gem5/src/arch/x86/isa/insts/simd64/integer/arithmetic/
H A Daddition.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dmultiply_add.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dsubtraction.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd64/integer/data_reordering/
H A Dpack_with_saturation.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/simd64/integer/logical/
H A Dpand.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/control/
H A Dsave_x87_status_word.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/
H A Dload_or_store_floating_point.py5121:a5f3cfdc4ee5 Wed Oct 03 01:57:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix x87 floating point stack register indexing.
5117:b422964a705c Wed Oct 03 01:06:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix up the microcode for the FST and FSTP instructions.
5084:675cb680830f Wed Sep 19 21:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the fld, fst, and fstp instructions.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dconvert_and_load_or_store_integer.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/transcendental_functions/
H A Dlogarithmic_functions.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/
H A Dx86_traits.hh5161:e7334f2d7bef Fri Oct 19 01:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the in/out instructions. These will still need support from the TLB and memory system.
5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.
5075:4ae876c5037d Thu Sep 13 19:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Total overhaul of the division instructions and microops.
5063:8eb72b1bd3c6 Thu Sep 06 19:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Rework the multiplication microops so that they work like they would in the patent.
5045:bf06c4d63bf4 Wed Sep 05 02:31:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add floating point micro registers.
5025:5c264911b7a9 Wed Aug 29 23:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Flesh out register indexing constants.
4682:3af5ab237724 Tue Jul 17 16:26:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a spot for the condition code portion of the flag register.
This is stored in the integer register file so that it can be renamed, but it should be a misc reg.
4578:1d4607d6acf4 Thu Jun 14 16:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add in some microregs.
4134:4a44fbb23297 Sun Mar 04 19:19:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> A new file for x86 specific parameters. This could be implemented as a sim object?
H A DSConscript5299:e61b9f2a9732 Sun Dec 02 02:09:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move startup code to the system object to initialize a Linux system.
5298:a836e89a8ee0 Sun Dec 02 02:07:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add a missing microcode file to the sconscript.
5245:d94bb8af9f76 Mon Nov 12 21:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Separate out the page table walker into it's own cc and hh.
5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
5173:07204d59a328 Fri Oct 19 18:11:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Impelement the HLT instruction and fix the "halt" microop.
5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.
5135:6ae576eada5c Sun Oct 07 21:10:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make initCPU and startupCPU do something basic.
5132:ad5e94876bfc Sun Oct 07 20:48:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make an x86 system object.
5124:3d8c50376609 Wed Oct 03 02:00:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.
5086:e7913ffb379d Mon Sep 24 20:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Get X86_FS to compile.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/arithmetic/
H A Dreciprocal_estimation.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/compare_and_test/
H A Dfloating_point_unordered_compare.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/insts/
H A Dmicroldstop.cc4842:e792fcf17ff9 Wed Aug 01 17:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Hide the irrelevant portions of the address components for load and store microops.
4804:4a707cb7065b Mon Jul 30 16:23:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make disassembly use the final register index. Add bits to indicate whether or not register indexes should be "folded".
4693:ca44a1014212 Tue Jul 17 21:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make disassembled x86 register indices reflect their size.
This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.
4679:0b39fa8f5eb8 Sat Jul 14 20:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Pull some hard coded base classes out of the isa description.
H A Dstatic_inst.cc5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs.
5232:d3801ea2792e Mon Nov 12 17:37:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Various fixes to indexing segmentation related registers
5202:ff56fa8c2091 Wed Oct 31 21:04:00 EDT 2007 Steve Reinhardt <stever@gmail.com> String constant const-ness changes to placate g++ 4.2.
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).
5121:a5f3cfdc4ee5 Wed Oct 03 01:57:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix x87 floating point stack register indexing.
5045:bf06c4d63bf4 Wed Sep 05 02:31:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add floating point micro registers.
4807:ffa0076e235f Mon Jul 30 16:26:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make register names in disassembly reflect high bytes.
4693:ca44a1014212 Tue Jul 17 21:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make disassembled x86 register indices reflect their size.
This doesn't handle high byte register accesses. It also highlights the fact that address size isn't actually being calculated, and that the size a microop uses needs to be overridable from the microassembly.
4679:0b39fa8f5eb8 Sat Jul 14 20:14:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Pull some hard coded base classes out of the isa description.
/gem5/src/arch/mips/
H A Ddsp.hh5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
H A Dsystem.hh5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/arch/x86/isa/microops/
H A Dregop.isa5296:5caa774215cd Sun Dec 02 02:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement mov from control register.
5295:5268691561b4 Sun Dec 02 02:05:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: First crack at far returns. This is grossly approximate.
5294:7222bdaed33b Sun Dec 02 02:03:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Reorganize segmentation and implement segment selector movs.
5291:5d38610cff05 Sun Dec 02 02:01:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the lgdt instruction.
5290:7dc3e8ee0a22 Sun Dec 02 02:00:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement wrbase and wrlimit for loading pseudo descriptors.
5246:21f29e99e021 Tue Nov 13 04:31:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make microcode use presegmentation RIPs and the rest of m5 use post segmentation RIPS.
5241:a6602acdd046 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the wrcr microop which writes a control register, and some control register work.
5239:0920dfb94514 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Change the meaning of the sext and zext width operand, and make sext set zext if the sign bit is 0.
5157:9c6c153af4b1 Fri Oct 19 01:36:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make wrip sign extend its second operand.
5138:069bbeae1ef8 Sun Oct 07 21:16:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Significantly filled out misc regs.
/gem5/src/arch/x86/isa/insts/general_purpose/arithmetic/
H A Dadd_and_subtract.py5119:a4469f2919f3 Wed Oct 03 01:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dincrement_and_decrement.py5119:a4469f2919f3 Wed Oct 03 01:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/data_transfer/
H A Dxchg.py5119:a4469f2919f3 Wed Oct 03 01:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/
H A Dlogical.py5119:a4469f2919f3 Wed Oct 03 01:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/
H A Drotate.py5119:a4469f2919f3 Wed Oct 03 01:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dshift.py5119:a4469f2919f3 Wed Oct 03 01:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put ldst into the microcode (the earlier changeset didn't really).
Also clean things up as much as possible so that faulting won't break an
instruction. More microops which verify addresses are needed.
5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/base/
H A Dfenv.c4571:04b82abadd44 Thu Jun 14 09:53:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fix an assert to allow rounding mode 0.
4394:dbaff14bb974 Sat Apr 21 17:50:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> create base/fenv.c to standerdize fenv across platforms. It's a c file and not a cpp file because c99
(which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really
desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment.

src/arch/alpha/isa/fp.isa:
src/arch/sparc/isa/formats/basic.isa:
use m5_fesetround()/m5_fegetround() istead of fenv interface directly
src/arch/sparc/isa/includes.isa:
use base/fenv instead of fenv directly
src/base/SConscript:
add fenv to sconscript
src/base/fenv.hh:
src/base/random.cc:
m5 implementation to standerdize fenv across platforms.

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