Searched hist:13741 (Results 1 - 6 of 6) sorted by relevance
| /gem5/src/arch/generic/ | ||
| H A D | tlb.hh | 13741:d994984b842a Fri Feb 22 11:29:00 EST 2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu> mem-cache: alias to mem::getMasterPort in TLB class TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and hides the BaseTLB::getMasterPort(). The TLB::getMasterPort() is renamed according to the expected behavior. Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8 Reviewed-on: https://gem5-review.googlesource.com/c/16648 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/x86/ | ||
| H A D | tlb.hh | 13741:d994984b842a Fri Feb 22 11:29:00 EST 2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu> mem-cache: alias to mem::getMasterPort in TLB class TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and hides the BaseTLB::getMasterPort(). The TLB::getMasterPort() is renamed according to the expected behavior. Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8 Reviewed-on: https://gem5-review.googlesource.com/c/16648 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | tlb.cc | 13741:d994984b842a Fri Feb 22 11:29:00 EST 2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu> mem-cache: alias to mem::getMasterPort in TLB class TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and hides the BaseTLB::getMasterPort(). The TLB::getMasterPort() is renamed according to the expected behavior. Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8 Reviewed-on: https://gem5-review.googlesource.com/c/16648 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/ | ||
| H A D | tlb.hh | 13741:d994984b842a Fri Feb 22 11:29:00 EST 2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu> mem-cache: alias to mem::getMasterPort in TLB class TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and hides the BaseTLB::getMasterPort(). The TLB::getMasterPort() is renamed according to the expected behavior. Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8 Reviewed-on: https://gem5-review.googlesource.com/c/16648 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | tlb.cc | 13741:d994984b842a Fri Feb 22 11:29:00 EST 2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu> mem-cache: alias to mem::getMasterPort in TLB class TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and hides the BaseTLB::getMasterPort(). The TLB::getMasterPort() is renamed according to the expected behavior. Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8 Reviewed-on: https://gem5-review.googlesource.com/c/16648 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/cpu/ | ||
| H A D | base.cc | 13741:d994984b842a Fri Feb 22 11:29:00 EST 2019 Andrea Mondelli <Andrea.Mondelli@ucf.edu> mem-cache: alias to mem::getMasterPort in TLB class TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and hides the BaseTLB::getMasterPort(). The TLB::getMasterPort() is renamed according to the expected behavior. Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8 Reviewed-on: https://gem5-review.googlesource.com/c/16648 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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