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/gem5/src/arch/sparc/solaris/
H A Dsolaris.hh11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps

For O3, which has a stat that counts reg reads, there is an additional
reg read per mmap() call since there's an arg we no longer ignore.
Otherwise, stats should not be affected.
11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct

The structure definition only had the open system call flag set in mind when
it was named, so we rename it here with the intention of using it to define
additional tables to translate flags for other system calls in the future.
/gem5/tests/long/se/20.parser/ref/arm/linux/minor-timing/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11388:bd4125134e77 Thu Mar 17 13:30:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap changes
/gem5/tests/long/se/50.vortex/ref/arm/linux/minor-timing/
H A Dconfig.ini11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11388:bd4125134e77 Thu Mar 17 13:30:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap changes
/gem5/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/
H A Dsimerr11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support

Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
/gem5/src/mem/ruby/profiler/
H A DAccessTraceForAddress.cc6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/tests/long/se/70.twolf/ref/x86/linux/o3-timing/
H A Dsimerr11959:c000bfbbdadd Thu Mar 30 20:59:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update the stats for 70.twolf for x86 o3-timing mode.

The following CL changed the stats:

commit 43418e7f81099072fb7d56dae11110ae1d858162
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 13:07:43 2017 -0600

syscall-emul: Move memState into its own file

It would be a good idea to try to figure out why, since it doesn't *look* like
this change was intended to move things around in memory or otherwise change
simulated behavior.

Change-Id: I0173ffdfb680a91b8c91f2bf5d7f72c76e7a8b63
Reviewed-on: https://gem5-review.googlesource.com/2655
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
H A Dstats.txt11959:c000bfbbdadd Thu Mar 30 20:59:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update the stats for 70.twolf for x86 o3-timing mode.

The following CL changed the stats:

commit 43418e7f81099072fb7d56dae11110ae1d858162
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 13:07:43 2017 -0600

syscall-emul: Move memState into its own file

It would be a good idea to try to figure out why, since it doesn't *look* like
this change was intended to move things around in memory or otherwise change
simulated behavior.

Change-Id: I0173ffdfb680a91b8c91f2bf5d7f72c76e7a8b63
Reviewed-on: https://gem5-review.googlesource.com/2655
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11441:0edcf757b6a2 Sat Apr 09 00:13:00 EDT 2016 Andreas Hansson <andreas.hansson@arm.com> stats: Match current behaviour

Small changes to the branch predictor and BTB caused stats changes
throughout.
11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support

Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
11388:bd4125134e77 Thu Mar 17 13:30:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap changes
11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
9901:13c5fea24be1 Wed Oct 02 05:03:00 EDT 2013 Andreas Sandberg <andreas@sandberg.pp.se> stats: Update x86 stats after x87 fixes

The updates to the x87 caused the stats for several regressions to
change. This was mainly caused by the addition of a working 32-bit and
80-bit FP load instruction and xsave support.
9568:cd1351d4d850 Fri Mar 01 13:20:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats to reflect SimpleDRAM changes

This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
9463:13e68ad8db54 Mon Jan 14 10:23:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> stats: Bump failing x86 regression stats

This patch bumps the stats of mcf and twolf for the o3 CPU such that
the regressions pass.
9449:56610ab73040 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for previous changes.
H A Dconfig.ini11959:c000bfbbdadd Thu Mar 30 20:59:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update the stats for 70.twolf for x86 o3-timing mode.

The following CL changed the stats:

commit 43418e7f81099072fb7d56dae11110ae1d858162
Author: Brandon Potter <Brandon.Potter@amd.com>
Date: Wed Mar 1 13:07:43 2017 -0600

syscall-emul: Move memState into its own file

It would be a good idea to try to figure out why, since it doesn't *look* like
this change was intended to move things around in memory or otherwise change
simulated behavior.

Change-Id: I0173ffdfb680a91b8c91f2bf5d7f72c76e7a8b63
Reviewed-on: https://gem5-review.googlesource.com/2655
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
9449:56610ab73040 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for previous changes.
9039:9a22621c741c Mon Jun 04 13:43:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Update stats for the CPUID change.
/gem5/src/arch/arm/tracers/
H A DSConscript12642:d0ce95094a54 Wed Mar 14 13:26:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace generation

This patch introduces the TarmacTracer: an instruction tracer which
allows to dump a gem5 execution trace in Tarmac format [1]. The new
tracer is supporting either Tarmac and TarmacV8 format specifications.
Not every traceable information has been implemented:

Implemented Trace Type:
Instruction Trace
Register Trace
Processor Memory Access Trace

Unimplemented Trace Type:
Program Flow Trace
Event Trace
Memory Bus Trace

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I8799d8e5852e868673f728971db3fe8c63961f5e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9382
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
12641:4c67bbebe381 Wed Mar 14 13:25:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Add support for Tarmac trace-based simulation

A new InstTracer (TarmacParser) has been implemented. This tracer is
parsing a pre-existing Tarmac trace file [1] while gem5 is running; it
is comparing execution data together with trace data and it is dumping
differences.
This allows to use Tarmac format as a glue between heterogeneous
simuators speaking the same Tarmac language.

Kudos to Giacomo Gabrielli for writing the original tracer.

[1]: https://developer.arm.com/docs/dui0845/f/tarmac-trace-file-format

Change-Id: I9b92204a149813166166adba4a7c61a248bdcac3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9381
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/dev/ps2/
H A DPS2.py12655:a1646f7c13ab Mon Apr 09 13:38:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> ps2: Add a simple touchscreen model

Add a touchscreen model that is compatible with Linux's TouchKit
driver. This model is based on the model in the Arm PL050 KMI model.

Change-Id: Id4d88a21a26bb42c455e4d778cd89875f650ac57
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9764
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
12654:749de33b7af6 Mon Apr 09 13:35:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> ps2: Add VNC support to the keyboard model

Add support for keyboard input from the VNC server in the PS/2
keyboard model. The introduced code is based on the functionality in
the Arm PL050 KMI model.

Change-Id: If04a9713e5a15e2149d1a7471b999e3060d8ee7d
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9763
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/mem/cache/compressors/
H A DCompressors.py13944:5000533e6b81 Wed Jun 13 10:39:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Create BDI Compressor

Implement Base-Delta-Immediate compression, as described in
'Base-Delta-Immediate Compression: Practical Data Compression
for On-Chip Caches'

Change-Id: I7980c340ab53a086b748f4b2108de4adc775fac8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11412
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
13942:e8b59b523af6 Wed Jun 13 08:36:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Create cache compressor

Create basic template for cache compressors. A basic compressor
must implement a compression and a decompression method.

Change-Id: I83dc4d2b8d2bc5ed9f760c938edfa4ebdd6b8583
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11100
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A DSConscript13944:5000533e6b81 Wed Jun 13 10:39:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Create BDI Compressor

Implement Base-Delta-Immediate compression, as described in
'Base-Delta-Immediate Compression: Practical Data Compression
for On-Chip Caches'

Change-Id: I7980c340ab53a086b748f4b2108de4adc775fac8
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11412
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
13942:e8b59b523af6 Wed Jun 13 08:36:00 EDT 2018 Daniel R. Carvalho <odanrc@yahoo.com.br> mem-cache: Create cache compressor

Create basic template for cache compressors. A basic compressor
must implement a compression and a decompression method.

Change-Id: I83dc4d2b8d2bc5ed9f760c938edfa4ebdd6b8583
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/11100
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/ext/testlib/
H A Dfixture.py13790:ed7f0a384c22 Wed Mar 13 13:32:00 EDT 2019 Jason Lowe-Power <jason@lowepower.com> tests,ext: Add skip_cleanup implementation for TempdirFixture

Change-Id: Idc5ec9309a4ef3c0ad0c7e8b2df47294acc97ec4
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17451
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
13790:ed7f0a384c22 Wed Mar 13 13:32:00 EDT 2019 Jason Lowe-Power <jason@lowepower.com> tests,ext: Add skip_cleanup implementation for TempdirFixture

Change-Id: Idc5ec9309a4ef3c0ad0c7e8b2df47294acc97ec4
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17451
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/mem/ruby/common/
H A DDataBlock.hh6355:79464d8a4d2f Mon Jul 13 18:22:00 EDT 2009 pdudnik@gmail.com 1. Got rid of unused functions in DirectoryMemory
2. Reintroduced RMW_Read and RMW_Write
3. Defined -2 in the Sequencer as well as made a note about mandatory queue

Did not address the issues in the slicc because remaking the atomics altogether to allow
multiple processors to issue atomic requests at once
6351:31d19bdd9d85 Mon Jul 13 12:59:00 EDT 2009 pdudnik@gmail.com Minor fixes for compiling
6347:a532849ca78f Mon Jul 13 12:13:00 EDT 2009 Polina pdudnik@gmail.com Reintegrated Derek's functional implementation of atomics with a minor change: don't clear lock on failure
6347:a532849ca78f Mon Jul 13 12:13:00 EDT 2009 Polina pdudnik@gmail.com Reintegrated Derek's functional implementation of atomics with a minor change: don't clear lock on failure
6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including.
This basically means changing all #include statements and changing
autogenerated code so that it generates the correct paths. Because
slicc generates #includes, I had to hard code the include paths to
mem/protocol.
6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS

We eventually plan to replace the m5 cache hierarchy with the GEMS
hierarchy, but for now we will make both live alongside eachother.
/gem5/src/arch/mips/linux/
H A Dlinux.hh11383:5ac090acd180 Thu Mar 17 13:24:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: extend mmap system call to support file backed mmaps

For O3, which has a stat that counts reg reads, there is an additional
reg read per mmap() call since there's an arg we no longer ignore.
Otherwise, stats should not be affected.
11382:654272b82e94 Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: add many Linux kernel flags
11381:516213d2f0cf Thu Mar 17 13:22:00 EDT 2016 Brandon Potter <brandon.potter@amd.com> syscall_emul: rename OpenFlagTransTable struct

The structure definition only had the open system call flag set in mind when
it was named, so we rename it here with the intention of using it to define
additional tables to translate flags for other system calls in the future.
10290:b7715fb7cf9f Tue Aug 26 10:13:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> mips: Fix RLIMIT_RSS naming

MIPS defined RLIMIT_RSS in a way that could cause a naming conflict with
RLIMIT_RSS from the host system. Broke clang+MacOS build.
6689:67d980fcbc7a Sat Oct 24 13:53:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> syscall: Addition of an ioctl command code for Power.
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/tests/long/se/10.mcf/ref/x86/linux/o3-timing/
H A Dsimout11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11388:bd4125134e77 Thu Mar 17 13:30:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap changes
11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
9449:56610ab73040 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for previous changes.
9039:9a22621c741c Mon Jun 04 13:43:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Update stats for the CPUID change.
8844:a451e4eda591 Mon Feb 13 01:30:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> bp: fix up stats for changes to branch predictor
/gem5/src/arch/x86/
H A Dx86_traits.hh9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change.
9040:cdfe09f9bdee Mon Jun 04 13:57:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.

This eliminates a use of the ExtMachInst type outside of the ISAs.
6479:b9ab1b56391b Fri Aug 07 13:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement shift right/left double microops.
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.
6479:b9ab1b56391b Fri Aug 07 13:13:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement shift right/left double microops.
This is my best guess as far as what these should do. Other existing microops
use implicit registers, mul1s and mul1u for instance, so this should be ok.
The microop that loads the implicit DoubleBits register would fall into one
of the microop slots for moving to/from special registers.
5075:4ae876c5037d Thu Sep 13 19:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Total overhaul of the division instructions and microops.
/gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/
H A Dsimout11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support

Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
9449:56610ab73040 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for previous changes.
8844:a451e4eda591 Mon Feb 13 01:30:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> bp: fix up stats for changes to branch predictor
/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/
H A Dsimout11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support

Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
9449:56610ab73040 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for previous changes.
8844:a451e4eda591 Mon Feb 13 01:30:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> bp: fix up stats for changes to branch predictor
/gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/
H A Dsimout11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support

Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
9449:56610ab73040 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for previous changes.
8844:a451e4eda591 Mon Feb 13 01:30:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> bp: fix up stats for changes to branch predictor
/gem5/tests/long/se/50.vortex/ref/arm/linux/o3-timing/
H A Dsimout11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11388:bd4125134e77 Thu Mar 17 13:30:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap changes
11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
9449:56610ab73040 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for previous changes.
8844:a451e4eda591 Mon Feb 13 01:30:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> bp: fix up stats for changes to branch predictor
/gem5/tests/quick/se/00.hello/ref/x86/linux/o3-timing/
H A Dsimout11680:b4d943429dc6 Thu Oct 13 18:21:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11384:e3cbd2823210 Thu Mar 17 13:25:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap() change.

SE O3 runs see an additional reg read per mmap() call.
9449:56610ab73040 Mon Jan 07 13:05:00 EST 2013 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for previous changes.
9039:9a22621c741c Mon Jun 04 13:43:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Update stats for the CPUID change.
8844:a451e4eda591 Mon Feb 13 01:30:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> bp: fix up stats for changes to branch predictor
/gem5/src/arch/power/
H A DSConscript9384:877293183bdf Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@arm.com> arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.
9057:f5ee56466b91 Tue Jun 05 13:52:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ISA: Back-out NoopMachInst as a StaticInstPtr change.
9040:cdfe09f9bdee Mon Jun 04 13:57:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.

This eliminates a use of the ExtMachInst type outside of the ISAs.
8792:1c0812bae427 Sun Nov 13 03:40:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Power: Add a stubbed out stacktrace.cc
7506:e76cc0ca16cc Thu Jul 22 13:47:00 EDT 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> Power: Provide a utility function to copy registers from one thread context
to another in the Power ISA.
/gem5/tests/long/se/20.parser/ref/x86/linux/simple-atomic/
H A Dsimout11390:f40859930028 Thu Mar 17 13:32:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for ld.so support

Additional auxv entries leads to more instructions in start-up
while walking the list, along with different cache conflicts
wrt stack entries.
11388:bd4125134e77 Thu Mar 17 13:30:00 EDT 2016 Steve Reinhardt <steve.reinhardt@amd.com> stats: update stats for mmap changes
9039:9a22621c741c Mon Jun 04 13:43:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Update stats for the CPUID change.
/gem5/src/sim/
H A Dinit_signals.cc12203:4fa428be5f7e Sun Sep 03 13:00:00 EDT 2017 Bjoern A. Zeeb <baz21@cam.ac.uk> sim: make compile on FreeBSD prior to 11

FreeBSD before the early 11 development is expecting a char *
for stack.ss_sp rather than the standards compliant void *.
Catch that case and allow gem5 to compile on old FreeBSD versions.

Change-Id: Ic0ae560b52bfe5b3905ae87df791d349e053ec97
Reviewed-on: https://gem5-review.googlesource.com/4660
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
11080:31ab5ca6836d Fri Sep 04 13:13:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> sim: Fix time unit in abort message
11080:31ab5ca6836d Fri Sep 04 13:13:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> sim: Fix time unit in abort message

Completed in 117 milliseconds

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