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/gem5/src/systemc/tests/systemc/kernel/phase_callbacks/test01/
H A Dtest01.cpp13158:886ca37b7665 Tue Sep 04 21:13:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Make some tests use cout instead of cerr to report completion.

cerr goes to simerr, but we compare simout against the golden output.

Change-Id: I9270866a92dd06a23d47c1964dacc4872030f30d
Reviewed-on: https://gem5-review.googlesource.com/c/12470
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/tests/systemc/kernel/phase_callbacks/test02/
H A Dtest02.cpp13158:886ca37b7665 Tue Sep 04 21:13:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Make some tests use cout instead of cerr to report completion.

cerr goes to simerr, but we compare simout against the golden output.

Change-Id: I9270866a92dd06a23d47c1964dacc4872030f30d
Reviewed-on: https://gem5-review.googlesource.com/c/12470
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/tests/systemc/kernel/sc_elab_and_sim/
H A Dsc_elab_and_sim.cpp13158:886ca37b7665 Tue Sep 04 21:13:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Make some tests use cout instead of cerr to report completion.

cerr goes to simerr, but we compare simout against the golden output.

Change-Id: I9270866a92dd06a23d47c1964dacc4872030f30d
Reviewed-on: https://gem5-review.googlesource.com/c/12470
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/tests/systemc/kernel/sc_main_main/
H A Dsc_main_main.cpp13158:886ca37b7665 Tue Sep 04 21:13:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Make some tests use cout instead of cerr to report completion.

cerr goes to simerr, but we compare simout against the golden output.

Change-Id: I9270866a92dd06a23d47c1964dacc4872030f30d
Reviewed-on: https://gem5-review.googlesource.com/c/12470
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/tests/systemc/kernel/sc_object_manager/test01/
H A Dtest01.cpp13158:886ca37b7665 Tue Sep 04 21:13:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Make some tests use cout instead of cerr to report completion.

cerr goes to simerr, but we compare simout against the golden output.

Change-Id: I9270866a92dd06a23d47c1964dacc4872030f30d
Reviewed-on: https://gem5-review.googlesource.com/c/12470
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/tests/systemc/kernel/sc_process_b/test02/
H A Dtest02.cpp13158:886ca37b7665 Tue Sep 04 21:13:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Make some tests use cout instead of cerr to report completion.

cerr goes to simerr, but we compare simout against the golden output.

Change-Id: I9270866a92dd06a23d47c1964dacc4872030f30d
Reviewed-on: https://gem5-review.googlesource.com/c/12470
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/systemc/tests/systemc/kernel/sc_start/time_overflow/
H A Dtime_overflow.cpp13158:886ca37b7665 Tue Sep 04 21:13:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Make some tests use cout instead of cerr to report completion.

cerr goes to simerr, but we compare simout against the golden output.

Change-Id: I9270866a92dd06a23d47c1964dacc4872030f30d
Reviewed-on: https://gem5-review.googlesource.com/c/12470
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/cpu/testers/traffic_gen/
H A Ddram_rot_gen.cc12804:f47e75dce5c6 Thu Apr 26 13:11:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A Dpygen.hh12813:2c023816bec9 Fri Apr 27 13:57:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Add a Python-enabled traffic generator

The current traffic generator relies on a configuration file that
describes a small machine to generate stimuli. This configuration file
is usually generated by the gem5 Python configuration. This creates an
unnecessary and fragile step.

This changeset introduces a Python-based trace module. When
instantiated, the module exposes a start method that takes an iterable
object as a parameter (e.g., a generator). The iterable object is
expected to represent a list of generators that will be run one after
the other. For example:

system.tgen = PyTrafficGen()
m5.instantiate()

def trace():
yield system.tgen.createIdle(1000)
yield system.tgen.createExit(0)

system.tgen.start(trace())

Change-Id: I58e60ca517e86c197859f4daaa67750066abdc1c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11518
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A Dlinear_gen.cc12804:f47e75dce5c6 Thu Apr 26 13:11:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A Drandom_gen.cc12804:f47e75dce5c6 Thu Apr 26 13:11:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
H A Didle_gen.cc12804:f47e75dce5c6 Thu Apr 26 13:11:00 EDT 2018 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Remove reduntant protobuf includes

Change-Id: Ic34b94b3a2ea951bc023cfce2d09ce304a602e41
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/11512
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/dev/arm/
H A Dvio_mmio.hh12740:beed0805c651 Mon Nov 07 13:21:00 EST 2016 Andreas Sandberg <andreas.sandberg@arm.com> dev-arm: Add a MMIO transport interface for VirtIO

The MMIO interface currently only supports a subset of version 0.9.5
of the VirtIO specification. It has the following known limitations:

* The queue size hint (the QUEUE_NUM register) is ignored.

* Queue alignment is assumed to be hard-coded to
VirtQueue::ALIGN_SIZE (4096 bytes).

* Only 4096 byte pages are currently supported.

Change-Id: Ifd318f5e5bddab0b6a42d8c8af9ff2fbb477f98b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2326
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
/gem5/ext/testlib/
H A Dhandlers.py13789:d7b2be2c468b Thu Mar 14 13:05:00 EDT 2019 Jason Lowe-Power <jason@lowepower.com> ext,tests: Make return code based on test results

This patch also fixes a spelling mistake.

Change-Id: I8635216e512c10913a9cda54541d7e31e0d22a40
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17450
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dresult.py13789:d7b2be2c468b Thu Mar 14 13:05:00 EDT 2019 Jason Lowe-Power <jason@lowepower.com> ext,tests: Make return code based on test results

This patch also fixes a spelling mistake.

Change-Id: I8635216e512c10913a9cda54541d7e31e0d22a40
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17450
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/arch/arm/isa/templates/
H A Dcrypto.isa13544:0b4e5446167c Sat Oct 13 02:32:00 EDT 2018 Gabe Black <gabeblack@google.com> arm: Stop using the FloatReg and FloatRegBits types.

This will let us make those types 64 bits to be in line with the other
architectures.

Change-Id: I5aef5199f4d2d5bb1558afedac5c6c92bf95c021
Reviewed-on: https://gem5-review.googlesource.com/c/13621
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
/gem5/tests/test-progs/pthread/
H A DMakefile.x8612751:05138dd753f8 Tue Feb 13 09:15:00 EST 2018 Tuan Ta <qtt2@cornell.edu> tests: add some pthread and std::thread unit tests

This patch adds some pthread and C++11 std::thread unit tests.

Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72
Reviewed-on: https://gem5-review.googlesource.com/8221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
H A DMakefile.riscv12751:05138dd753f8 Tue Feb 13 09:15:00 EST 2018 Tuan Ta <qtt2@cornell.edu> tests: add some pthread and std::thread unit tests

This patch adds some pthread and C++11 std::thread unit tests.

Change-Id: I9706b542e5fa927a87c6e8ae2a6330fab7bb5d72
Reviewed-on: https://gem5-review.googlesource.com/8221
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Brandon Potter <Brandon.Potter@amd.com>
/gem5/src/cpu/
H A Dutils.hh13954:2f400a5f2627 Fri Jul 07 09:13:00 EDT 2017 Giacomo Gabrielli <giacomo.gabrielli@arm.com> cpu,mem: Add support for partial loads/stores and wide mem. accesses

This changeset adds support for partial (or masked) loads/stores, i.e.
loads/stores that can disable accesses to individual bytes within the
target address range. In addition, this changeset extends the code to
crack memory accesses across most CPU models (TimingSimpleCPU still
TBD), so that arbitrarily wide memory accesses are supported. These
changes are required for supporting ISAs with wide vectors.

Additional authors:
- Gabor Dozsa <gabor.dozsa@arm.com>
- Tiago Muck <tiago.muck@arm.com>

Change-Id: Ibad33541c258ad72925c0b1d5abc3e5e8bf92d92
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13518
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/arch/arm/kvm/
H A DArmKvmCPU.py14212:c0575e785e98 Tue Aug 13 05:37:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> arm,kvm: Fix python imports from global namespace

Change-Id: I31bd3563c2427efd7e520f714b1ca6f480fa4e85
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20491
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
/gem5/src/arch/generic/
H A Ddebugfaults.hh10292:933dfb9d8279 Tue Aug 26 10:13:00 EDT 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> base: Replace the internal varargs stuff with C++11 constructs

We currently use our own home-baked support for type-safe variadic
functions. This is confusing and somewhat limited (e.g., cprintf only
supports a limited number of arguments). This changeset converts all
uses of our internal varargs support to use C++11 variadic macros.
9414:88fa4031a9e3 Mon Jan 07 13:05:00 EST 2013 Andreas Sandberg <Andreas.Sandberg@ARM.com> arch: Fix broken M5VarArgsFault initialization

At least gcc 4.4.3 seems to get confused by the use of func both as a
template parameter and a member variable in the M5VarArgsFault
class. This causes the value of the member variable func to be
unpredictable in M5VarArgsFault objects. This changeset renames the
template parameter to remove this ambiguity.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7965:f4c89fe1246b Sun Feb 13 20:42:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Define fault objects to carry debug messages.

These faults can panic/warn/warn_once, etc., instead of instructions doing
that themselves directly. That way, instructions can be speculatively
executed, and only if they're actually going to commit will their fault be
invoked and the panic, etc., happen.
/gem5/src/cpu/kvm/
H A Dtimer.hh9655:78c9adc85718 Mon Apr 22 13:20:00 EDT 2013 Andreas Sandberg <Andreas.Sandberg@ARM.com> kvm: Add experimental support for a perf-based execution timer

Add support for using the CPU cycle counter instead of a normal POSIX
timer to generate timed exits to gem5. This should, in theory, provide
better resolution when requesting timer signals.

The perf-based timer requires a fairly recent kernel since it requires
a working PERF_EVENT_IOC_PERIOD ioctl. This ioctl has existed in the
kernel for a long time, but it used to be completely broken due to an
inverted match when the kernel copied things from user
space. Additionally, the ioctl does not change the sample period
correctly on all kernel versions which implement it. It is currently
only known to work reliably on kernel version 3.7 and above on ARM.
9651:f551c8ad12a5 Mon Apr 22 13:20:00 EDT 2013 Andreas Sandberg <Andreas.Sandberg@ARM.com> kvm: Basic support for hardware virtualized CPUs

This changeset introduces the architecture independent parts required
to support KVM-accelerated CPUs. It introduces two new simulation
objects:

KvmVM -- The KVM VM is a component shared between all CPUs in a shared
memory domain. It is typically instantiated as a child of the
system object in the simulation hierarchy. It provides access
to KVM VM specific interfaces.

BaseKvmCPU -- Abstract base class for all KVM-based CPUs. Architecture
dependent CPU implementations inherit from this class
and implement the following methods:

* updateKvmState() -- Update the
architecture-dependent KVM state from the gem5
thread context associated with the CPU.

* updateThreadContext() -- Update the thread context
from the architecture-dependent KVM state.

* dump() -- Dump the KVM state using (optional).

In order to deliver interrupts to the guest, CPU
implementations typically override the tick() method and
check for, and deliver, interrupts prior to entering
KVM.

Hardware-virutalized CPU currently have the following limitations:
* SE mode is not supported.
* PC events are not supported.
* Timing statistics are currently very limited. The current approach
simply scales the host cycles with a user-configurable factor.
* The simulated system must not contain any caches.
* Since cycle counts are approximate, there is no way to request an
exact number of cycles (or instructions) to be executed by the CPU.
* Hardware virtualized CPUs and gem5 CPUs must not execute at the
same time in the same simulator instance.
* Only single-CPU systems can be simulated.
* Remote GDB connections to the guest system are not supported.

Additionally, m5ops requires an architecture specific interface and
might not be supported.
/gem5/src/arch/x86/isa/insts/general_purpose/input_output/
H A Dgeneral_io.py8672:2c7ece076c8b Mon Jan 09 21:13:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> X86: Add memory fence to I/O instructions
5927:5e3367b103da Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Do a merge for the zero extension microop.
H A Dstring_io.py8672:2c7ece076c8b Mon Jan 09 21:13:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> X86: Add memory fence to I/O instructions
5927:5e3367b103da Wed Feb 25 13:20:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Do a merge for the zero extension microop.
/gem5/src/arch/x86/isa/insts/general_purpose/
H A Dsystem_calls.py5908:c24a1ffc4ad0 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the sysret instruction in long mode.
5907:8a633e6a8df1 Wed Feb 25 13:17:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the longmode versions of the syscall instruction.

Completed in 55 milliseconds

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