Searched hist:12401 (Results 1 - 6 of 6) sorted by relevance
| /gem5/src/dev/arm/ | ||
| H A D | vio_mmio.cc | 12974:b840a646cfbd Thu Aug 30 11:43:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Factory SimObject for generating ArmInterruptPin With this patch the python ArmInterruptPin SimObject matches to the C++ ArmInterruptPinGen. The latter is in charge of generating the ArmInterruptPin (which is not a SimObject anymore). This is meant to ease the generation of ArmInterruptPins: by not being SimObjects we are not forced to instantiate them in the configuration script; we can generate them dynamically instead throughout simulation. Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12401 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | base_gic.cc | 12974:b840a646cfbd Thu Aug 30 11:43:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Factory SimObject for generating ArmInterruptPin With this patch the python ArmInterruptPin SimObject matches to the C++ ArmInterruptPinGen. The latter is in charge of generating the ArmInterruptPin (which is not a SimObject anymore). This is meant to ease the generation of ArmInterruptPins: by not being SimObjects we are not forced to instantiate them in the configuration script; we can generate them dynamically instead throughout simulation. Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12401 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | base_gic.hh | 12974:b840a646cfbd Thu Aug 30 11:43:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Factory SimObject for generating ArmInterruptPin With this patch the python ArmInterruptPin SimObject matches to the C++ ArmInterruptPinGen. The latter is in charge of generating the ArmInterruptPin (which is not a SimObject anymore). This is meant to ease the generation of ArmInterruptPins: by not being SimObjects we are not forced to instantiate them in the configuration script; we can generate them dynamically instead throughout simulation. Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12401 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | Gic.py | 12974:b840a646cfbd Thu Aug 30 11:43:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Factory SimObject for generating ArmInterruptPin With this patch the python ArmInterruptPin SimObject matches to the C++ ArmInterruptPinGen. The latter is in charge of generating the ArmInterruptPin (which is not a SimObject anymore). This is meant to ease the generation of ArmInterruptPins: by not being SimObjects we are not forced to instantiate them in the configuration script; we can generate them dynamically instead throughout simulation. Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12401 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/ | ||
| H A D | pmu.cc | 12974:b840a646cfbd Thu Aug 30 11:43:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Factory SimObject for generating ArmInterruptPin With this patch the python ArmInterruptPin SimObject matches to the C++ ArmInterruptPinGen. The latter is in charge of generating the ArmInterruptPin (which is not a SimObject anymore). This is meant to ease the generation of ArmInterruptPins: by not being SimObjects we are not forced to instantiate them in the configuration script; we can generate them dynamically instead throughout simulation. Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12401 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/arm/insts/ | ||
| H A D | static_inst.hh | 12401:692ba6d84f4b Tue Dec 19 13:15:00 EST 2017 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Fix StaticInst encoding() method The previously introduced method was missing the machInst value to be masked. Change-Id: Ic722f7cc2abc680da1a1f19c08299338b5c859a6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Chuan Zhu <chuan.zhu@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/6881 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
Completed in 38 milliseconds