Searched hist:10432 (Results 1 - 4 of 4) sorted by relevance
| /gem5/src/mem/ | ||
| H A D | dram_ctrl.hh | 10432:da98b90b5df0 Tue Jul 29 12:22:00 EDT 2014 Omar Naji <Omar.Naji@arm.com> mem: DRAMPower integration for on-line DRAM power stats This patch takes the final step in integrating DRAMPower and adds the appropriate calls in the DRAM controller to provide the command trace and extract the power and energy stats. The debug printouts are still left in place, but will eventually be removed. At the moment the DRAM power calculation is always on when using the DRAM controller model. The run-time impact of this addition is around 1.5% when looking at the total host seconds of the regressions. We deem this a sensible trade-off to avoid the complication of adding an enable/disable mechanism. |
| H A D | dram_ctrl.cc | 10432:da98b90b5df0 Tue Jul 29 12:22:00 EDT 2014 Omar Naji <Omar.Naji@arm.com> mem: DRAMPower integration for on-line DRAM power stats This patch takes the final step in integrating DRAMPower and adds the appropriate calls in the DRAM controller to provide the command trace and extract the power and energy stats. The debug printouts are still left in place, but will eventually be removed. At the moment the DRAM power calculation is always on when using the DRAM controller model. The run-time impact of this addition is around 1.5% when looking at the total host seconds of the regressions. We deem this a sensible trade-off to avoid the complication of adding an enable/disable mechanism. |
| /gem5/src/mem/cache/ | ||
| H A D | cache.cc | 12725:3dcb96899659 Thu May 03 10:51:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Move cache bypass mechanism to the ports Cache bypass is necessary for cpu models like the KvmCPU. Previously the bypass would happen at the cache classes. With this change the bypassing happens directly at the ports. Change-Id: I34de9fc63383aee8590643e169501ea6060d2d62 Reviewed-on: https://gem5-review.googlesource.com/10432 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
| H A D | base.cc | 12725:3dcb96899659 Thu May 03 10:51:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Move cache bypass mechanism to the ports Cache bypass is necessary for cpu models like the KvmCPU. Previously the bypass would happen at the cache classes. With this change the bypassing happens directly at the ports. Change-Id: I34de9fc63383aee8590643e169501ea6060d2d62 Reviewed-on: https://gem5-review.googlesource.com/10432 Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
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