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Searched hist:10333 (Results 1 - 10 of 10) sorted by relevance

/gem5/src/cpu/o3/
H A D	mem_dep_unit.hh	10333:6be8945d226b Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior.
H A D	inst_queue.hh	10333:6be8945d226b Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior.
H A D	mem_dep_unit_impl.hh	10333:6be8945d226b Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior.
H A D	iew.hh	10333:6be8945d226b Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior.
H A D	lsq.hh	10333:6be8945d226b Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior.
H A D	lsq_impl.hh	10333:6be8945d226b Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior.
H A D	lsq_unit.hh	10333:6be8945d226b Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior.
H A D	inst_queue_impl.hh	10333:6be8945d226b Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior.
H A D	iew_impl.hh	10333:6be8945d226b Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior.
H A D	lsq_unit_impl.hh	10333:6be8945d226b Wed Sep 03 07:42:00 EDT 2014 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix cache blocked load behavior in o3 cpu This patch fixes the load blocked/replay mechanism in the o3 cpu. Rather than flushing the entire pipeline, this patch replays loads once the cache becomes unblocked. Additionally, deferred memory instructions (loads which had conflicting stores), when replayed would not respect the number of functional units (only respected issue width). This patch also corrects that. Improvements over 20% have been observed on a microbenchmark designed to exercise this behavior.

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