Searched defs:reg_idx (Results 1 - 12 of 12) sorted by relevance
| /gem5/src/cpu/o3/ |
| H A D | thread_context.hh | 191 readReg(RegIndex reg_idx) argument
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| H A D | regfile.cc | 138 int reg_idx = 0; local
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| H A D | dyn_inst.hh | 411 int reg_idx = idx; variable
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| H A D | thread_context_impl.hh | 265 O3ThreadContext<Impl>::setIntRegFlat(RegIndex reg_idx, RegVal val) argument
274 O3ThreadContext<Impl>::setFloatRegFlat(RegIndex reg_idx, RegVal val) argument
283 setVecRegFlat( RegIndex reg_idx, const VecRegContainer& val) argument
302 setVecPredRegFlat(RegIndex reg_idx, const VecPredRegContainer& val) argument
312 setCCRegFlat(RegIndex reg_idx, RegVal val) argument
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| H A D | regfile.hh | 179 PhysRegIdPtr getMiscRegId(RegIndex reg_idx) { argument
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| H A D | cpu.cc | 1316 FullO3CPU<Impl>::readArchIntReg(int reg_idx, ThreadID tid) argument
1327 FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid) argument
1388 readArchCCReg(int reg_idx, ThreadID tid) argument
1399 setArchIntReg(int reg_idx, RegVal val, ThreadID tid) argument
1410 setArchFloatReg(int reg_idx, RegVal val, ThreadID tid) argument
1421 setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid) argument
1431 setArchVecElem(const RegIndex& reg_idx, const ElemIndex& ldx, const VecElem& val, ThreadID tid) argument
1441 setArchVecPredReg(int reg_idx, const VecPredRegContainer& val, ThreadID tid) argument
1451 setArchCCReg(int reg_idx, RegVal val, ThreadID tid) argument
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| H A D | cpu.hh | 435 readArchVecLane(int reg_idx, int lId, ThreadID tid) const argument
446 setArchVecLane(int reg_idx, int lId, ThreadID tid, const LD& val) argument
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| /gem5/src/arch/x86/insts/ |
| H A D | static_inst.cc | 135 RegIndex reg_idx = reg.index(); local
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| /gem5/src/arch/sparc/insts/ |
| H A D | static_inst.cc | 104 RegIndex reg_idx = reg.index(); local
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| /gem5/src/arch/arm/insts/ |
| H A D | static_inst.cc | 296 ArmStaticInst::printIntReg(std::ostream &os, RegIndex reg_idx, argument
348 ArmStaticInst::printVecReg(std::ostream &os, RegIndex reg_idx, argument
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| H A D | macromem.cc | 147 unsigned reg_idx; local
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| /gem5/src/cpu/ |
| H A D | reg_class.hh | 93 RegId(RegClass reg_class, RegIndex reg_idx) argument
96 explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx) argument
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