| /gem5/src/cpu/ |
| H A D | nativetrace.cc | 48 int port = 8000; local
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| /gem5/util/tlm/src/ |
| H A D | master_transactor.cc | 57 auto* port = sim_control->getMasterPort(portName); local
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| H A D | slave_transactor.cc | 57 auto* port = sim_control->getSlavePort(portName); local
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| /gem5/src/systemc/core/ |
| H A D | sc_sensitive.cc | 114 sc_sensitive::operator () (::sc_gem5::Process *p, const sc_in<bool> &port) argument
129 sc_sensitive::operator () (::sc_gem5::Process *p, const sc_inout<bool> &port) argument
121 operator ()(::sc_gem5::Process *p, const sc_in<sc_dt::sc_logic> &port) argument
136 operator ()(::sc_gem5::Process *p, const sc_inout<sc_dt::sc_logic> &port) argument
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| H A D | port.cc | 42 Port::finalizePort(StaticSensitivityPort *port) argument
69 Port::sensitive(StaticSensitivityPort *port) argument
[all...] |
| /gem5/src/cpu/simple/ |
| H A D | noncaching.cc | 57 NonCachingSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt) argument
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| /gem5/src/mem/ |
| H A D | SimpleMemory.py | 48 port = SlavePort("Slave ports") variable in class:SimpleMemory
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| H A D | ExternalMaster.py | 48 port = MasterPort("Master port") variable in class:ExternalMaster
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| H A D | ExternalSlave.py | 45 port = SlavePort("Slave port") variable in class:ExternalSlave
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| H A D | DRAMSim2.py | 47 port = SlavePort("Slave port") variable in class:DRAMSim2
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| H A D | fs_translating_port_proxy.cc | 69 FSTranslatingPortProxy( MasterPort &port, unsigned int cacheLineSize) argument
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| H A D | se_translating_port_proxy.cc | 63 SETranslatingPortProxy::SETranslatingPortProxy(MasterPort &port, argument
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| /gem5/src/dev/serial/ |
| H A D | Terminal.py | 52 port = Param.TcpPort(3456, "listen port") variable in class:Terminal
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| /gem5/src/base/vnc/ |
| H A D | Vnc.py | 54 port = Param.TcpPort(5900, "listen port") variable in class:VncServer
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| /gem5/src/mem/qos/ |
| H A D | QoSMemSinkCtrl.py | 45 port = SlavePort("Slave ports") variable in class:QoSMemSinkCtrl
|
| /gem5/src/arch/x86/ |
| H A D | X86TLB.py | 48 port = MasterPort("Port for the hardware table walker") variable in class:X86PagetableWalker
|
| /gem5/ext/systemc/src/sysc/communication/ |
| H A D | sc_event_finder.h | 50 const sc_port_base& port() const function in class:sc_core::sc_event_finder
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| /gem5/src/base/ |
| H A D | socket.cc | 90 ListenSocket::listen(int port, bool reuse) argument
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| /gem5/src/systemc/tests/systemc/tmp/others/sc_writer_bug/ |
| H A D | sc_writer_bug.cpp | 15 sc_inout<bool> port;
member in struct:M
|
| /gem5/src/cpu/testers/directedtest/ |
| H A D | SeriesRequestGenerator.cc | 58 MasterPort* port = m_directed_tester->getCpuPort(m_active_node); local
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| H A D | InvalidateGenerator.cc | 57 MasterPort* port; local
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| /gem5/src/dev/virtio/ |
| H A D | VirtIO9P.py | 71 port = Param.String("564", "9P server port") variable in class:VirtIO9PSocket
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| /gem5/src/cpu/testers/memtest/ |
| H A D | MemTest.py | 69 port = MasterPort("Port to the memory system") variable in class:MemTest
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| /gem5/src/systemc/ |
| H A D | sc_port_wrapper.hh | 64 port() function in class:sc_gem5::ScPortWrapper
145 port() function in class:sc_gem5::ScExportWrapper
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| /gem5/util/statetrace/base/ |
| H A D | statetrace.cc | 121 int port; local
|