| /gem5/src/cpu/ |
| H A D | exetrace.hh | 50 ExeTracerRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, TheISA::PCState _pc, const StaticInstPtr _macroStaticInst = NULL) argument
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| H A D | inteltrace.hh | 48 IntelTraceRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, TheISA::PCState _pc, const StaticInstPtr _macroStaticInst = NULL) argument
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| H A D | nativetrace.hh | 56 NativeTraceRecord(NativeTrace * _parent, Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, TheISA::PCState _pc, const StaticInstPtr _macroStaticInst = NULL) argument
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| H A D | base_dyn_inst_impl.hh | 62 BaseDynInst(const StaticInstPtr &_staticInst, const StaticInstPtr &_macroop, TheISA::PCState _pc, TheISA::PCState _predPC, InstSeqNum seq_num, ImplCPU *cpu) argument
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| /gem5/src/arch/arm/tracers/ |
| H A D | tarmac_record_v8.hh | 132 TarmacTracerRecordV8(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, ArmISA::PCState _pc, TarmacTracer& _parent, const StaticInstPtr _macroStaticInst = NULL) argument
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| H A D | tarmac_base.cc | 54 TarmacBaseRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, PCState _pc, const StaticInstPtr _macroStaticInst) argument
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| H A D | tarmac_tracer.hh | 64 TarmacContext(ThreadContext* _thread, const StaticInstPtr _staticInst, ArmISA::PCState _pc) argument
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| H A D | tarmac_record.cc | 107 TarmacTracerRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, PCState _pc, TarmacTracer& _tracer, const StaticInstPtr _macroStaticInst) argument
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| H A D | tarmac_parser.cc | 758 TarmacParserRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, PCState _pc, TarmacParser& _parent, const StaticInstPtr _macroStaticInst) argument
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| H A D | tarmac_parser.hh | 95 TarmacParserRecordEvent(TarmacParser& _parent, ThreadContext *_thread, const StaticInstPtr _inst, ArmISA::PCState _pc, bool _mismatch, bool _mismatch_on_pc_or_opcode) argument
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| /gem5/src/arch/generic/ |
| H A D | types.hh | 57 Addr _pc; member in class:GenericISA::PCStateBase
120 SERIALIZE_SCALAR(_pc); variable
127 UNSERIALIZE_SCALAR(_pc); variable
328 Base::_pc = Base::_npc; member in class:GenericISA::DelaySlotPCState::Base
[all...] |
| /gem5/src/arch/alpha/ |
| H A D | faults.hh | 238 ItbFault(Addr _pc) : pc(_pc) { } argument
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| /gem5/src/mem/ruby/slicc_interface/ |
| H A D | RubyRequest.hh | 65 RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb = PrefetchBit_No, ContextID _proc_id = 100, ContextID _core_id = 99, HSAScope _scope = HSAScope_UNSPECIFIED, HSASegment _segment = HSASegment_GLOBAL) argument
87 RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb, unsigned _proc_id, unsigned _core_id, int _wm_size, std::vector<bool> & _wm_mask, DataBlock & _Data, HSAScope _scope = HSAScope_UNSPECIFIED, HSASegment _segment = HSASegment_GLOBAL) argument
114 RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb, unsigned _proc_id, unsigned _core_id, int _wm_size, std::vector<bool> & _wm_mask, DataBlock & _Data, std::vector< std::pair<int,AtomicOpFunctor*> > _atomicOps, HSAScope _scope = HSAScope_UNSPECIFIED, HSASegment _segment = HSASegment_GLOBAL) argument
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| /gem5/src/sim/ |
| H A D | insttracer.hh | 150 InstRecord(Tick _when, ThreadContext *_thread, const StaticInstPtr _staticInst, TheISA::PCState _pc, const StaticInstPtr _macroStaticInst = NULL) argument
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| /gem5/src/cpu/pred/ |
| H A D | multiperspective_perceptron.hh | 113 MPPBranchInfo(Addr _pc, int pcshift, bool cb) : pc((unsigned int)_pc), argument
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| /gem5/src/mem/ |
| H A D | request.hh | 386 Addr _pc; variable
[all...] |