arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black

ARM: Add limited CP14 support.

New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.

ARM: Add support for M5 ops in the ARM ISA

ARM: Implement all ARM SIMD instructions.

ARM: Decode the neon instruction space.

ARM: Move some case values out of ##included files.

This will help keep the high level decode together and not have it spread into
the subordinate decode stuff. The ##include lines still need to be on a line
by themselves, though.

ARM: Move the VFP data operation decode into a function.

ARM: Fix up thumb decoding of coproc instructions.

ARM: Clean up some redundancy and fault behavior for unimplemented thumb MCR, MRC.

ARM: Decode 8, 16, and 32 bit transfers between core and extension (fp) registers.

ARM: Decode the RFE instruction.

ARM: When an instruction is intentionally undefined, fault on it.

ARM: Decode the thumb32 load byte/memory hint instructions.

ARM: Decode the load halfword, memory hints instructions for 32 bit Thumb.

ARM: Decode the thumb versions of the mcr and mrc instructions.

ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.

ARM: Decode 32 bit thumb data processing register instructions.

ARM: Hook the new multiply instructions into all the decoders.

ARM: Decode plain binary immediate thumb data processing instructions.

ARM: Hook the new branch instructions into the 32 bit thumb decoder.

ARM: Hook the new branch instructions into the 16 bit thumb decoder.

ARM: Hook the external data processing instructions into the Thumb decoder.

ARM: Hook up 32 bit thumb load/store multiple.

ARM: Hook up 16 bit thumb load/store multiple.

ARM: Decode 16 bit thumb PC relative memory instructions.

ARM: Decode 16 bit thumb immediate addressed memory instructions.

ARM: Decode 16 bit thumb register addressed memory instructions.

ARM: Make single stores decode to the new external store instructions.

ARM: Make 32 bit thumb use the new, external load instructions.

ARM: Create a "decoder" directory for the files implementing the decoder.