thumb.isa revision 7136:8652cc210840
1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating 9// to a hardware implementation of the functionality of the software 10// licensed hereunder. You may use the software subject to the license 11// terms below provided that you ensure that this notice is replicated 12// unmodified and in its entirety in all distributions of the software, 13// modified or unmodified, in source code or in binary form. 14// 15// Copyright (c) 2009 The Regents of The University of Michigan 16// All rights reserved. 17// 18// Redistribution and use in source and binary forms, with or without 19// modification, are permitted provided that the following conditions are 20// met: redistributions of source code must retain the above copyright 21// notice, this list of conditions and the following disclaimer; 22// redistributions in binary form must reproduce the above copyright 23// notice, this list of conditions and the following disclaimer in the 24// documentation and/or other materials provided with the distribution; 25// neither the name of the copyright holders nor the names of its 26// contributors may be used to endorse or promote products derived from 27// this software without specific prior written permission. 28// 29// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40// 41// Authors: Gabe Black 42 431: decode BIGTHUMB { 44 // 16 bit thumb instructions. 45 0: decode TOPCODE_15_13 { 46 0x0, 0x1: decode TOPCODE_13_11 { 47 0x0: WarnUnimpl::lsl(); //immediate 48 0x1: WarnUnimpl::lsr(); //immediate 49 0x2: WarnUnimpl::asr(); //immediate 50 0x3: decode TOPCODE_10_9 { 51 0x0: WarnUnimpl::add(); //register 52 0x1: WarnUnimpl::sub(); //register 53 0x2: WarnUnimpl::add(); //3 bit immediate 54 0x3: WarnUnimpl::sub(); //3 bit immediate 55 } 56 0x4: WarnUnimpl::mov(); //immediate 57 0x5: WarnUnimpl::cmp(); //immediate 58 0x6: WarnUnimpl::add(); //8 bit immediate, thumb 59 0x7: WarnUnimpl::sub(); //8 bit immediate, thumb 60 } 61 0x2: decode TOPCODE_12_10 { 62 // Data processing 63 0x0: decode TOPCODE_9_6 { 64 0x0: WarnUnimpl::and(); //register 65 0x1: WarnUnimpl::eor(); //register 66 0x2: WarnUnimpl::lsl(); //register 67 0x3: WarnUnimpl::lsr(); //register 68 0x4: WarnUnimpl::asr(); //register 69 0x5: WarnUnimpl::adc(); //register 70 0x6: WarnUnimpl::sbc(); //register 71 0x7: WarnUnimpl::ror(); //register 72 0x8: WarnUnimpl::tst(); //register 73 0x9: WarnUnimpl::rsb(); //immediate 74 0xa: WarnUnimpl::cmp(); //register (high registers) 75 0xb: WarnUnimpl::cmn(); //register 76 0xc: WarnUnimpl::orr(); //register 77 0xd: WarnUnimpl::mul(); 78 0xe: WarnUnimpl::bic(); //register 79 0xf: WarnUnimpl::mvn(); //register 80 } 81 // Special data instructions and branch and exchange 82 0x1: decode TOPCODE_9_6 { 83 0x0: WarnUnimpl::add(); //register (low registers) 84 0x1, 0x2, 0x3: WarnUnimpl::add(); //register (high registers) 85 0x4: WarnUnimpl::unpredictable(); //? 86 0x5, 0x6, 0x7: WarnUnimpl::cmp(); //register 87 0x8: WarnUnimpl::mov(); //register (low registers) 88 0x9, 0xa, 0xb: WarnUnimpl::mov(); //register (high registers) 89 0xc, 0xd: WarnUnimpl::bx(); 90 0xe, 0xf: WarnUnimpl::blx(); //register 91 } 92 0x2, 0x3: Thumb16MemLit::thumb16MemLit(); 93 default: Thumb16MemReg::thumb16MemReg(); 94 } 95 0x3, 0x4: Thumb16MemImm::thumb16MemImm(); 96 0x5: decode TOPCODE_12_11 { 97 0x0: WarnUnimpl::adr(); 98 0x1: WarnUnimpl::add(); //sp, immediate 99 0x2: decode TOPCODE_10_8 { 100 0x0: decode TOPCODE_7 { 101 0x0: WarnUnimpl::add(); //sp, immediate 102 0x1: WarnUnimpl::sub(); //sp, immediate 103 } 104 0x1, 0x3: WarnUnimpl::cbz(); //cbnz too... 105 0x2: decode TOPCODE_7_6 { 106 0x0: WarnUnimpl::sxth(); 107 0x1: WarnUnimpl::sxtb(); 108 0x2: WarnUnimpl::uxth(); 109 0x3: WarnUnimpl::uxtb(); 110 } 111 0x4, 0x5: WarnUnimpl::pop(); 112 0x6: decode TOPCODE_7_5 { 113 0x2: WarnUnimpl::setend(); 114 0x3: WarnUnimpl::cps(); 115 } 116 } 117 0x3: decode TOPCODE_10_8 { 118 0x1, 0x3: WarnUnimpl::cbz(); //cbnz too... 119 0x2: decode TOPCODE_7_6 { 120 0x0: WarnUnimpl::rev(); 121 0x1: WarnUnimpl::rev16(); 122 0x3: WarnUnimpl::revsh(); 123 } 124 0x4, 0x5: WarnUnimpl::pop(); 125 0x6: WarnUnimpl::bkpt(); 126 0x7: decode TOPCODE_3_0 { 127 0x0: WarnUnimpl::it(); 128 default: decode TOPCODE_7_4 { 129 0x0: WarnUnimpl::nop(); 130 0x1: WarnUnimpl::yield(); 131 0x2: WarnUnimpl::wfe(); 132 0x3: WarnUnimpl::wfi(); 133 0x4: WarnUnimpl::sev(); 134 default: WarnUnimpl::unallocated_hint(); 135 } 136 } 137 } 138 } 139 0x6: decode TOPCODE_12_11 { 140 0x0, 0x1: Thumb16MacroMem::thumb16MacroMem(); 141 default: decode TOPCODE_11_8 { 142 0xe: WarnUnimpl::undefined(); // permanently undefined 143 0xf: WarnUnimpl::svc(); // formerly swi 144 default: WarnUnimpl::b(); // conditional 145 } 146 } 147 0x7: decode TOPCODE_12_11 { 148 0x0: WarnUnimpl::b(); // unconditional 149 } 150 } 151 152 // 32 bit thumb instructions. 153 1: decode HTOPCODE_12_11 { 154 0x1: decode HTOPCODE_10_9 { 155 0x0: decode HTOPCODE_8_6 { 156 0x0, 0x6: decode HTOPCODE_4 { 157 0x0: WarnUnimpl::srs(); 158 0x1: WarnUnimpl::rfe(); 159 } 160 0x1: decode HTOPCODE_5_4 { 161 0x0: WarnUnimpl::strex(); 162 0x1: WarnUnimpl::ldrex(); 163 0x2: WarnUnimpl::strd(); // immediate 164 0x3: decode HTRN { 165 0xf: WarnUnimpl::ldrd(); // literal 166 default: WarnUnimpl::ldrd(); // immediate 167 } 168 } 169 // This uses the same encoding as regular ARM. 170 0x2: ArmMacroMem::armMacroMem(); 171 0x3: decode HTOPCODE_5_4 { 172 0x0: decode LTOPCODE_7_4 { 173 0x4: WarnUnimpl::strexb(); 174 0x5: WarnUnimpl::strexh(); 175 0x7: WarnUnimpl::strexd(); 176 } 177 0x1: decode LTOPCODE_7_4 { 178 0x0: WarnUnimpl::tbb(); 179 0x1: WarnUnimpl::tbh(); 180 0x4: WarnUnimpl::ldrexb(); 181 0x5: WarnUnimpl::ldrexh(); 182 0x7: WarnUnimpl::ldrexd(); 183 } 184 0x2: WarnUnimpl::strd(); // immediate 185 0x3: decode HTRN { 186 0xf: WarnUnimpl::ldrd(); // literal 187 default: WarnUnimpl::ldrd(); // immediate 188 } 189 } 190 // This uses the same encoding as regular ARM. 191 0x4: ArmMacroMem::armMacroMem(); 192 0x5, 0x7: decode HTOPCODE_4 { 193 0x0: WarnUnimpl::strd(); // immediate 194 0x1: decode HTRN { 195 0xf: WarnUnimpl::ldrd(); // literal 196 default: WarnUnimpl::ldrd(); // immediate 197 } 198 } 199 } 200 0x1: decode HTOPCODE_8_5 { 201 0x0: decode LTRD { 202 0xf: decode HTS { 203 0x1: WarnUnimpl::tst(); // register 204 } 205 default: WarnUnimpl::and(); // register 206 } 207 0x1: WarnUnimpl::bic(); // register 208 0x2: decode HTRN { 209 0xf: WarnUnimpl::mov(); // register 210 default: WarnUnimpl::orr(); // register 211 } 212 0x3: decode HTRN { 213 0xf: WarnUnimpl::mvn(); // register 214 default: WarnUnimpl::orn(); // register 215 } 216 0x4: decode LTRD { 217 0xf: decode HTS { 218 0x1: WarnUnimpl::teq(); // register 219 } 220 default: WarnUnimpl::eor(); // register 221 } 222 0x6: WarnUnimpl::pkh(); 223 0x8: decode LTRD { 224 0xf: decode HTS { 225 0x1: WarnUnimpl::cmn(); // register 226 } 227 default: WarnUnimpl::add(); // register 228 } 229 0xa: WarnUnimpl::adc(); // register 230 0xb: WarnUnimpl::sbc(); // register 231 0xd: decode LTRD { 232 0xf: decode HTS { 233 0x1: WarnUnimpl::cmp(); // register 234 } 235 default: WarnUnimpl::sub(); // register 236 } 237 0xe: WarnUnimpl::rsb(); // register 238 } 239 default: decode HTOPCODE_9_8 { 240 0x2: decode LTOPCODE_4 { 241 0x0: decode LTCOPROC { 242 0xa, 0xb: decode OPCODE_23_20 { 243##include "vfp.isa" 244 } 245 default: WarnUnimpl::cdp(); // cdp2 246 } 247 0x1: decode LTCOPROC { 248 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); 249 default: decode HTOPCODE_4 { 250 0x0: WarnUnimpl::mcr(); // mcr2 251 0x1: WarnUnimpl::mrc(); // mrc2 252 } 253 } 254 } 255 0x3: WarnUnimpl::Advanced_SIMD(); 256 default: decode LTCOPROC { 257 0xa, 0xb: decode HTOPCODE_9_4 { 258 0x00: WarnUnimpl::undefined(); 259 0x04: WarnUnimpl::mcrr(); // mcrr2 260 0x05: WarnUnimpl::mrrc(); // mrrc2 261 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 262 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e: 263 WarnUnimpl::stc(); // stc2 264 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11, 265 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f: 266 decode HTRN { 267 0xf: WarnUnimpl::ldc(); // ldc2 (literal) 268 default: WarnUnimpl::ldc(); // ldc2 (immediate) 269 } 270 } 271 default: decode HTOPCODE_9_5 { 272 0x00: WarnUnimpl::undefined(); 273 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 274 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 275 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: 276 WarnUnimpl::Extension_register_load_store_instruction(); 277 } 278 } 279 } 280 } 281 0x2: decode LTOPCODE_15 { 282 0x0: decode HTOPCODE_9 { 283 0x0: decode HTOPCODE_8_5 { 284 0x0: decode LTRD { 285 0xf: decode HTS { 286 0x1: DataModImmOp::tst({{ 287 resTemp = Rn & rotated_imm; 288 }}); 289 } 290 default: DataModImmOp::and({{ 291 Rs = resTemp = Rn & rotated_imm; 292 }}); 293 } 294 0x1: DataModImmOp::bic({{ 295 Rs = resTemp = Rn & ~rotated_imm; 296 }}); 297 0x2: decode HTRN { 298 0xf: DataModImmOp::mov({{ 299 Rs = resTemp = rotated_imm; 300 }}); 301 default: DataModImmOp::orr({{ 302 Rs = resTemp = Rn | rotated_imm; 303 }}); 304 } 305 0x3: decode HTRN { 306 0xf: DataModImmOp::mvn({{ 307 Rs = resTemp = ~rotated_imm; 308 }}); 309 default: DataModImmOp::orn({{ 310 Rs = resTemp = Rn | ~rotated_imm; 311 }}); 312 } 313 0x4: decode LTRD { 314 0xf: decode HTS { 315 0x1: DataModImmOp::teq({{ 316 resTemp = Rn ^ rotated_imm; 317 }}); 318 } 319 default: DataModImmOp::eor({{ 320 Rs = resTemp = Rn ^ rotated_imm; 321 }}); 322 } 323 0x8: decode LTRD { 324 0xf: decode HTS { 325 0x1: DataModImmOp::cmn({{ 326 resTemp = Rn + rotated_imm; 327 }}, add); 328 } 329 default: DataModImmOp::add({{ 330 Rs = resTemp = Rn + rotated_imm; 331 }}, add); 332 } 333 0xa: DataModImmOp::adc({{ 334 Rs = resTemp = Rn + rotated_imm + CondCodes<29:>; 335 }}, add); 336 0xb: DataModImmOp::sbc({{ 337 Rs = resTemp = Rn - rotated_imm - !CondCodes<29:>; 338 }}, sub); 339 0xd: decode LTRD { 340 0xf: decode HTS { 341 0x1: DataModImmOp::cmp({{ 342 resTemp = Rn - rotated_imm; 343 }}, sub); 344 } 345 default: DataModImmOp::sub({{ 346 Rs = resTemp = Rn - rotated_imm; 347 }}, sub); 348 } 349 0xe: DataModImmOp::rsb({{ 350 Rs = resTemp = rotated_imm - Rn; 351 }}, rsb); 352 } 353 0x1: WarnUnimpl::Data_processing_plain_binary_immediate(); 354 } 355 0x1: WarnUnimpl::Branches_and_miscellaneous_control(); 356 } 357 0x3: decode HTOPCODE_10_9 { 358 0x0: decode HTOPCODE_4 { 359 0x0: decode HTOPCODE_8 { 360 0x0: Thumb32StoreSingle::thumb32StoreSingle(); 361 0x1: WarnUnimpl::Advanced_SIMD_or_structure_load_store(); 362 } 363 0x1: decode HTOPCODE_6_5 { 364 0x0: WarnUnimpl::Load_byte_memory_hints(); 365 0x1: WarnUnimpl::Load_halfword_memory_hints(); 366 0x2: Thumb32LoadWord::thumb32LoadWord(); 367 0x3: WarnUnimpl::undefined(); 368 } 369 } 370 0x1: decode HTOPCODE_8_7 { 371 0x2: WarnUnimpl::Multiply_multiply_accumulate_and_absolute_difference(); 372 0x3: WarnUnimpl::Long_multiply_long_multiply_accumulate_and_divide(); 373 default: WarnUnimpl::Data_processing_register(); 374 } 375 default: decode HTOPCODE_9_8 { 376 0x2: decode LTOPCODE_4 { 377 0x0: decode LTCOPROC { 378 0xa, 0xb: WarnUnimpl::VFP_Inst(); 379 default: WarnUnimpl::cdp(); // cdp2 380 } 381 0x1: decode LTCOPROC { 382 0xa, 0xb: WarnUnimpl::Core_to_extension_transfer(); 383 default: decode HTOPCODE_4 { 384 0x0: WarnUnimpl::mcr(); // mcr2 385 0x1: WarnUnimpl::mrc(); // mrc2 386 } 387 } 388 } 389 0x3: WarnUnimpl::Advanced_SIMD(); 390 default: decode LTCOPROC { 391 0xa, 0xb: decode HTOPCODE_9_4 { 392 0x00: WarnUnimpl::undefined(); 393 0x04: WarnUnimpl::mcrr(); // mcrr2 394 0x05: WarnUnimpl::mrrc(); // mrrc2 395 0x02, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 396 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e: 397 WarnUnimpl::stc(); // stc2 398 0x03, 0x07, 0x09, 0x0b, 0x0d, 0x0f, 0x11, 399 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d, 0x1f: 400 decode HTRN { 401 0xf: WarnUnimpl::ldc(); // ldc2 (literal) 402 default: WarnUnimpl::ldc(); // ldc2 (immediate) 403 } 404 } 405 default: decode HTOPCODE_9_5 { 406 0x00: WarnUnimpl::undefined(); 407 0x02: WarnUnimpl::SIMD_VFP_64_bit_core_extension_transfer(); 408 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 409 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f: 410 WarnUnimpl::Extension_register_load_store_instruction(); 411 } 412 } 413 } 414 } 415 } 416} 417