stats.txt revision 11570
111507SCurtis.Dunham@arm.com 211507SCurtis.Dunham@arm.com---------- Begin Simulation Statistics ---------- 311570SCurtis.Dunham@arm.comsim_seconds 0.512589 # Number of seconds simulated 411570SCurtis.Dunham@arm.comsim_ticks 512588680500 # Number of ticks simulated 511570SCurtis.Dunham@arm.comfinal_tick 512588680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 611507SCurtis.Dunham@arm.comsim_freq 1000000000000 # Frequency of simulated ticks 711570SCurtis.Dunham@arm.comhost_inst_rate 180394 # Simulator instruction rate (inst/s) 811570SCurtis.Dunham@arm.comhost_op_rate 222088 # Simulator op (including micro ops) rate (op/s) 911570SCurtis.Dunham@arm.comhost_tick_rate 144333179 # Simulator tick rate (ticks/s) 1011570SCurtis.Dunham@arm.comhost_mem_usage 275860 # Number of bytes of host memory used 1111570SCurtis.Dunham@arm.comhost_seconds 3551.43 # Real time elapsed on the host 1211507SCurtis.Dunham@arm.comsim_insts 640655085 # Number of instructions simulated 1311507SCurtis.Dunham@arm.comsim_ops 788730744 # Number of ops (including micro ops) simulated 1411507SCurtis.Dunham@arm.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1511507SCurtis.Dunham@arm.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611570SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 1711570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory 1811570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::cpu.data 18474048 # Number of bytes read from this memory 1911570SCurtis.Dunham@arm.comsystem.physmem.bytes_read::total 18638208 # Number of bytes read from this memory 2011570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory 2111570SCurtis.Dunham@arm.comsystem.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory 2211507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 2311507SCurtis.Dunham@arm.comsystem.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 2411570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory 2511570SCurtis.Dunham@arm.comsystem.physmem.num_reads::cpu.data 288657 # Number of read requests responded to by this memory 2611570SCurtis.Dunham@arm.comsystem.physmem.num_reads::total 291222 # Number of read requests responded to by this memory 2711507SCurtis.Dunham@arm.comsystem.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 2811507SCurtis.Dunham@arm.comsystem.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 2911570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.inst 320257 # Total read bandwidth from this memory (bytes/s) 3011570SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 36040687 # Total read bandwidth from this memory (bytes/s) 3111570SCurtis.Dunham@arm.comsystem.physmem.bw_read::total 36360943 # Total read bandwidth from this memory (bytes/s) 3211570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::cpu.inst 320257 # Instruction read bandwidth from this memory (bytes/s) 3311570SCurtis.Dunham@arm.comsystem.physmem.bw_inst_read::total 320257 # Instruction read bandwidth from this memory (bytes/s) 3411570SCurtis.Dunham@arm.comsystem.physmem.bw_write::writebacks 8252761 # Write bandwidth from this memory (bytes/s) 3511570SCurtis.Dunham@arm.comsystem.physmem.bw_write::total 8252761 # Write bandwidth from this memory (bytes/s) 3611570SCurtis.Dunham@arm.comsystem.physmem.bw_total::writebacks 8252761 # Total bandwidth to/from this memory (bytes/s) 3711570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.inst 320257 # Total bandwidth to/from this memory (bytes/s) 3811570SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 36040687 # Total bandwidth to/from this memory (bytes/s) 3911570SCurtis.Dunham@arm.comsystem.physmem.bw_total::total 44613705 # Total bandwidth to/from this memory (bytes/s) 4011570SCurtis.Dunham@arm.comsystem.physmem.readReqs 291222 # Number of read requests accepted 4111507SCurtis.Dunham@arm.comsystem.physmem.writeReqs 66098 # Number of write requests accepted 4211570SCurtis.Dunham@arm.comsystem.physmem.readBursts 291222 # Number of DRAM read bursts, including those serviced by the write queue 4311507SCurtis.Dunham@arm.comsystem.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue 4411570SCurtis.Dunham@arm.comsystem.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM 4511570SCurtis.Dunham@arm.comsystem.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue 4611507SCurtis.Dunham@arm.comsystem.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM 4711570SCurtis.Dunham@arm.comsystem.physmem.bytesReadSys 18638208 # Total read bytes from the system interface side 4811507SCurtis.Dunham@arm.comsystem.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side 4911570SCurtis.Dunham@arm.comsystem.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue 5011507SCurtis.Dunham@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 5111507SCurtis.Dunham@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 5211570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 18288 # Per bank write bursts 5311570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::1 18133 # Per bank write bursts 5411570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::2 18220 # Per bank write bursts 5511507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::3 18178 # Per bank write bursts 5611570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::4 18281 # Per bank write bursts 5711570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::5 18410 # Per bank write bursts 5811570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::6 18174 # Per bank write bursts 5911570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::7 17993 # Per bank write bursts 6011570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::8 18029 # Per bank write bursts 6111570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::9 18057 # Per bank write bursts 6211570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::10 18103 # Per bank write bursts 6311570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::11 18205 # Per bank write bursts 6411570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::12 18223 # Per bank write bursts 6511570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::13 18272 # Per bank write bursts 6611507SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::14 18077 # Per bank write bursts 6711570SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::15 18257 # Per bank write bursts 6811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::0 4171 # Per bank write bursts 6911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::1 4099 # Per bank write bursts 7011570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::2 4135 # Per bank write bursts 7111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::3 4146 # Per bank write bursts 7211570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::4 4223 # Per bank write bursts 7311570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::5 4222 # Per bank write bursts 7411507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::6 4173 # Per bank write bursts 7511507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::7 4094 # Per bank write bursts 7611507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::8 4096 # Per bank write bursts 7711507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::9 4096 # Per bank write bursts 7811507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::10 4096 # Per bank write bursts 7911507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::11 4097 # Per bank write bursts 8011570SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::12 4098 # Per bank write bursts 8111507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::13 4096 # Per bank write bursts 8211507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::14 4096 # Per bank write bursts 8311507SCurtis.Dunham@arm.comsystem.physmem.perBankWrBursts::15 4138 # Per bank write bursts 8411507SCurtis.Dunham@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 8511507SCurtis.Dunham@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 8611570SCurtis.Dunham@arm.comsystem.physmem.totGap 512588586500 # Total gap between requests 8711507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 8811507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 8911507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 9011507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 9111507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 9211507SCurtis.Dunham@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 9311570SCurtis.Dunham@arm.comsystem.physmem.readPktSize::6 291222 # Read request sizes (log2) 9411507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 9511507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 9611507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 9711507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 9811507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 9911507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 10011507SCurtis.Dunham@arm.comsystem.physmem.writePktSize::6 66098 # Write request sizes (log2) 10111570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 290535 # What read queue length does an incoming req see 10211570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see 10311570SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see 10411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 10511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 10611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 10711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 10811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 10911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 11011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 11111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 11211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 11311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 11411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 11511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 11611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 11711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 11811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 11911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 12011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 12111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 12211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 12311507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 12411507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 12511507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 12611507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 12711507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 12811507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 12911507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 13011507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 13111507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 13211507SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 13311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 13411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 13511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 13611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 13711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 13811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 13911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 14011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 14111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 14211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 14311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 14411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 14511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 14611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 14711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 14811570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::15 910 # What write queue length does an incoming req see 14911570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::16 910 # What write queue length does an incoming req see 15011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see 15111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see 15211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::19 4017 # What write queue length does an incoming req see 15311570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::20 4017 # What write queue length does an incoming req see 15411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::21 4017 # What write queue length does an incoming req see 15511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see 15611570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see 15711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see 15811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see 15911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see 16011570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see 16111570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::28 4016 # What write queue length does an incoming req see 16211570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see 16311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see 16411570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::31 4016 # What write queue length does an incoming req see 16511570SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::32 4016 # What write queue length does an incoming req see 16611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 17011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 17111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 17211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 17311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 17411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 17511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 17611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 18011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 18111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 18211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 18311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 18411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 18511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 18611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18711507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18811507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18911507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 19011507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 19111507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 19211507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 19311507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 19411507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 19511507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 19611507SCurtis.Dunham@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19711570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 110334 # Bytes accessed per row activation 19811570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::mean 207.049577 # Bytes accessed per row activation 19911570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::gmean 134.865332 # Bytes accessed per row activation 20011570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::stdev 256.872236 # Bytes accessed per row activation 20111570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 45104 40.88% 40.88% # Bytes accessed per row activation 20211570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 43590 39.51% 80.39% # Bytes accessed per row activation 20311570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 9238 8.37% 88.76% # Bytes accessed per row activation 20411570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 1655 1.50% 90.26% # Bytes accessed per row activation 20511570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 896 0.81% 91.07% # Bytes accessed per row activation 20611570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 605 0.55% 91.62% # Bytes accessed per row activation 20711570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 780 0.71% 92.33% # Bytes accessed per row activation 20811570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 416 0.38% 92.70% # Bytes accessed per row activation 20911570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 8050 7.30% 100.00% # Bytes accessed per row activation 21011570SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 110334 # Bytes accessed per row activation 21111570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::samples 4016 # Reads before turning the bus around for writes 21211570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::mean 48.533367 # Reads before turning the bus around for writes 21311570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::gmean 34.247557 # Reads before turning the bus around for writes 21411570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::stdev 506.662918 # Reads before turning the bus around for writes 21511570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::0-1023 4014 99.95% 99.95% # Reads before turning the bus around for writes 21611507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 21711507SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 21811570SCurtis.Dunham@arm.comsystem.physmem.rdPerTurnAround::total 4016 # Reads before turning the bus around for writes 21911570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::samples 4016 # Writes before turning the bus around for reads 22011570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::mean 16.453187 # Writes before turning the bus around for reads 22111570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::gmean 16.432732 # Writes before turning the bus around for reads 22211570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::stdev 0.838251 # Writes before turning the bus around for reads 22311570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::16 3107 77.37% 77.37% # Writes before turning the bus around for reads 22411570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::18 907 22.58% 99.95% # Writes before turning the bus around for reads 22511570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads 22611570SCurtis.Dunham@arm.comsystem.physmem.wrPerTurnAround::total 4016 # Writes before turning the bus around for reads 22711570SCurtis.Dunham@arm.comsystem.physmem.totQLat 2758807250 # Total ticks spent queuing 22811570SCurtis.Dunham@arm.comsystem.physmem.totMemAccLat 8213182250 # Total ticks spent from burst creation until serviced by the DRAM 22911570SCurtis.Dunham@arm.comsystem.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers 23011570SCurtis.Dunham@arm.comsystem.physmem.avgQLat 9483.70 # Average queueing delay per DRAM burst 23111507SCurtis.Dunham@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 23211570SCurtis.Dunham@arm.comsystem.physmem.avgMemAccLat 28233.70 # Average memory access latency per DRAM burst 23311570SCurtis.Dunham@arm.comsystem.physmem.avgRdBW 36.32 # Average DRAM read bandwidth in MiByte/s 23411570SCurtis.Dunham@arm.comsystem.physmem.avgWrBW 8.25 # Average achieved write bandwidth in MiByte/s 23511570SCurtis.Dunham@arm.comsystem.physmem.avgRdBWSys 36.36 # Average system read bandwidth in MiByte/s 23611570SCurtis.Dunham@arm.comsystem.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s 23711507SCurtis.Dunham@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 23811570SCurtis.Dunham@arm.comsystem.physmem.busUtil 0.35 # Data bus utilization in percentage 23911570SCurtis.Dunham@arm.comsystem.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads 24011570SCurtis.Dunham@arm.comsystem.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 24111507SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 24211570SCurtis.Dunham@arm.comsystem.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing 24311570SCurtis.Dunham@arm.comsystem.physmem.readRowHits 195021 # Number of row buffer hits during reads 24411570SCurtis.Dunham@arm.comsystem.physmem.writeRowHits 51610 # Number of row buffer hits during writes 24511570SCurtis.Dunham@arm.comsystem.physmem.readRowHitRate 67.04 # Row buffer hit rate for reads 24611570SCurtis.Dunham@arm.comsystem.physmem.writeRowHitRate 78.08 # Row buffer hit rate for writes 24711570SCurtis.Dunham@arm.comsystem.physmem.avgGap 1434536.51 # Average gap between requests 24811570SCurtis.Dunham@arm.comsystem.physmem.pageHitRate 69.08 # Row buffer hit rate, read and write combined 24911570SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 417312000 # Energy for activate commands per rank (pJ) 25011570SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 227700000 # Energy for precharge commands per rank (pJ) 25111570SCurtis.Dunham@arm.comsystem.physmem_0.readEnergy 1136202600 # Energy for read commands per rank (pJ) 25211570SCurtis.Dunham@arm.comsystem.physmem_0.writeEnergy 215544240 # Energy for write commands per rank (pJ) 25311570SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ) 25411570SCurtis.Dunham@arm.comsystem.physmem_0.actBackEnergy 103911193800 # Energy for active background per rank (pJ) 25511570SCurtis.Dunham@arm.comsystem.physmem_0.preBackEnergy 216400632000 # Energy for precharge background per rank (pJ) 25611570SCurtis.Dunham@arm.comsystem.physmem_0.totalEnergy 355788106560 # Total energy per rank (pJ) 25711570SCurtis.Dunham@arm.comsystem.physmem_0.averagePower 694.106023 # Core power per rank (mW) 25811570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 359300376000 # Time in different power states 25911570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 17116320000 # Time in different power states 26011507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 26111570SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT 136167987750 # Time in different power states 26211507SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 26311570SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 416737440 # Energy for activate commands per rank (pJ) 26411570SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 227386500 # Energy for precharge commands per rank (pJ) 26511570SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 1132435200 # Energy for read commands per rank (pJ) 26611570SCurtis.Dunham@arm.comsystem.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ) 26711570SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ) 26811570SCurtis.Dunham@arm.comsystem.physmem_1.actBackEnergy 103626578835 # Energy for active background per rank (pJ) 26911570SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 216650294250 # Energy for precharge background per rank (pJ) 27011570SCurtis.Dunham@arm.comsystem.physmem_1.totalEnergy 355745582385 # Total energy per rank (pJ) 27111570SCurtis.Dunham@arm.comsystem.physmem_1.averagePower 694.023062 # Core power per rank (mW) 27211570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 359717078250 # Time in different power states 27311570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 17116320000 # Time in different power states 27411507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 27511570SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT 135751825750 # Time in different power states 27611507SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 27711570SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 27811570SCurtis.Dunham@arm.comsystem.cpu.branchPred.lookups 147261658 # Number of BP lookups 27911570SCurtis.Dunham@arm.comsystem.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted 28011570SCurtis.Dunham@arm.comsystem.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect 28111570SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBLookups 89949366 # Number of BTB lookups 28211570SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHits 63294628 # Number of BTB hits 28311507SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 28411570SCurtis.Dunham@arm.comsystem.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage 28511570SCurtis.Dunham@arm.comsystem.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target. 28611570SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 1312 # Number of incorrect RAS predictions. 28711570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectLookups 15995155 # Number of indirect predictor lookups. 28811570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 15988941 # Number of indirect target hits. 28911570SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. 29011570SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. 29111507SCurtis.Dunham@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 29211570SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 29311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 29411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 29511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 29611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 29711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 29811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 29911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 30011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 30111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 30211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 30311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 30411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 30511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 30611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 30711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 30811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 30911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 31011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 31111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 31211507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 31311507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 31411507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 31511507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 31611507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 31711507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 31811507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 31911507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 32011507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 32111507SCurtis.Dunham@arm.comsystem.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 32211570SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 32311507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walks 0 # Table walker walks requested 32411507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 32511507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 32611507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 32711507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 32811507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 32911507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 33011507SCurtis.Dunham@arm.comsystem.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 33111507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_hits 0 # ITB inst hits 33211507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_misses 0 # ITB inst misses 33311507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_hits 0 # DTB read hits 33411507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 0 # DTB read misses 33511507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_hits 0 # DTB write hits 33611507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_misses 0 # DTB write misses 33711507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 33811507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 33911507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 34011507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 34111507SCurtis.Dunham@arm.comsystem.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 34211507SCurtis.Dunham@arm.comsystem.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 34311507SCurtis.Dunham@arm.comsystem.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 34411507SCurtis.Dunham@arm.comsystem.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 34511507SCurtis.Dunham@arm.comsystem.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 34611507SCurtis.Dunham@arm.comsystem.cpu.dtb.read_accesses 0 # DTB read accesses 34711507SCurtis.Dunham@arm.comsystem.cpu.dtb.write_accesses 0 # DTB write accesses 34811507SCurtis.Dunham@arm.comsystem.cpu.dtb.inst_accesses 0 # ITB inst accesses 34911507SCurtis.Dunham@arm.comsystem.cpu.dtb.hits 0 # DTB hits 35011507SCurtis.Dunham@arm.comsystem.cpu.dtb.misses 0 # DTB misses 35111507SCurtis.Dunham@arm.comsystem.cpu.dtb.accesses 0 # DTB accesses 35211570SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 35311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 35411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 35611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 35711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 35811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 35911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 36011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 36111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 36211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 36311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 36411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 36511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 36611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 36711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 36811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 36911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 37011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 37111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 37211507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 37311507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 37411507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 37511507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 37611507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 37711507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 37811507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 37911507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 38011507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 38111507SCurtis.Dunham@arm.comsystem.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 38211570SCurtis.Dunham@arm.comsystem.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 38311507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walks 0 # Table walker walks requested 38411507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38511507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 38611507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 38711507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38811507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 38911507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39011507SCurtis.Dunham@arm.comsystem.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39111507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_hits 0 # ITB inst hits 39211507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_misses 0 # ITB inst misses 39311507SCurtis.Dunham@arm.comsystem.cpu.itb.read_hits 0 # DTB read hits 39411507SCurtis.Dunham@arm.comsystem.cpu.itb.read_misses 0 # DTB read misses 39511507SCurtis.Dunham@arm.comsystem.cpu.itb.write_hits 0 # DTB write hits 39611507SCurtis.Dunham@arm.comsystem.cpu.itb.write_misses 0 # DTB write misses 39711507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 39811507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 39911507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40011507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40111507SCurtis.Dunham@arm.comsystem.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 40211507SCurtis.Dunham@arm.comsystem.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 40311507SCurtis.Dunham@arm.comsystem.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 40411507SCurtis.Dunham@arm.comsystem.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 40511507SCurtis.Dunham@arm.comsystem.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 40611507SCurtis.Dunham@arm.comsystem.cpu.itb.read_accesses 0 # DTB read accesses 40711507SCurtis.Dunham@arm.comsystem.cpu.itb.write_accesses 0 # DTB write accesses 40811507SCurtis.Dunham@arm.comsystem.cpu.itb.inst_accesses 0 # ITB inst accesses 40911507SCurtis.Dunham@arm.comsystem.cpu.itb.hits 0 # DTB hits 41011507SCurtis.Dunham@arm.comsystem.cpu.itb.misses 0 # DTB misses 41111507SCurtis.Dunham@arm.comsystem.cpu.itb.accesses 0 # DTB accesses 41211507SCurtis.Dunham@arm.comsystem.cpu.workload.num_syscalls 673 # Number of system calls 41311570SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON 512588680500 # Cumulative time (in ticks) in various power states 41411570SCurtis.Dunham@arm.comsystem.cpu.numCycles 1025177361 # number of cpu cycles simulated 41511507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 41611507SCurtis.Dunham@arm.comsystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 41711507SCurtis.Dunham@arm.comsystem.cpu.committedInsts 640655085 # Number of instructions committed 41811507SCurtis.Dunham@arm.comsystem.cpu.committedOps 788730744 # Number of ops (including micro ops) committed 41911570SCurtis.Dunham@arm.comsystem.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit 42011507SCurtis.Dunham@arm.comsystem.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 42111570SCurtis.Dunham@arm.comsystem.cpu.cpi 1.600202 # CPI: cycles per instruction 42211570SCurtis.Dunham@arm.comsystem.cpu.ipc 0.624921 # IPC: instructions per cycle 42311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 42411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction 42511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 42611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 42711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 42811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 42911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 43011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 43111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 43211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 43311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 43411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 43511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 43611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 43711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 43811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 43911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 44011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 44111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 44211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 44311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 44411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 44511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 44611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 44711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 44811507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 44911507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 45011507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 45111507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 45211507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 45311507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 45411507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction 45511507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 45611507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 45711507SCurtis.Dunham@arm.comsystem.cpu.op_class_0::total 788730744 # Class of committed instruction 45811570SCurtis.Dunham@arm.comsystem.cpu.tickCycles 955908039 # Number of cycles that the object actually ticked 45911570SCurtis.Dunham@arm.comsystem.cpu.idleCycles 69269322 # Total number of cycles that the object has spent stopped 46011570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 46111570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.replacements 778100 # number of replacements 46211570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tagsinuse 4092.241926 # Cycle average of tags in use 46311570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. 46411570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. 46511570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. 46611570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.warmup_cycle 798177500 # Cycle when the warmup percentage was hit. 46711570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 4092.241926 # Average occupied blocks per requestor 46811570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.999083 # Average percentage of cache occupancy 46911570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.999083 # Average percentage of cache occupancy 47011507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 47111570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 47211570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 47311570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id 47411570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::3 1420 # Occupied blocks per task id 47511570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id 47611507SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 47711570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses 47811570SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses 47911570SCurtis.Dunham@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 48011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits 48111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits 48211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits 48311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits 48411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits 48511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits 48611507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 48711507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 48811507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 48911507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 49011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::cpu.data 378434445 # number of demand (read+write) hits 49111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_hits::total 378434445 # number of demand (read+write) hits 49211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::cpu.data 378437929 # number of overall hits 49311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_hits::total 378437929 # number of overall hits 49411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 713192 # number of ReadReq misses 49511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 713192 # number of ReadReq misses 49611570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses 49711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses 49811507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses 49911507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses 50011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::cpu.data 850904 # number of demand (read+write) misses 50111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses 50211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses 50311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_misses::total 851045 # number of overall misses 50411570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 24628452500 # number of ReadReq miss cycles 50511570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 24628452500 # number of ReadReq miss cycles 50611570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 10137526000 # number of WriteReq miss cycles 50711570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 10137526000 # number of WriteReq miss cycles 50811570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 34765978500 # number of demand (read+write) miss cycles 50911570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_latency::total 34765978500 # number of demand (read+write) miss cycles 51011570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 34765978500 # number of overall miss cycles 51111570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_latency::total 34765978500 # number of overall miss cycles 51211570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) 51311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) 51411507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 51511507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 51611507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) 51711507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses) 51811507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 51911507SCurtis.Dunham@arm.comsystem.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 52011507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 52111507SCurtis.Dunham@arm.comsystem.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 52211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 379285349 # number of demand (read+write) accesses 52311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_accesses::total 379285349 # number of demand (read+write) accesses 52411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 379288974 # number of overall (read+write) accesses 52511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_accesses::total 379288974 # number of overall (read+write) accesses 52611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002849 # miss rate for ReadReq accesses 52711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.002849 # miss rate for ReadReq accesses 52811507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses 52911507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 53011507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses 53111507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses 53211570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.002243 # miss rate for demand accesses 53311570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses 53411570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses 53511570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses 53611570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34532.709986 # average ReadReq miss latency 53711570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 34532.709986 # average ReadReq miss latency 53811570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73613.962472 # average WriteReq miss latency 53911570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 73613.962472 # average WriteReq miss latency 54011570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 40857.697813 # average overall miss latency 54111570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 40857.697813 # average overall miss latency 54211570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 40850.928564 # average overall miss latency 54311570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 40850.928564 # average overall miss latency 54411507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 54511507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 54611507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 54711507SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 54811507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 54911507SCurtis.Dunham@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 55011570SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::writebacks 88716 # number of writebacks 55111570SCurtis.Dunham@arm.comsystem.cpu.dcache.writebacks::total 88716 # number of writebacks 55211570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits 55311570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits 55411570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits 55511570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits 55611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 68847 # number of demand (read+write) MSHR hits 55711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_hits::total 68847 # number of demand (read+write) MSHR hits 55811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 68847 # number of overall MSHR hits 55911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_hits::total 68847 # number of overall MSHR hits 56011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 712735 # number of ReadReq MSHR misses 56111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_misses::total 712735 # number of ReadReq MSHR misses 56211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses 56311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses 56411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 56511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 56611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 782057 # number of demand (read+write) MSHR misses 56711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses 56811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses 56911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses 57011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23907337500 # number of ReadReq MSHR miss cycles 57111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 23907337500 # number of ReadReq MSHR miss cycles 57211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5084282000 # number of WriteReq MSHR miss cycles 57311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 5084282000 # number of WriteReq MSHR miss cycles 57411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles 57511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles 57611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 28991619500 # number of demand (read+write) MSHR miss cycles 57711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 28991619500 # number of demand (read+write) MSHR miss cycles 57811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993407500 # number of overall MSHR miss cycles 57911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 28993407500 # number of overall MSHR miss cycles 58011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 58111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 58211507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 58311507SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 58411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses 58511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses 58611507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 58711507SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 58811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 58911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses 59011570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33543.094558 # average ReadReq mshr miss latency 59111570SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33543.094558 # average ReadReq mshr miss latency 59211570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73342.979141 # average WriteReq mshr miss latency 59311570SCurtis.Dunham@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73342.979141 # average WriteReq mshr miss latency 59411507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency 59511507SCurtis.Dunham@arm.comsystem.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency 59611570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37070.980120 # average overall mshr miss latency 59711570SCurtis.Dunham@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 37070.980120 # average overall mshr miss latency 59811570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37066.678301 # average overall mshr miss latency 59911570SCurtis.Dunham@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 37066.678301 # average overall mshr miss latency 60011570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 60111570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.replacements 24885 # number of replacements 60211570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tagsinuse 1711.979735 # Cycle average of tags in use 60311570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.total_refs 257789647 # Total number of references to valid blocks. 60411570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. 60511570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.avg_refs 9678.241741 # Average number of references to valid blocks. 60611507SCurtis.Dunham@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 60711570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 1711.979735 # Average occupied blocks per requestor 60811570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.835928 # Average percentage of cache occupancy 60911570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_percent::total 0.835928 # Average percentage of cache occupancy 61011570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id 61111570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 61211570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 61311570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id 61411570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id 61511570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.tag_accesses 515659204 # Number of tag accesses 61611570SCurtis.Dunham@arm.comsystem.cpu.icache.tags.data_accesses 515659204 # Number of data accesses 61711570SCurtis.Dunham@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 61811570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 257789647 # number of ReadReq hits 61911570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_hits::total 257789647 # number of ReadReq hits 62011570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::cpu.inst 257789647 # number of demand (read+write) hits 62111570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_hits::total 257789647 # number of demand (read+write) hits 62211570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::cpu.inst 257789647 # number of overall hits 62311570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_hits::total 257789647 # number of overall hits 62411570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses 62511570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses 62611570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses 62711570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses 62811570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses 62911570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 26637 # number of overall misses 63011570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 515552500 # number of ReadReq miss cycles 63111570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 515552500 # number of ReadReq miss cycles 63211570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 515552500 # number of demand (read+write) miss cycles 63311570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_latency::total 515552500 # number of demand (read+write) miss cycles 63411570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 515552500 # number of overall miss cycles 63511570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_latency::total 515552500 # number of overall miss cycles 63611570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 257816284 # number of ReadReq accesses(hits+misses) 63711570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_accesses::total 257816284 # number of ReadReq accesses(hits+misses) 63811570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 257816284 # number of demand (read+write) accesses 63911570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_accesses::total 257816284 # number of demand (read+write) accesses 64011570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 257816284 # number of overall (read+write) accesses 64111570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_accesses::total 257816284 # number of overall (read+write) accesses 64211570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses 64311570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses 64411570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses 64511570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses 64611570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses 64711570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses 64811570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19354.750910 # average ReadReq miss latency 64911570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 19354.750910 # average ReadReq miss latency 65011570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency 65111570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 19354.750910 # average overall miss latency 65211570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency 65311570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 19354.750910 # average overall miss latency 65411507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 65511507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 65611507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 65711507SCurtis.Dunham@arm.comsystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 65811507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 65911507SCurtis.Dunham@arm.comsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 66011570SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::writebacks 24885 # number of writebacks 66111570SCurtis.Dunham@arm.comsystem.cpu.icache.writebacks::total 24885 # number of writebacks 66211570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 26637 # number of ReadReq MSHR misses 66311570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 26637 # number of ReadReq MSHR misses 66411570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 26637 # number of demand (read+write) MSHR misses 66511570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses 66611570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses 66711570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses 66811570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 488916500 # number of ReadReq MSHR miss cycles 66911570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 488916500 # number of ReadReq MSHR miss cycles 67011570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 488916500 # number of demand (read+write) MSHR miss cycles 67111570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 488916500 # number of demand (read+write) MSHR miss cycles 67211570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 488916500 # number of overall MSHR miss cycles 67311570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 488916500 # number of overall MSHR miss cycles 67411570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses 67511570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses 67611570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses 67711570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses 67811570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses 67911570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses 68011570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18354.788452 # average ReadReq mshr miss latency 68111570SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18354.788452 # average ReadReq mshr miss latency 68211570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency 68311570SCurtis.Dunham@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency 68411570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency 68511570SCurtis.Dunham@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency 68611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 68711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.replacements 258816 # number of replacements 68811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tagsinuse 32567.443571 # Cycle average of tags in use 68911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.total_refs 1247529 # Total number of references to valid blocks. 69011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.sampled_refs 291562 # Sample count of references to valid blocks. 69111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.avg_refs 4.278778 # Average number of references to valid blocks. 69211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 69311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::writebacks 2619.708679 # Average occupied blocks per requestor 69411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 89.014636 # Average occupied blocks per requestor 69511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 29858.720256 # Average occupied blocks per requestor 69611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::writebacks 0.079947 # Average percentage of cache occupancy 69711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.002717 # Average percentage of cache occupancy 69811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.911216 # Average percentage of cache occupancy 69911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy 70011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 32746 # Occupied blocks per task id 70111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 70211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id 70311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id 70411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id 70511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::4 29128 # Occupied blocks per task id 70611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.999329 # Percentage of cache occupancy per task id 70711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.tag_accesses 13229556 # Number of tag accesses 70811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.data_accesses 13229556 # Number of data accesses 70911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 71011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::writebacks 88716 # number of WritebackDirty hits 71111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_hits::total 88716 # number of WritebackDirty hits 71211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits 71311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_hits::total 23552 # number of WritebackClean hits 71411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 71511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 71611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24067 # number of ReadCleanReq hits 71711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 24067 # number of ReadCleanReq hits 71811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::cpu.data 490282 # number of ReadSharedReq hits 71911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_hits::total 490282 # number of ReadSharedReq hits 72011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.inst 24067 # number of demand (read+write) hits 72111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::cpu.data 493513 # number of demand (read+write) hits 72211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_hits::total 517580 # number of demand (read+write) hits 72311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.inst 24067 # number of overall hits 72411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::cpu.data 493513 # number of overall hits 72511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_hits::total 517580 # number of overall hits 72611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses 72711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses 72811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2570 # number of ReadCleanReq misses 72911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 2570 # number of ReadCleanReq misses 73011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 222592 # number of ReadSharedReq misses 73111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_misses::total 222592 # number of ReadSharedReq misses 73211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 2570 # number of demand (read+write) misses 73311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::cpu.data 288683 # number of demand (read+write) misses 73411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_misses::total 291253 # number of demand (read+write) misses 73511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses 73611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::cpu.data 288683 # number of overall misses 73711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_misses::total 291253 # number of overall misses 73811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4946370000 # number of ReadExReq miss cycles 73911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 4946370000 # number of ReadExReq miss cycles 74011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194980000 # number of ReadCleanReq miss cycles 74111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 194980000 # number of ReadCleanReq miss cycles 74211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17689881000 # number of ReadSharedReq miss cycles 74311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 17689881000 # number of ReadSharedReq miss cycles 74411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 194980000 # number of demand (read+write) miss cycles 74511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 22636251000 # number of demand (read+write) miss cycles 74611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_latency::total 22831231000 # number of demand (read+write) miss cycles 74711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 194980000 # number of overall miss cycles 74811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 22636251000 # number of overall miss cycles 74911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_latency::total 22831231000 # number of overall miss cycles 75011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::writebacks 88716 # number of WritebackDirty accesses(hits+misses) 75111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackDirty_accesses::total 88716 # number of WritebackDirty accesses(hits+misses) 75211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) 75311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.WritebackClean_accesses::total 23552 # number of WritebackClean accesses(hits+misses) 75411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) 75511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) 75611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26637 # number of ReadCleanReq accesses(hits+misses) 75711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 26637 # number of ReadCleanReq accesses(hits+misses) 75811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712874 # number of ReadSharedReq accesses(hits+misses) 75911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 712874 # number of ReadSharedReq accesses(hits+misses) 76011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 26637 # number of demand (read+write) accesses 76111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::cpu.data 782196 # number of demand (read+write) accesses 76211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_accesses::total 808833 # number of demand (read+write) accesses 76311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 26637 # number of overall (read+write) accesses 76411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::cpu.data 782196 # number of overall (read+write) accesses 76511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_accesses::total 808833 # number of overall (read+write) accesses 76611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses 76711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses 76811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096482 # miss rate for ReadCleanReq accesses 76911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096482 # miss rate for ReadCleanReq accesses 77011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312246 # miss rate for ReadSharedReq accesses 77111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312246 # miss rate for ReadSharedReq accesses 77211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.096482 # miss rate for demand accesses 77311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 0.369067 # miss rate for demand accesses 77411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.360090 # miss rate for demand accesses 77511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses 77611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 0.369067 # miss rate for overall accesses 77711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.360090 # miss rate for overall accesses 77811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74841.809021 # average ReadExReq miss latency 77911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 74841.809021 # average ReadExReq miss latency 78011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.704280 # average ReadCleanReq miss latency 78111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.704280 # average ReadCleanReq miss latency 78211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79472.222721 # average ReadSharedReq miss latency 78311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79472.222721 # average ReadSharedReq miss latency 78411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency 78511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency 78611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 78389.685256 # average overall miss latency 78711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency 78811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency 78911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 78389.685256 # average overall miss latency 79011507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 79111507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 79211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 79311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 79411507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 79511507SCurtis.Dunham@arm.comsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 79611507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 79711507SCurtis.Dunham@arm.comsystem.cpu.l2cache.writebacks::total 66098 # number of writebacks 79811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits 79911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 80011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 26 # number of ReadSharedReq MSHR hits 80111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_hits::total 26 # number of ReadSharedReq MSHR hits 80211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 80311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits 80411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits 80511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 80611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits 80711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits 80811507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses 80911507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses 81011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2566 # number of ReadCleanReq MSHR misses 81111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 2566 # number of ReadCleanReq MSHR misses 81211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222566 # number of ReadSharedReq MSHR misses 81311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 222566 # number of ReadSharedReq MSHR misses 81411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses 81511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 288657 # number of demand (read+write) MSHR misses 81611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 291223 # number of demand (read+write) MSHR misses 81711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses 81811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 288657 # number of overall MSHR misses 81911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 291223 # number of overall MSHR misses 82011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285460000 # number of ReadExReq MSHR miss cycles 82111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285460000 # number of ReadExReq MSHR miss cycles 82211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169076000 # number of ReadCleanReq MSHR miss cycles 82311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169076000 # number of ReadCleanReq MSHR miss cycles 82411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15462440500 # number of ReadSharedReq MSHR miss cycles 82511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15462440500 # number of ReadSharedReq MSHR miss cycles 82611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169076000 # number of demand (read+write) MSHR miss cycles 82711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19747900500 # number of demand (read+write) MSHR miss cycles 82811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 19916976500 # number of demand (read+write) MSHR miss cycles 82911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169076000 # number of overall MSHR miss cycles 83011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19747900500 # number of overall MSHR miss cycles 83111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 19916976500 # number of overall MSHR miss cycles 83211507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses 83311507SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses 83411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses 83511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses 83611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312209 # mshr miss rate for ReadSharedReq accesses 83711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312209 # mshr miss rate for ReadSharedReq accesses 83811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses 83911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for demand accesses 84011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.360053 # mshr miss rate for demand accesses 84111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses 84211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for overall accesses 84311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.360053 # mshr miss rate for overall accesses 84411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64841.809021 # average ReadExReq mshr miss latency 84511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64841.809021 # average ReadExReq mshr miss latency 84611570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65890.880748 # average ReadCleanReq mshr miss latency 84711570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65890.880748 # average ReadCleanReq mshr miss latency 84811570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69473.506735 # average ReadSharedReq mshr miss latency 84911570SCurtis.Dunham@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69473.506735 # average ReadSharedReq mshr miss latency 85011570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency 85111570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency 85211570SCurtis.Dunham@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency 85311570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency 85411570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency 85511570SCurtis.Dunham@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency 85611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. 85711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. 85811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 85911507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. 86011507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 86111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 86211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 86311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution 86411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackDirty 154814 # Transaction distribution 86511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution 86611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::CleanEvict 882102 # Transaction distribution 86711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 86811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 86911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution 87011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution 87111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78158 # Packet count per connected master and slave (bytes) 87211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes) 87311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_count::total 2420650 # Packet count per connected master and slave (bytes) 87411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297344 # Cumulative packet size per connected master and slave (bytes) 87511570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55738368 # Cumulative packet size per connected master and slave (bytes) 87611570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pkt_size::total 59035712 # Cumulative packet size per connected master and slave (bytes) 87711570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoops 258816 # Total snoops (count) 87811570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) 87911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 1067649 # Request fanout histogram 88011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.004997 # Request fanout histogram 88111570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.070711 # Request fanout histogram 88211507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 88311570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 1062329 99.50% 99.50% # Request fanout histogram 88411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 5305 0.50% 100.00% # Request fanout histogram 88511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram 88611507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 88711507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 88811507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 88911570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 1067649 # Request fanout histogram 89011570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 919510000 # Layer occupancy (ticks) 89111507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 89211570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 39955996 # Layer occupancy (ticks) 89311507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 89411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) 89511507SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 89611570SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 89711570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadResp 225131 # Transaction distribution 89811507SCurtis.Dunham@arm.comsystem.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 89911570SCurtis.Dunham@arm.comsystem.membus.trans_dist::CleanEvict 190690 # Transaction distribution 90011507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExReq 66091 # Transaction distribution 90111507SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadExResp 66091 # Transaction distribution 90211570SCurtis.Dunham@arm.comsystem.membus.trans_dist::ReadSharedReq 225131 # Transaction distribution 90311570SCurtis.Dunham@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839232 # Packet count per connected master and slave (bytes) 90411570SCurtis.Dunham@arm.comsystem.membus.pkt_count::total 839232 # Packet count per connected master and slave (bytes) 90511570SCurtis.Dunham@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868480 # Cumulative packet size per connected master and slave (bytes) 90611570SCurtis.Dunham@arm.comsystem.membus.pkt_size::total 22868480 # Cumulative packet size per connected master and slave (bytes) 90711507SCurtis.Dunham@arm.comsystem.membus.snoops 0 # Total snoops (count) 90811570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 90911570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::samples 548010 # Request fanout histogram 91011507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 91111507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 91211507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 91311570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::0 548010 100.00% 100.00% # Request fanout histogram 91411507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 91511507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 91611507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 91711507SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 91811570SCurtis.Dunham@arm.comsystem.membus.snoop_fanout::total 548010 # Request fanout histogram 91911570SCurtis.Dunham@arm.comsystem.membus.reqLayer0.occupancy 917220500 # Layer occupancy (ticks) 92011507SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 92111570SCurtis.Dunham@arm.comsystem.membus.respLayer1.occupancy 1554785500 # Layer occupancy (ticks) 92211507SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 0.3 # Layer utilization (%) 92311507SCurtis.Dunham@arm.com 92411507SCurtis.Dunham@arm.com---------- End Simulation Statistics ---------- 925