stats.txt revision 11570
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.512589 # Number of seconds simulated 4sim_ticks 512588680500 # Number of ticks simulated 5final_tick 512588680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 180394 # Simulator instruction rate (inst/s) 8host_op_rate 222088 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 144333179 # Simulator tick rate (ticks/s) 10host_mem_usage 275860 # Number of bytes of host memory used 11host_seconds 3551.43 # Real time elapsed on the host 12sim_insts 640655085 # Number of instructions simulated 13sim_ops 788730744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 164160 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 18474048 # Number of bytes read from this memory 19system.physmem.bytes_read::total 18638208 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 164160 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 164160 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2565 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 288657 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 291222 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 320257 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 36040687 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 36360943 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 320257 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 320257 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 8252761 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 8252761 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 8252761 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 320257 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 36040687 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 44613705 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 291222 # Number of read requests accepted 41system.physmem.writeReqs 66098 # Number of write requests accepted 42system.physmem.readBursts 291222 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 18617600 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 20608 # Total number of bytes read from write queue 46system.physmem.bytesWritten 4228864 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 18638208 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side 49system.physmem.servicedByWrQ 322 # Number of DRAM read bursts serviced by the write queue 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 52system.physmem.perBankRdBursts::0 18288 # Per bank write bursts 53system.physmem.perBankRdBursts::1 18133 # Per bank write bursts 54system.physmem.perBankRdBursts::2 18220 # Per bank write bursts 55system.physmem.perBankRdBursts::3 18178 # Per bank write bursts 56system.physmem.perBankRdBursts::4 18281 # Per bank write bursts 57system.physmem.perBankRdBursts::5 18410 # Per bank write bursts 58system.physmem.perBankRdBursts::6 18174 # Per bank write bursts 59system.physmem.perBankRdBursts::7 17993 # Per bank write bursts 60system.physmem.perBankRdBursts::8 18029 # Per bank write bursts 61system.physmem.perBankRdBursts::9 18057 # Per bank write bursts 62system.physmem.perBankRdBursts::10 18103 # Per bank write bursts 63system.physmem.perBankRdBursts::11 18205 # Per bank write bursts 64system.physmem.perBankRdBursts::12 18223 # Per bank write bursts 65system.physmem.perBankRdBursts::13 18272 # Per bank write bursts 66system.physmem.perBankRdBursts::14 18077 # Per bank write bursts 67system.physmem.perBankRdBursts::15 18257 # Per bank write bursts 68system.physmem.perBankWrBursts::0 4171 # Per bank write bursts 69system.physmem.perBankWrBursts::1 4099 # Per bank write bursts 70system.physmem.perBankWrBursts::2 4135 # Per bank write bursts 71system.physmem.perBankWrBursts::3 4146 # Per bank write bursts 72system.physmem.perBankWrBursts::4 4223 # Per bank write bursts 73system.physmem.perBankWrBursts::5 4222 # Per bank write bursts 74system.physmem.perBankWrBursts::6 4173 # Per bank write bursts 75system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 76system.physmem.perBankWrBursts::8 4096 # Per bank write bursts 77system.physmem.perBankWrBursts::9 4096 # Per bank write bursts 78system.physmem.perBankWrBursts::10 4096 # Per bank write bursts 79system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 80system.physmem.perBankWrBursts::12 4098 # Per bank write bursts 81system.physmem.perBankWrBursts::13 4096 # Per bank write bursts 82system.physmem.perBankWrBursts::14 4096 # Per bank write bursts 83system.physmem.perBankWrBursts::15 4138 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 86system.physmem.totGap 512588586500 # Total gap between requests 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 291222 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 66098 # Write request sizes (log2) 101system.physmem.rdQLenPdf::0 290535 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 355 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 10 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::15 910 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 910 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 4009 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 4017 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 4017 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 4017 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 4017 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 4016 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 4016 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 4017 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 4017 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 4017 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 4018 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 4016 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 4018 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 4019 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 4016 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 4016 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 197system.physmem.bytesPerActivate::samples 110334 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 207.049577 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 134.865332 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 256.872236 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 45104 40.88% 40.88% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 43590 39.51% 80.39% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 9238 8.37% 88.76% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 1655 1.50% 90.26% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 896 0.81% 91.07% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 605 0.55% 91.62% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 780 0.71% 92.33% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 416 0.38% 92.70% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 8050 7.30% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 110334 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 4016 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 48.533367 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 34.247557 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 506.662918 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 4014 99.95% 99.95% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 4016 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 4016 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.453187 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.432732 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.838251 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 3107 77.37% 77.37% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::18 907 22.58% 99.95% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::19 2 0.05% 100.00% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::total 4016 # Writes before turning the bus around for reads 227system.physmem.totQLat 2758807250 # Total ticks spent queuing 228system.physmem.totMemAccLat 8213182250 # Total ticks spent from burst creation until serviced by the DRAM 229system.physmem.totBusLat 1454500000 # Total ticks spent in databus transfers 230system.physmem.avgQLat 9483.70 # Average queueing delay per DRAM burst 231system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 232system.physmem.avgMemAccLat 28233.70 # Average memory access latency per DRAM burst 233system.physmem.avgRdBW 36.32 # Average DRAM read bandwidth in MiByte/s 234system.physmem.avgWrBW 8.25 # Average achieved write bandwidth in MiByte/s 235system.physmem.avgRdBWSys 36.36 # Average system read bandwidth in MiByte/s 236system.physmem.avgWrBWSys 8.25 # Average system write bandwidth in MiByte/s 237system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 238system.physmem.busUtil 0.35 # Data bus utilization in percentage 239system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads 240system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 241system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 242system.physmem.avgWrQLen 22.93 # Average write queue length when enqueuing 243system.physmem.readRowHits 195021 # Number of row buffer hits during reads 244system.physmem.writeRowHits 51610 # Number of row buffer hits during writes 245system.physmem.readRowHitRate 67.04 # Row buffer hit rate for reads 246system.physmem.writeRowHitRate 78.08 # Row buffer hit rate for writes 247system.physmem.avgGap 1434536.51 # Average gap between requests 248system.physmem.pageHitRate 69.08 # Row buffer hit rate, read and write combined 249system.physmem_0.actEnergy 417312000 # Energy for activate commands per rank (pJ) 250system.physmem_0.preEnergy 227700000 # Energy for precharge commands per rank (pJ) 251system.physmem_0.readEnergy 1136202600 # Energy for read commands per rank (pJ) 252system.physmem_0.writeEnergy 215544240 # Energy for write commands per rank (pJ) 253system.physmem_0.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ) 254system.physmem_0.actBackEnergy 103911193800 # Energy for active background per rank (pJ) 255system.physmem_0.preBackEnergy 216400632000 # Energy for precharge background per rank (pJ) 256system.physmem_0.totalEnergy 355788106560 # Total energy per rank (pJ) 257system.physmem_0.averagePower 694.106023 # Core power per rank (mW) 258system.physmem_0.memoryStateTime::IDLE 359300376000 # Time in different power states 259system.physmem_0.memoryStateTime::REF 17116320000 # Time in different power states 260system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 261system.physmem_0.memoryStateTime::ACT 136167987750 # Time in different power states 262system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 263system.physmem_1.actEnergy 416737440 # Energy for activate commands per rank (pJ) 264system.physmem_1.preEnergy 227386500 # Energy for precharge commands per rank (pJ) 265system.physmem_1.readEnergy 1132435200 # Energy for read commands per rank (pJ) 266system.physmem_1.writeEnergy 212628240 # Energy for write commands per rank (pJ) 267system.physmem_1.refreshEnergy 33479521920 # Energy for refresh commands per rank (pJ) 268system.physmem_1.actBackEnergy 103626578835 # Energy for active background per rank (pJ) 269system.physmem_1.preBackEnergy 216650294250 # Energy for precharge background per rank (pJ) 270system.physmem_1.totalEnergy 355745582385 # Total energy per rank (pJ) 271system.physmem_1.averagePower 694.023062 # Core power per rank (mW) 272system.physmem_1.memoryStateTime::IDLE 359717078250 # Time in different power states 273system.physmem_1.memoryStateTime::REF 17116320000 # Time in different power states 274system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 275system.physmem_1.memoryStateTime::ACT 135751825750 # Time in different power states 276system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 277system.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 278system.cpu.branchPred.lookups 147261658 # Number of BP lookups 279system.cpu.branchPred.condPredicted 98231058 # Number of conditional branches predicted 280system.cpu.branchPred.condIncorrect 1384734 # Number of conditional branches incorrect 281system.cpu.branchPred.BTBLookups 89949366 # Number of BTB lookups 282system.cpu.branchPred.BTBHits 63294628 # Number of BTB hits 283system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 284system.cpu.branchPred.BTBHitPct 70.366953 # BTB Hit Percentage 285system.cpu.branchPred.usedRAS 19276105 # Number of times the RAS was used to get a target. 286system.cpu.branchPred.RASInCorrect 1312 # Number of incorrect RAS predictions. 287system.cpu.branchPred.indirectLookups 15995155 # Number of indirect predictor lookups. 288system.cpu.branchPred.indirectHits 15988941 # Number of indirect target hits. 289system.cpu.branchPred.indirectMisses 6214 # Number of indirect misses. 290system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. 291system.cpu_clk_domain.clock 500 # Clock period in ticks 292system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 293system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 302system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 303system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 304system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 305system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 306system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 307system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 308system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 309system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 310system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 311system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 312system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 313system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 314system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 315system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 316system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 317system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 318system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 319system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 320system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 321system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 322system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 323system.cpu.dtb.walker.walks 0 # Table walker walks requested 324system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.inst_hits 0 # ITB inst hits 332system.cpu.dtb.inst_misses 0 # ITB inst misses 333system.cpu.dtb.read_hits 0 # DTB read hits 334system.cpu.dtb.read_misses 0 # DTB read misses 335system.cpu.dtb.write_hits 0 # DTB write hits 336system.cpu.dtb.write_misses 0 # DTB write misses 337system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 338system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 339system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 340system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 341system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 342system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 343system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 344system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 345system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 346system.cpu.dtb.read_accesses 0 # DTB read accesses 347system.cpu.dtb.write_accesses 0 # DTB write accesses 348system.cpu.dtb.inst_accesses 0 # ITB inst accesses 349system.cpu.dtb.hits 0 # DTB hits 350system.cpu.dtb.misses 0 # DTB misses 351system.cpu.dtb.accesses 0 # DTB accesses 352system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 353system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 362system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 363system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 364system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 365system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 366system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 367system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 368system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 371system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 372system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 373system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 374system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 375system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 376system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 377system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 378system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 379system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 380system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 381system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 382system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 383system.cpu.itb.walker.walks 0 # Table walker walks requested 384system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 385system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.inst_hits 0 # ITB inst hits 392system.cpu.itb.inst_misses 0 # ITB inst misses 393system.cpu.itb.read_hits 0 # DTB read hits 394system.cpu.itb.read_misses 0 # DTB read misses 395system.cpu.itb.write_hits 0 # DTB write hits 396system.cpu.itb.write_misses 0 # DTB write misses 397system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 398system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 399system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 400system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 401system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 402system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 403system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 404system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 405system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu.itb.read_accesses 0 # DTB read accesses 407system.cpu.itb.write_accesses 0 # DTB write accesses 408system.cpu.itb.inst_accesses 0 # ITB inst accesses 409system.cpu.itb.hits 0 # DTB hits 410system.cpu.itb.misses 0 # DTB misses 411system.cpu.itb.accesses 0 # DTB accesses 412system.cpu.workload.num_syscalls 673 # Number of system calls 413system.cpu.pwrStateResidencyTicks::ON 512588680500 # Cumulative time (in ticks) in various power states 414system.cpu.numCycles 1025177361 # number of cpu cycles simulated 415system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 416system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 417system.cpu.committedInsts 640655085 # Number of instructions committed 418system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed 419system.cpu.discardedOps 8621768 # Number of ops (including micro ops) which were discarded before commit 420system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 421system.cpu.cpi 1.600202 # CPI: cycles per instruction 422system.cpu.ipc 0.624921 # IPC: instructions per cycle 423system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 424system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction 425system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 426system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 427system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 428system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 429system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 430system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 431system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 432system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 433system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 434system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 435system.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 436system.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 437system.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 438system.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 439system.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 440system.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 441system.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 442system.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 443system.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 444system.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 445system.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 446system.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 447system.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 448system.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 449system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 450system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 451system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 452system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 453system.cpu.op_class_0::MemRead 252240938 31.98% 83.65% # Class of committed instruction 454system.cpu.op_class_0::MemWrite 128980497 16.35% 100.00% # Class of committed instruction 455system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 456system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 457system.cpu.op_class_0::total 788730744 # Class of committed instruction 458system.cpu.tickCycles 955908039 # Number of cycles that the object actually ticked 459system.cpu.idleCycles 69269322 # Total number of cycles that the object has spent stopped 460system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 461system.cpu.dcache.tags.replacements 778100 # number of replacements 462system.cpu.dcache.tags.tagsinuse 4092.241926 # Cycle average of tags in use 463system.cpu.dcache.tags.total_refs 378449407 # Total number of references to valid blocks. 464system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. 465system.cpu.dcache.tags.avg_refs 483.829382 # Average number of references to valid blocks. 466system.cpu.dcache.tags.warmup_cycle 798177500 # Cycle when the warmup percentage was hit. 467system.cpu.dcache.tags.occ_blocks::cpu.data 4092.241926 # Average occupied blocks per requestor 468system.cpu.dcache.tags.occ_percent::cpu.data 0.999083 # Average percentage of cache occupancy 469system.cpu.dcache.tags.occ_percent::total 0.999083 # Average percentage of cache occupancy 470system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 471system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 472system.cpu.dcache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 473system.cpu.dcache.tags.age_task_id_blocks_1024::2 968 # Occupied blocks per task id 474system.cpu.dcache.tags.age_task_id_blocks_1024::3 1420 # Occupied blocks per task id 475system.cpu.dcache.tags.age_task_id_blocks_1024::4 1501 # Occupied blocks per task id 476system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 477system.cpu.dcache.tags.tag_accesses 759383100 # Number of tag accesses 478system.cpu.dcache.tags.data_accesses 759383100 # Number of data accesses 479system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 480system.cpu.dcache.ReadReq_hits::cpu.data 249620680 # number of ReadReq hits 481system.cpu.dcache.ReadReq_hits::total 249620680 # number of ReadReq hits 482system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits 483system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits 484system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits 485system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits 486system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 487system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 488system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 489system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 490system.cpu.dcache.demand_hits::cpu.data 378434445 # number of demand (read+write) hits 491system.cpu.dcache.demand_hits::total 378434445 # number of demand (read+write) hits 492system.cpu.dcache.overall_hits::cpu.data 378437929 # number of overall hits 493system.cpu.dcache.overall_hits::total 378437929 # number of overall hits 494system.cpu.dcache.ReadReq_misses::cpu.data 713192 # number of ReadReq misses 495system.cpu.dcache.ReadReq_misses::total 713192 # number of ReadReq misses 496system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses 497system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses 498system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses 499system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses 500system.cpu.dcache.demand_misses::cpu.data 850904 # number of demand (read+write) misses 501system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses 502system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses 503system.cpu.dcache.overall_misses::total 851045 # number of overall misses 504system.cpu.dcache.ReadReq_miss_latency::cpu.data 24628452500 # number of ReadReq miss cycles 505system.cpu.dcache.ReadReq_miss_latency::total 24628452500 # number of ReadReq miss cycles 506system.cpu.dcache.WriteReq_miss_latency::cpu.data 10137526000 # number of WriteReq miss cycles 507system.cpu.dcache.WriteReq_miss_latency::total 10137526000 # number of WriteReq miss cycles 508system.cpu.dcache.demand_miss_latency::cpu.data 34765978500 # number of demand (read+write) miss cycles 509system.cpu.dcache.demand_miss_latency::total 34765978500 # number of demand (read+write) miss cycles 510system.cpu.dcache.overall_miss_latency::cpu.data 34765978500 # number of overall miss cycles 511system.cpu.dcache.overall_miss_latency::total 34765978500 # number of overall miss cycles 512system.cpu.dcache.ReadReq_accesses::cpu.data 250333872 # number of ReadReq accesses(hits+misses) 513system.cpu.dcache.ReadReq_accesses::total 250333872 # number of ReadReq accesses(hits+misses) 514system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 515system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 516system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) 517system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses) 518system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 519system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 520system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 521system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 522system.cpu.dcache.demand_accesses::cpu.data 379285349 # number of demand (read+write) accesses 523system.cpu.dcache.demand_accesses::total 379285349 # number of demand (read+write) accesses 524system.cpu.dcache.overall_accesses::cpu.data 379288974 # number of overall (read+write) accesses 525system.cpu.dcache.overall_accesses::total 379288974 # number of overall (read+write) accesses 526system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002849 # miss rate for ReadReq accesses 527system.cpu.dcache.ReadReq_miss_rate::total 0.002849 # miss rate for ReadReq accesses 528system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses 529system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 530system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses 531system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses 532system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 # miss rate for demand accesses 533system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses 534system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses 535system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses 536system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34532.709986 # average ReadReq miss latency 537system.cpu.dcache.ReadReq_avg_miss_latency::total 34532.709986 # average ReadReq miss latency 538system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73613.962472 # average WriteReq miss latency 539system.cpu.dcache.WriteReq_avg_miss_latency::total 73613.962472 # average WriteReq miss latency 540system.cpu.dcache.demand_avg_miss_latency::cpu.data 40857.697813 # average overall miss latency 541system.cpu.dcache.demand_avg_miss_latency::total 40857.697813 # average overall miss latency 542system.cpu.dcache.overall_avg_miss_latency::cpu.data 40850.928564 # average overall miss latency 543system.cpu.dcache.overall_avg_miss_latency::total 40850.928564 # average overall miss latency 544system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 545system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 546system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 547system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 548system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 549system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 550system.cpu.dcache.writebacks::writebacks 88716 # number of writebacks 551system.cpu.dcache.writebacks::total 88716 # number of writebacks 552system.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits 553system.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits 554system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits 555system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits 556system.cpu.dcache.demand_mshr_hits::cpu.data 68847 # number of demand (read+write) MSHR hits 557system.cpu.dcache.demand_mshr_hits::total 68847 # number of demand (read+write) MSHR hits 558system.cpu.dcache.overall_mshr_hits::cpu.data 68847 # number of overall MSHR hits 559system.cpu.dcache.overall_mshr_hits::total 68847 # number of overall MSHR hits 560system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712735 # number of ReadReq MSHR misses 561system.cpu.dcache.ReadReq_mshr_misses::total 712735 # number of ReadReq MSHR misses 562system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses 563system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses 564system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 565system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 566system.cpu.dcache.demand_mshr_misses::cpu.data 782057 # number of demand (read+write) MSHR misses 567system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses 568system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses 569system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses 570system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23907337500 # number of ReadReq MSHR miss cycles 571system.cpu.dcache.ReadReq_mshr_miss_latency::total 23907337500 # number of ReadReq MSHR miss cycles 572system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5084282000 # number of WriteReq MSHR miss cycles 573system.cpu.dcache.WriteReq_mshr_miss_latency::total 5084282000 # number of WriteReq MSHR miss cycles 574system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788000 # number of SoftPFReq MSHR miss cycles 575system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788000 # number of SoftPFReq MSHR miss cycles 576system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28991619500 # number of demand (read+write) MSHR miss cycles 577system.cpu.dcache.demand_mshr_miss_latency::total 28991619500 # number of demand (read+write) MSHR miss cycles 578system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28993407500 # number of overall MSHR miss cycles 579system.cpu.dcache.overall_mshr_miss_latency::total 28993407500 # number of overall MSHR miss cycles 580system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 581system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 582system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 583system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 584system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses 585system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses 586system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 587system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 588system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 589system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses 590system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33543.094558 # average ReadReq mshr miss latency 591system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33543.094558 # average ReadReq mshr miss latency 592system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73342.979141 # average WriteReq mshr miss latency 593system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73342.979141 # average WriteReq mshr miss latency 594system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12863.309353 # average SoftPFReq mshr miss latency 595system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12863.309353 # average SoftPFReq mshr miss latency 596system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37070.980120 # average overall mshr miss latency 597system.cpu.dcache.demand_avg_mshr_miss_latency::total 37070.980120 # average overall mshr miss latency 598system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37066.678301 # average overall mshr miss latency 599system.cpu.dcache.overall_avg_mshr_miss_latency::total 37066.678301 # average overall mshr miss latency 600system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 601system.cpu.icache.tags.replacements 24885 # number of replacements 602system.cpu.icache.tags.tagsinuse 1711.979735 # Cycle average of tags in use 603system.cpu.icache.tags.total_refs 257789647 # Total number of references to valid blocks. 604system.cpu.icache.tags.sampled_refs 26636 # Sample count of references to valid blocks. 605system.cpu.icache.tags.avg_refs 9678.241741 # Average number of references to valid blocks. 606system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 607system.cpu.icache.tags.occ_blocks::cpu.inst 1711.979735 # Average occupied blocks per requestor 608system.cpu.icache.tags.occ_percent::cpu.inst 0.835928 # Average percentage of cache occupancy 609system.cpu.icache.tags.occ_percent::total 0.835928 # Average percentage of cache occupancy 610system.cpu.icache.tags.occ_task_id_blocks::1024 1751 # Occupied blocks per task id 611system.cpu.icache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::4 1596 # Occupied blocks per task id 614system.cpu.icache.tags.occ_task_id_percent::1024 0.854980 # Percentage of cache occupancy per task id 615system.cpu.icache.tags.tag_accesses 515659204 # Number of tag accesses 616system.cpu.icache.tags.data_accesses 515659204 # Number of data accesses 617system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 618system.cpu.icache.ReadReq_hits::cpu.inst 257789647 # number of ReadReq hits 619system.cpu.icache.ReadReq_hits::total 257789647 # number of ReadReq hits 620system.cpu.icache.demand_hits::cpu.inst 257789647 # number of demand (read+write) hits 621system.cpu.icache.demand_hits::total 257789647 # number of demand (read+write) hits 622system.cpu.icache.overall_hits::cpu.inst 257789647 # number of overall hits 623system.cpu.icache.overall_hits::total 257789647 # number of overall hits 624system.cpu.icache.ReadReq_misses::cpu.inst 26637 # number of ReadReq misses 625system.cpu.icache.ReadReq_misses::total 26637 # number of ReadReq misses 626system.cpu.icache.demand_misses::cpu.inst 26637 # number of demand (read+write) misses 627system.cpu.icache.demand_misses::total 26637 # number of demand (read+write) misses 628system.cpu.icache.overall_misses::cpu.inst 26637 # number of overall misses 629system.cpu.icache.overall_misses::total 26637 # number of overall misses 630system.cpu.icache.ReadReq_miss_latency::cpu.inst 515552500 # number of ReadReq miss cycles 631system.cpu.icache.ReadReq_miss_latency::total 515552500 # number of ReadReq miss cycles 632system.cpu.icache.demand_miss_latency::cpu.inst 515552500 # number of demand (read+write) miss cycles 633system.cpu.icache.demand_miss_latency::total 515552500 # number of demand (read+write) miss cycles 634system.cpu.icache.overall_miss_latency::cpu.inst 515552500 # number of overall miss cycles 635system.cpu.icache.overall_miss_latency::total 515552500 # number of overall miss cycles 636system.cpu.icache.ReadReq_accesses::cpu.inst 257816284 # number of ReadReq accesses(hits+misses) 637system.cpu.icache.ReadReq_accesses::total 257816284 # number of ReadReq accesses(hits+misses) 638system.cpu.icache.demand_accesses::cpu.inst 257816284 # number of demand (read+write) accesses 639system.cpu.icache.demand_accesses::total 257816284 # number of demand (read+write) accesses 640system.cpu.icache.overall_accesses::cpu.inst 257816284 # number of overall (read+write) accesses 641system.cpu.icache.overall_accesses::total 257816284 # number of overall (read+write) accesses 642system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses 643system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses 644system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses 645system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses 646system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses 647system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses 648system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19354.750910 # average ReadReq miss latency 649system.cpu.icache.ReadReq_avg_miss_latency::total 19354.750910 # average ReadReq miss latency 650system.cpu.icache.demand_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency 651system.cpu.icache.demand_avg_miss_latency::total 19354.750910 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::cpu.inst 19354.750910 # average overall miss latency 653system.cpu.icache.overall_avg_miss_latency::total 19354.750910 # average overall miss latency 654system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 655system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 656system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 657system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 658system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 659system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 660system.cpu.icache.writebacks::writebacks 24885 # number of writebacks 661system.cpu.icache.writebacks::total 24885 # number of writebacks 662system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26637 # number of ReadReq MSHR misses 663system.cpu.icache.ReadReq_mshr_misses::total 26637 # number of ReadReq MSHR misses 664system.cpu.icache.demand_mshr_misses::cpu.inst 26637 # number of demand (read+write) MSHR misses 665system.cpu.icache.demand_mshr_misses::total 26637 # number of demand (read+write) MSHR misses 666system.cpu.icache.overall_mshr_misses::cpu.inst 26637 # number of overall MSHR misses 667system.cpu.icache.overall_mshr_misses::total 26637 # number of overall MSHR misses 668system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 488916500 # number of ReadReq MSHR miss cycles 669system.cpu.icache.ReadReq_mshr_miss_latency::total 488916500 # number of ReadReq MSHR miss cycles 670system.cpu.icache.demand_mshr_miss_latency::cpu.inst 488916500 # number of demand (read+write) MSHR miss cycles 671system.cpu.icache.demand_mshr_miss_latency::total 488916500 # number of demand (read+write) MSHR miss cycles 672system.cpu.icache.overall_mshr_miss_latency::cpu.inst 488916500 # number of overall MSHR miss cycles 673system.cpu.icache.overall_mshr_miss_latency::total 488916500 # number of overall MSHR miss cycles 674system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses 675system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses 676system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses 677system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses 678system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses 679system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses 680system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18354.788452 # average ReadReq mshr miss latency 681system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18354.788452 # average ReadReq mshr miss latency 682system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency 683system.cpu.icache.demand_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency 684system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18354.788452 # average overall mshr miss latency 685system.cpu.icache.overall_avg_mshr_miss_latency::total 18354.788452 # average overall mshr miss latency 686system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 687system.cpu.l2cache.tags.replacements 258816 # number of replacements 688system.cpu.l2cache.tags.tagsinuse 32567.443571 # Cycle average of tags in use 689system.cpu.l2cache.tags.total_refs 1247529 # Total number of references to valid blocks. 690system.cpu.l2cache.tags.sampled_refs 291562 # Sample count of references to valid blocks. 691system.cpu.l2cache.tags.avg_refs 4.278778 # Average number of references to valid blocks. 692system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 693system.cpu.l2cache.tags.occ_blocks::writebacks 2619.708679 # Average occupied blocks per requestor 694system.cpu.l2cache.tags.occ_blocks::cpu.inst 89.014636 # Average occupied blocks per requestor 695system.cpu.l2cache.tags.occ_blocks::cpu.data 29858.720256 # Average occupied blocks per requestor 696system.cpu.l2cache.tags.occ_percent::writebacks 0.079947 # Average percentage of cache occupancy 697system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002717 # Average percentage of cache occupancy 698system.cpu.l2cache.tags.occ_percent::cpu.data 0.911216 # Average percentage of cache occupancy 699system.cpu.l2cache.tags.occ_percent::total 0.993880 # Average percentage of cache occupancy 700system.cpu.l2cache.tags.occ_task_id_blocks::1024 32746 # Occupied blocks per task id 701system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 702system.cpu.l2cache.tags.age_task_id_blocks_1024::1 208 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2978 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29128 # Occupied blocks per task id 706system.cpu.l2cache.tags.occ_task_id_percent::1024 0.999329 # Percentage of cache occupancy per task id 707system.cpu.l2cache.tags.tag_accesses 13229556 # Number of tag accesses 708system.cpu.l2cache.tags.data_accesses 13229556 # Number of data accesses 709system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 710system.cpu.l2cache.WritebackDirty_hits::writebacks 88716 # number of WritebackDirty hits 711system.cpu.l2cache.WritebackDirty_hits::total 88716 # number of WritebackDirty hits 712system.cpu.l2cache.WritebackClean_hits::writebacks 23552 # number of WritebackClean hits 713system.cpu.l2cache.WritebackClean_hits::total 23552 # number of WritebackClean hits 714system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 715system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 716system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24067 # number of ReadCleanReq hits 717system.cpu.l2cache.ReadCleanReq_hits::total 24067 # number of ReadCleanReq hits 718system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490282 # number of ReadSharedReq hits 719system.cpu.l2cache.ReadSharedReq_hits::total 490282 # number of ReadSharedReq hits 720system.cpu.l2cache.demand_hits::cpu.inst 24067 # number of demand (read+write) hits 721system.cpu.l2cache.demand_hits::cpu.data 493513 # number of demand (read+write) hits 722system.cpu.l2cache.demand_hits::total 517580 # number of demand (read+write) hits 723system.cpu.l2cache.overall_hits::cpu.inst 24067 # number of overall hits 724system.cpu.l2cache.overall_hits::cpu.data 493513 # number of overall hits 725system.cpu.l2cache.overall_hits::total 517580 # number of overall hits 726system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses 727system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses 728system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2570 # number of ReadCleanReq misses 729system.cpu.l2cache.ReadCleanReq_misses::total 2570 # number of ReadCleanReq misses 730system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222592 # number of ReadSharedReq misses 731system.cpu.l2cache.ReadSharedReq_misses::total 222592 # number of ReadSharedReq misses 732system.cpu.l2cache.demand_misses::cpu.inst 2570 # number of demand (read+write) misses 733system.cpu.l2cache.demand_misses::cpu.data 288683 # number of demand (read+write) misses 734system.cpu.l2cache.demand_misses::total 291253 # number of demand (read+write) misses 735system.cpu.l2cache.overall_misses::cpu.inst 2570 # number of overall misses 736system.cpu.l2cache.overall_misses::cpu.data 288683 # number of overall misses 737system.cpu.l2cache.overall_misses::total 291253 # number of overall misses 738system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4946370000 # number of ReadExReq miss cycles 739system.cpu.l2cache.ReadExReq_miss_latency::total 4946370000 # number of ReadExReq miss cycles 740system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 194980000 # number of ReadCleanReq miss cycles 741system.cpu.l2cache.ReadCleanReq_miss_latency::total 194980000 # number of ReadCleanReq miss cycles 742system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17689881000 # number of ReadSharedReq miss cycles 743system.cpu.l2cache.ReadSharedReq_miss_latency::total 17689881000 # number of ReadSharedReq miss cycles 744system.cpu.l2cache.demand_miss_latency::cpu.inst 194980000 # number of demand (read+write) miss cycles 745system.cpu.l2cache.demand_miss_latency::cpu.data 22636251000 # number of demand (read+write) miss cycles 746system.cpu.l2cache.demand_miss_latency::total 22831231000 # number of demand (read+write) miss cycles 747system.cpu.l2cache.overall_miss_latency::cpu.inst 194980000 # number of overall miss cycles 748system.cpu.l2cache.overall_miss_latency::cpu.data 22636251000 # number of overall miss cycles 749system.cpu.l2cache.overall_miss_latency::total 22831231000 # number of overall miss cycles 750system.cpu.l2cache.WritebackDirty_accesses::writebacks 88716 # number of WritebackDirty accesses(hits+misses) 751system.cpu.l2cache.WritebackDirty_accesses::total 88716 # number of WritebackDirty accesses(hits+misses) 752system.cpu.l2cache.WritebackClean_accesses::writebacks 23552 # number of WritebackClean accesses(hits+misses) 753system.cpu.l2cache.WritebackClean_accesses::total 23552 # number of WritebackClean accesses(hits+misses) 754system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) 755system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) 756system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26637 # number of ReadCleanReq accesses(hits+misses) 757system.cpu.l2cache.ReadCleanReq_accesses::total 26637 # number of ReadCleanReq accesses(hits+misses) 758system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712874 # number of ReadSharedReq accesses(hits+misses) 759system.cpu.l2cache.ReadSharedReq_accesses::total 712874 # number of ReadSharedReq accesses(hits+misses) 760system.cpu.l2cache.demand_accesses::cpu.inst 26637 # number of demand (read+write) accesses 761system.cpu.l2cache.demand_accesses::cpu.data 782196 # number of demand (read+write) accesses 762system.cpu.l2cache.demand_accesses::total 808833 # number of demand (read+write) accesses 763system.cpu.l2cache.overall_accesses::cpu.inst 26637 # number of overall (read+write) accesses 764system.cpu.l2cache.overall_accesses::cpu.data 782196 # number of overall (read+write) accesses 765system.cpu.l2cache.overall_accesses::total 808833 # number of overall (read+write) accesses 766system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses 767system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses 768system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096482 # miss rate for ReadCleanReq accesses 769system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096482 # miss rate for ReadCleanReq accesses 770system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312246 # miss rate for ReadSharedReq accesses 771system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312246 # miss rate for ReadSharedReq accesses 772system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096482 # miss rate for demand accesses 773system.cpu.l2cache.demand_miss_rate::cpu.data 0.369067 # miss rate for demand accesses 774system.cpu.l2cache.demand_miss_rate::total 0.360090 # miss rate for demand accesses 775system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096482 # miss rate for overall accesses 776system.cpu.l2cache.overall_miss_rate::cpu.data 0.369067 # miss rate for overall accesses 777system.cpu.l2cache.overall_miss_rate::total 0.360090 # miss rate for overall accesses 778system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74841.809021 # average ReadExReq miss latency 779system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74841.809021 # average ReadExReq miss latency 780system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75867.704280 # average ReadCleanReq miss latency 781system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75867.704280 # average ReadCleanReq miss latency 782system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 79472.222721 # average ReadSharedReq miss latency 783system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 79472.222721 # average ReadSharedReq miss latency 784system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency 785system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency 786system.cpu.l2cache.demand_avg_miss_latency::total 78389.685256 # average overall miss latency 787system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75867.704280 # average overall miss latency 788system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78412.137189 # average overall miss latency 789system.cpu.l2cache.overall_avg_miss_latency::total 78389.685256 # average overall miss latency 790system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 791system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 792system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 793system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 794system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 795system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 796system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 797system.cpu.l2cache.writebacks::total 66098 # number of writebacks 798system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits 799system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 800system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 26 # number of ReadSharedReq MSHR hits 801system.cpu.l2cache.ReadSharedReq_mshr_hits::total 26 # number of ReadSharedReq MSHR hits 802system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 803system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits 804system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits 805system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 806system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits 807system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits 808system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses 809system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses 810system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2566 # number of ReadCleanReq MSHR misses 811system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2566 # number of ReadCleanReq MSHR misses 812system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222566 # number of ReadSharedReq MSHR misses 813system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222566 # number of ReadSharedReq MSHR misses 814system.cpu.l2cache.demand_mshr_misses::cpu.inst 2566 # number of demand (read+write) MSHR misses 815system.cpu.l2cache.demand_mshr_misses::cpu.data 288657 # number of demand (read+write) MSHR misses 816system.cpu.l2cache.demand_mshr_misses::total 291223 # number of demand (read+write) MSHR misses 817system.cpu.l2cache.overall_mshr_misses::cpu.inst 2566 # number of overall MSHR misses 818system.cpu.l2cache.overall_mshr_misses::cpu.data 288657 # number of overall MSHR misses 819system.cpu.l2cache.overall_mshr_misses::total 291223 # number of overall MSHR misses 820system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4285460000 # number of ReadExReq MSHR miss cycles 821system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4285460000 # number of ReadExReq MSHR miss cycles 822system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 169076000 # number of ReadCleanReq MSHR miss cycles 823system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 169076000 # number of ReadCleanReq MSHR miss cycles 824system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15462440500 # number of ReadSharedReq MSHR miss cycles 825system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15462440500 # number of ReadSharedReq MSHR miss cycles 826system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169076000 # number of demand (read+write) MSHR miss cycles 827system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19747900500 # number of demand (read+write) MSHR miss cycles 828system.cpu.l2cache.demand_mshr_miss_latency::total 19916976500 # number of demand (read+write) MSHR miss cycles 829system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 169076000 # number of overall MSHR miss cycles 830system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19747900500 # number of overall MSHR miss cycles 831system.cpu.l2cache.overall_mshr_miss_latency::total 19916976500 # number of overall MSHR miss cycles 832system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses 833system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses 834system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for ReadCleanReq accesses 835system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096332 # mshr miss rate for ReadCleanReq accesses 836system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312209 # mshr miss rate for ReadSharedReq accesses 837system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312209 # mshr miss rate for ReadSharedReq accesses 838system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for demand accesses 839system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for demand accesses 840system.cpu.l2cache.demand_mshr_miss_rate::total 0.360053 # mshr miss rate for demand accesses 841system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096332 # mshr miss rate for overall accesses 842system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369034 # mshr miss rate for overall accesses 843system.cpu.l2cache.overall_mshr_miss_rate::total 0.360053 # mshr miss rate for overall accesses 844system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 64841.809021 # average ReadExReq mshr miss latency 845system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 64841.809021 # average ReadExReq mshr miss latency 846system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65890.880748 # average ReadCleanReq mshr miss latency 847system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65890.880748 # average ReadCleanReq mshr miss latency 848system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 69473.506735 # average ReadSharedReq mshr miss latency 849system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 69473.506735 # average ReadSharedReq mshr miss latency 850system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency 851system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency 852system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency 853system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65890.880748 # average overall mshr miss latency 854system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 68413.031730 # average overall mshr miss latency 855system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68390.808762 # average overall mshr miss latency 856system.cpu.toL2Bus.snoop_filter.tot_requests 1611818 # Total number of requests made to the snoop filter. 857system.cpu.toL2Bus.snoop_filter.hit_single_requests 803044 # Number of requests hitting in the snoop filter with a single holder of the requested data. 858system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 859system.cpu.toL2Bus.snoop_filter.tot_snoops 2027 # Total number of snoops made to the snoop filter. 860system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2012 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 861system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 862system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 863system.cpu.toL2Bus.trans_dist::ReadResp 739510 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::WritebackDirty 154814 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::WritebackClean 24885 # Transaction distribution 866system.cpu.toL2Bus.trans_dist::CleanEvict 882102 # Transaction distribution 867system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 869system.cpu.toL2Bus.trans_dist::ReadCleanReq 26637 # Transaction distribution 870system.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution 871system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78158 # Packet count per connected master and slave (bytes) 872system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes) 873system.cpu.toL2Bus.pkt_count::total 2420650 # Packet count per connected master and slave (bytes) 874system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297344 # Cumulative packet size per connected master and slave (bytes) 875system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55738368 # Cumulative packet size per connected master and slave (bytes) 876system.cpu.toL2Bus.pkt_size::total 59035712 # Cumulative packet size per connected master and slave (bytes) 877system.cpu.toL2Bus.snoops 258816 # Total snoops (count) 878system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) 879system.cpu.toL2Bus.snoop_fanout::samples 1067649 # Request fanout histogram 880system.cpu.toL2Bus.snoop_fanout::mean 0.004997 # Request fanout histogram 881system.cpu.toL2Bus.snoop_fanout::stdev 0.070711 # Request fanout histogram 882system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 883system.cpu.toL2Bus.snoop_fanout::0 1062329 99.50% 99.50% # Request fanout histogram 884system.cpu.toL2Bus.snoop_fanout::1 5305 0.50% 100.00% # Request fanout histogram 885system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram 886system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 887system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 888system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 889system.cpu.toL2Bus.snoop_fanout::total 1067649 # Request fanout histogram 890system.cpu.toL2Bus.reqLayer0.occupancy 919510000 # Layer occupancy (ticks) 891system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 892system.cpu.toL2Bus.respLayer0.occupancy 39955996 # Layer occupancy (ticks) 893system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 894system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) 895system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 896system.membus.pwrStateResidencyTicks::UNDEFINED 512588680500 # Cumulative time (in ticks) in various power states 897system.membus.trans_dist::ReadResp 225131 # Transaction distribution 898system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 899system.membus.trans_dist::CleanEvict 190690 # Transaction distribution 900system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 901system.membus.trans_dist::ReadExResp 66091 # Transaction distribution 902system.membus.trans_dist::ReadSharedReq 225131 # Transaction distribution 903system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839232 # Packet count per connected master and slave (bytes) 904system.membus.pkt_count::total 839232 # Packet count per connected master and slave (bytes) 905system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22868480 # Cumulative packet size per connected master and slave (bytes) 906system.membus.pkt_size::total 22868480 # Cumulative packet size per connected master and slave (bytes) 907system.membus.snoops 0 # Total snoops (count) 908system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 909system.membus.snoop_fanout::samples 548010 # Request fanout histogram 910system.membus.snoop_fanout::mean 0 # Request fanout histogram 911system.membus.snoop_fanout::stdev 0 # Request fanout histogram 912system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 913system.membus.snoop_fanout::0 548010 100.00% 100.00% # Request fanout histogram 914system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 915system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 916system.membus.snoop_fanout::min_value 0 # Request fanout histogram 917system.membus.snoop_fanout::max_value 0 # Request fanout histogram 918system.membus.snoop_fanout::total 548010 # Request fanout histogram 919system.membus.reqLayer0.occupancy 917220500 # Layer occupancy (ticks) 920system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 921system.membus.respLayer1.occupancy 1554785500 # Layer occupancy (ticks) 922system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 923 924---------- End Simulation Statistics ---------- 925