1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.525648 # Number of seconds simulated 4sim_ticks 525647850500 # Number of ticks simulated 5final_tick 525647850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 304424 # Simulator instruction rate (inst/s) 8host_op_rate 374786 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 249775392 # Simulator tick rate (ticks/s) 10host_mem_usage 281156 # Number of bytes of host memory used 11host_seconds 2104.48 # Real time elapsed on the host 12sim_insts 640655085 # Number of instructions simulated 13sim_ops 788730744 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 164544 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory 19system.physmem.bytes_read::total 18639040 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 164544 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 164544 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory 23system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 2571 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 291235 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 313031 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 35146146 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 35459177 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 313031 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 313031 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 8047730 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 8047730 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 8047730 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 313031 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 35146146 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 43506907 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 291235 # Number of read requests accepted 41system.physmem.writeReqs 66098 # Number of write requests accepted 42system.physmem.readBursts 291235 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 18619136 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue 46system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 18639040 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side 49system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 52system.physmem.perBankRdBursts::0 18288 # Per bank write bursts 53system.physmem.perBankRdBursts::1 18134 # Per bank write bursts 54system.physmem.perBankRdBursts::2 18217 # Per bank write bursts 55system.physmem.perBankRdBursts::3 18185 # Per bank write bursts 56system.physmem.perBankRdBursts::4 18292 # Per bank write bursts 57system.physmem.perBankRdBursts::5 18424 # Per bank write bursts 58system.physmem.perBankRdBursts::6 18179 # Per bank write bursts 59system.physmem.perBankRdBursts::7 17990 # Per bank write bursts 60system.physmem.perBankRdBursts::8 18031 # Per bank write bursts 61system.physmem.perBankRdBursts::9 18051 # Per bank write bursts 62system.physmem.perBankRdBursts::10 18108 # Per bank write bursts 63system.physmem.perBankRdBursts::11 18204 # Per bank write bursts 64system.physmem.perBankRdBursts::12 18211 # Per bank write bursts 65system.physmem.perBankRdBursts::13 18269 # Per bank write bursts 66system.physmem.perBankRdBursts::14 18079 # Per bank write bursts 67system.physmem.perBankRdBursts::15 18262 # Per bank write bursts 68system.physmem.perBankWrBursts::0 4171 # Per bank write bursts 69system.physmem.perBankWrBursts::1 4099 # Per bank write bursts 70system.physmem.perBankWrBursts::2 4134 # Per bank write bursts 71system.physmem.perBankWrBursts::3 4146 # Per bank write bursts 72system.physmem.perBankWrBursts::4 4223 # Per bank write bursts 73system.physmem.perBankWrBursts::5 4224 # Per bank write bursts 74system.physmem.perBankWrBursts::6 4173 # Per bank write bursts 75system.physmem.perBankWrBursts::7 4094 # Per bank write bursts 76system.physmem.perBankWrBursts::8 4093 # Per bank write bursts 77system.physmem.perBankWrBursts::9 4093 # Per bank write bursts 78system.physmem.perBankWrBursts::10 4096 # Per bank write bursts 79system.physmem.perBankWrBursts::11 4097 # Per bank write bursts 80system.physmem.perBankWrBursts::12 4095 # Per bank write bursts 81system.physmem.perBankWrBursts::13 4095 # Per bank write bursts 82system.physmem.perBankWrBursts::14 4095 # Per bank write bursts 83system.physmem.perBankWrBursts::15 4138 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 86system.physmem.totGap 525647749500 # Total gap between requests 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 291235 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 66098 # Write request sizes (log2) 101system.physmem.rdQLenPdf::0 290544 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 133system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 890 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 4020 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 4021 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 4021 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 4023 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 4020 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 4018 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 197system.physmem.bytesPerActivate::samples 102644 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 222.570282 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 147.559533 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 262.016403 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 36015 35.09% 35.09% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 41909 40.83% 75.92% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 13148 12.81% 88.73% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 1006 0.98% 89.71% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 491 0.48% 90.18% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 1034 1.01% 91.19% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 399 0.39% 91.58% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 481 0.47% 92.05% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 8161 7.95% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 102644 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 4018 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 48.515182 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 34.167653 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 506.604541 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 4016 99.95% 99.95% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 4018 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 4018 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.442509 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.422441 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.830286 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 3129 77.87% 77.87% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::18 889 22.13% 100.00% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::total 4018 # Writes before turning the bus around for reads 226system.physmem.totQLat 15528676000 # Total ticks spent queuing 227system.physmem.totMemAccLat 20983501000 # Total ticks spent from burst creation until serviced by the DRAM 228system.physmem.totBusLat 1454620000 # Total ticks spent in databus transfers 229system.physmem.avgQLat 53377.09 # Average queueing delay per DRAM burst 230system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 231system.physmem.avgMemAccLat 72127.09 # Average memory access latency per DRAM burst 232system.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s 233system.physmem.avgWrBW 8.04 # Average achieved write bandwidth in MiByte/s 234system.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s 235system.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s 236system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 237system.physmem.busUtil 0.34 # Data bus utilization in percentage 238system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads 239system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes 240system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing 241system.physmem.avgWrQLen 28.92 # Average write queue length when enqueuing 242system.physmem.readRowHits 202546 # Number of row buffer hits during reads 243system.physmem.writeRowHits 51789 # Number of row buffer hits during writes 244system.physmem.readRowHitRate 69.62 # Row buffer hit rate for reads 245system.physmem.writeRowHitRate 78.35 # Row buffer hit rate for writes 246system.physmem.avgGap 1471030.52 # Average gap between requests 247system.physmem.pageHitRate 71.24 # Row buffer hit rate, read and write combined 248system.physmem_0.actEnergy 366410520 # Energy for activate commands per rank (pJ) 249system.physmem_0.preEnergy 194736630 # Energy for precharge commands per rank (pJ) 250system.physmem_0.readEnergy 1040362260 # Energy for read commands per rank (pJ) 251system.physmem_0.writeEnergy 173638080 # Energy for write commands per rank (pJ) 252system.physmem_0.refreshEnergy 28886236080.000008 # Energy for refresh commands per rank (pJ) 253system.physmem_0.actBackEnergy 8300918550 # Energy for active background per rank (pJ) 254system.physmem_0.preBackEnergy 1634993280 # Energy for precharge background per rank (pJ) 255system.physmem_0.actPowerDownEnergy 57345491820 # Energy for active power-down per rank (pJ) 256system.physmem_0.prePowerDownEnergy 51305938080 # Energy for precharge power-down per rank (pJ) 257system.physmem_0.selfRefreshEnergy 64928910000 # Energy for self refresh per rank (pJ) 258system.physmem_0.totalEnergy 214198815120 # Total energy per rank (pJ) 259system.physmem_0.averagePower 407.494892 # Core power per rank (mW) 260system.physmem_0.totalIdleTime 503139346250 # Total Idle time Per DRAM Rank 261system.physmem_0.memoryStateTime::IDLE 3209706000 # Time in different power states 262system.physmem_0.memoryStateTime::REF 12289528000 # Time in different power states 263system.physmem_0.memoryStateTime::SREF 243772297750 # Time in different power states 264system.physmem_0.memoryStateTime::PRE_PDN 133609273250 # Time in different power states 265system.physmem_0.memoryStateTime::ACT 7009209500 # Time in different power states 266system.physmem_0.memoryStateTime::ACT_PDN 125757836000 # Time in different power states 267system.physmem_1.actEnergy 366546180 # Energy for activate commands per rank (pJ) 268system.physmem_1.preEnergy 194797350 # Energy for precharge commands per rank (pJ) 269system.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ) 270system.physmem_1.writeEnergy 171226440 # Energy for write commands per rank (pJ) 271system.physmem_1.refreshEnergy 28725815040.000008 # Energy for refresh commands per rank (pJ) 272system.physmem_1.actBackEnergy 8187694890 # Energy for active background per rank (pJ) 273system.physmem_1.preBackEnergy 1628706720 # Energy for precharge background per rank (pJ) 274system.physmem_1.actPowerDownEnergy 56919000150 # Energy for active power-down per rank (pJ) 275system.physmem_1.prePowerDownEnergy 51113801760 # Energy for precharge power-down per rank (pJ) 276system.physmem_1.selfRefreshEnergy 65311053315 # Energy for self refresh per rank (pJ) 277system.physmem_1.totalEnergy 213675530385 # Total energy per rank (pJ) 278system.physmem_1.averagePower 406.499389 # Core power per rank (mW) 279system.physmem_1.totalIdleTime 503405920500 # Total Idle time Per DRAM Rank 280system.physmem_1.memoryStateTime::IDLE 3197022000 # Time in different power states 281system.physmem_1.memoryStateTime::REF 12221338000 # Time in different power states 282system.physmem_1.memoryStateTime::SREF 245475081750 # Time in different power states 283system.physmem_1.memoryStateTime::PRE_PDN 133108808000 # Time in different power states 284system.physmem_1.memoryStateTime::ACT 6823284750 # Time in different power states 285system.physmem_1.memoryStateTime::ACT_PDN 124822316000 # Time in different power states 286system.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 287system.cpu.branchPred.lookups 147257105 # Number of BP lookups 288system.cpu.branchPred.condPredicted 98226689 # Number of conditional branches predicted 289system.cpu.branchPred.condIncorrect 1384794 # Number of conditional branches incorrect 290system.cpu.branchPred.BTBLookups 89640439 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 63297158 # Number of BTB hits 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 293system.cpu.branchPred.BTBHitPct 70.612280 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 19276056 # Number of times the RAS was used to get a target. 295system.cpu.branchPred.RASInCorrect 1321 # Number of incorrect RAS predictions. 296system.cpu.branchPred.indirectLookups 15995188 # Number of indirect predictor lookups. 297system.cpu.branchPred.indirectHits 15989428 # Number of indirect target hits. 298system.cpu.branchPred.indirectMisses 5760 # Number of indirect misses. 299system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. 300system.cpu_clk_domain.clock 500 # Clock period in ticks 301system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 302system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 311system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 312system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 313system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 314system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 315system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 316system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 317system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 320system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 321system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 322system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 323system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 324system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 325system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 326system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 327system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 328system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 329system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 330system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 331system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 332system.cpu.dtb.walker.walks 0 # Table walker walks requested 333system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.inst_hits 0 # ITB inst hits 341system.cpu.dtb.inst_misses 0 # ITB inst misses 342system.cpu.dtb.read_hits 0 # DTB read hits 343system.cpu.dtb.read_misses 0 # DTB read misses 344system.cpu.dtb.write_hits 0 # DTB write hits 345system.cpu.dtb.write_misses 0 # DTB write misses 346system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 347system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 348system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 349system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 350system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 351system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 352system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 353system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 354system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.dtb.read_accesses 0 # DTB read accesses 356system.cpu.dtb.write_accesses 0 # DTB write accesses 357system.cpu.dtb.inst_accesses 0 # ITB inst accesses 358system.cpu.dtb.hits 0 # DTB hits 359system.cpu.dtb.misses 0 # DTB misses 360system.cpu.dtb.accesses 0 # DTB accesses 361system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 362system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 371system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 372system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 373system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 374system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 375system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 376system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 377system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 378system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 379system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 380system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 381system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 382system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 383system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 384system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 386system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 387system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 388system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 389system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 390system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 391system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 392system.cpu.itb.walker.walks 0 # Table walker walks requested 393system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.inst_hits 0 # ITB inst hits 401system.cpu.itb.inst_misses 0 # ITB inst misses 402system.cpu.itb.read_hits 0 # DTB read hits 403system.cpu.itb.read_misses 0 # DTB read misses 404system.cpu.itb.write_hits 0 # DTB write hits 405system.cpu.itb.write_misses 0 # DTB write misses 406system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 407system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 408system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 409system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 410system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 411system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 412system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 413system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 414system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 415system.cpu.itb.read_accesses 0 # DTB read accesses 416system.cpu.itb.write_accesses 0 # DTB write accesses 417system.cpu.itb.inst_accesses 0 # ITB inst accesses 418system.cpu.itb.hits 0 # DTB hits 419system.cpu.itb.misses 0 # DTB misses 420system.cpu.itb.accesses 0 # DTB accesses 421system.cpu.workload.numSyscalls 673 # Number of system calls 422system.cpu.pwrStateResidencyTicks::ON 525647850500 # Cumulative time (in ticks) in various power states 423system.cpu.numCycles 1051295701 # number of cpu cycles simulated 424system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 425system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 426system.cpu.committedInsts 640655085 # Number of instructions committed 427system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed 428system.cpu.discardedOps 8620171 # Number of ops (including micro ops) which were discarded before commit 429system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 430system.cpu.cpi 1.640970 # CPI: cycles per instruction 431system.cpu.ipc 0.609396 # IPC: instructions per cycle 432system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 433system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction 434system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction 435system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction 436system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction 437system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction 438system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction 439system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction 440system.cpu.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction 441system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction 442system.cpu.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction 443system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction 444system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction 445system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction 446system.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction 447system.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction 448system.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction 449system.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction 450system.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction 451system.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction 452system.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction 453system.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction 454system.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction 455system.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction 456system.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction 457system.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction 458system.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction 459system.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction 460system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction 461system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction 462system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction 463system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction 464system.cpu.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction 465system.cpu.op_class_0::MemWrite 125149823 15.87% 98.62% # Class of committed instruction 466system.cpu.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction 467system.cpu.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction 468system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 469system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 470system.cpu.op_class_0::total 788730744 # Class of committed instruction 471system.cpu.tickCycles 955914808 # Number of cycles that the object actually ticked 472system.cpu.idleCycles 95380893 # Total number of cycles that the object has spent stopped 473system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 474system.cpu.dcache.tags.replacements 778100 # number of replacements 475system.cpu.dcache.tags.tagsinuse 4092.107040 # Cycle average of tags in use 476system.cpu.dcache.tags.total_refs 378447440 # Total number of references to valid blocks. 477system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. 478system.cpu.dcache.tags.avg_refs 483.826867 # Average number of references to valid blocks. 479system.cpu.dcache.tags.warmup_cycle 850680500 # Cycle when the warmup percentage was hit. 480system.cpu.dcache.tags.occ_blocks::cpu.data 4092.107040 # Average occupied blocks per requestor 481system.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy 482system.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy 483system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 484system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 485system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 486system.cpu.dcache.tags.age_task_id_blocks_1024::2 969 # Occupied blocks per task id 487system.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id 488system.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id 489system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 490system.cpu.dcache.tags.tag_accesses 759379166 # Number of tag accesses 491system.cpu.dcache.tags.data_accesses 759379166 # Number of data accesses 492system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 493system.cpu.dcache.ReadReq_hits::cpu.data 249618713 # number of ReadReq hits 494system.cpu.dcache.ReadReq_hits::total 249618713 # number of ReadReq hits 495system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits 496system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits 497system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits 498system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits 499system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits 500system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits 501system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits 502system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits 503system.cpu.dcache.demand_hits::cpu.data 378432478 # number of demand (read+write) hits 504system.cpu.dcache.demand_hits::total 378432478 # number of demand (read+write) hits 505system.cpu.dcache.overall_hits::cpu.data 378435962 # number of overall hits 506system.cpu.dcache.overall_hits::total 378435962 # number of overall hits 507system.cpu.dcache.ReadReq_misses::cpu.data 713192 # number of ReadReq misses 508system.cpu.dcache.ReadReq_misses::total 713192 # number of ReadReq misses 509system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses 510system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses 511system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses 512system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses 513system.cpu.dcache.demand_misses::cpu.data 850904 # number of demand (read+write) misses 514system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses 515system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses 516system.cpu.dcache.overall_misses::total 851045 # number of overall misses 517system.cpu.dcache.ReadReq_miss_latency::cpu.data 37264745000 # number of ReadReq miss cycles 518system.cpu.dcache.ReadReq_miss_latency::total 37264745000 # number of ReadReq miss cycles 519system.cpu.dcache.WriteReq_miss_latency::cpu.data 10940214000 # number of WriteReq miss cycles 520system.cpu.dcache.WriteReq_miss_latency::total 10940214000 # number of WriteReq miss cycles 521system.cpu.dcache.demand_miss_latency::cpu.data 48204959000 # number of demand (read+write) miss cycles 522system.cpu.dcache.demand_miss_latency::total 48204959000 # number of demand (read+write) miss cycles 523system.cpu.dcache.overall_miss_latency::cpu.data 48204959000 # number of overall miss cycles 524system.cpu.dcache.overall_miss_latency::total 48204959000 # number of overall miss cycles 525system.cpu.dcache.ReadReq_accesses::cpu.data 250331905 # number of ReadReq accesses(hits+misses) 526system.cpu.dcache.ReadReq_accesses::total 250331905 # number of ReadReq accesses(hits+misses) 527system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) 528system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) 529system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) 530system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses) 531system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) 532system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) 533system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) 534system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) 535system.cpu.dcache.demand_accesses::cpu.data 379283382 # number of demand (read+write) accesses 536system.cpu.dcache.demand_accesses::total 379283382 # number of demand (read+write) accesses 537system.cpu.dcache.overall_accesses::cpu.data 379287007 # number of overall (read+write) accesses 538system.cpu.dcache.overall_accesses::total 379287007 # number of overall (read+write) accesses 539system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002849 # miss rate for ReadReq accesses 540system.cpu.dcache.ReadReq_miss_rate::total 0.002849 # miss rate for ReadReq accesses 541system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses 542system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses 543system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses 544system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses 545system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 # miss rate for demand accesses 546system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses 547system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses 548system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses 549system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52250.649194 # average ReadReq miss latency 550system.cpu.dcache.ReadReq_avg_miss_latency::total 52250.649194 # average ReadReq miss latency 551system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79442.706518 # average WriteReq miss latency 552system.cpu.dcache.WriteReq_avg_miss_latency::total 79442.706518 # average WriteReq miss latency 553system.cpu.dcache.demand_avg_miss_latency::cpu.data 56651.465970 # average overall miss latency 554system.cpu.dcache.demand_avg_miss_latency::total 56651.465970 # average overall miss latency 555system.cpu.dcache.overall_avg_miss_latency::cpu.data 56642.080031 # average overall miss latency 556system.cpu.dcache.overall_avg_miss_latency::total 56642.080031 # average overall miss latency 557system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 558system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 559system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 560system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 561system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 562system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 563system.cpu.dcache.writebacks::writebacks 88684 # number of writebacks 564system.cpu.dcache.writebacks::total 88684 # number of writebacks 565system.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits 566system.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits 567system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits 568system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits 569system.cpu.dcache.demand_mshr_hits::cpu.data 68847 # number of demand (read+write) MSHR hits 570system.cpu.dcache.demand_mshr_hits::total 68847 # number of demand (read+write) MSHR hits 571system.cpu.dcache.overall_mshr_hits::cpu.data 68847 # number of overall MSHR hits 572system.cpu.dcache.overall_mshr_hits::total 68847 # number of overall MSHR hits 573system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712735 # number of ReadReq MSHR misses 574system.cpu.dcache.ReadReq_mshr_misses::total 712735 # number of ReadReq MSHR misses 575system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses 576system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses 577system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses 578system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses 579system.cpu.dcache.demand_mshr_misses::cpu.data 782057 # number of demand (read+write) MSHR misses 580system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses 581system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses 582system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses 583system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36543095500 # number of ReadReq MSHR miss cycles 584system.cpu.dcache.ReadReq_mshr_miss_latency::total 36543095500 # number of ReadReq MSHR miss cycles 585system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5486426000 # number of WriteReq MSHR miss cycles 586system.cpu.dcache.WriteReq_mshr_miss_latency::total 5486426000 # number of WriteReq MSHR miss cycles 587system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles 588system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles 589system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42029521500 # number of demand (read+write) MSHR miss cycles 590system.cpu.dcache.demand_mshr_miss_latency::total 42029521500 # number of demand (read+write) MSHR miss cycles 591system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42031323500 # number of overall MSHR miss cycles 592system.cpu.dcache.overall_mshr_miss_latency::total 42031323500 # number of overall MSHR miss cycles 593system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses 594system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses 595system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses 596system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses 597system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses 598system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses 599system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses 600system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses 601system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses 602system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses 603system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51271.644440 # average ReadReq mshr miss latency 604system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51271.644440 # average ReadReq mshr miss latency 605system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79144.081244 # average WriteReq mshr miss latency 606system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79144.081244 # average WriteReq mshr miss latency 607system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency 608system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency 609system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53742.273901 # average overall mshr miss latency 610system.cpu.dcache.demand_avg_mshr_miss_latency::total 53742.273901 # average overall mshr miss latency 611system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53735.027410 # average overall mshr miss latency 612system.cpu.dcache.overall_avg_mshr_miss_latency::total 53735.027410 # average overall mshr miss latency 613system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 614system.cpu.icache.tags.replacements 24889 # number of replacements 615system.cpu.icache.tags.tagsinuse 1710.890314 # Cycle average of tags in use 616system.cpu.icache.tags.total_refs 257795451 # Total number of references to valid blocks. 617system.cpu.icache.tags.sampled_refs 26639 # Sample count of references to valid blocks. 618system.cpu.icache.tags.avg_refs 9677.369684 # Average number of references to valid blocks. 619system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 620system.cpu.icache.tags.occ_blocks::cpu.inst 1710.890314 # Average occupied blocks per requestor 621system.cpu.icache.tags.occ_percent::cpu.inst 0.835396 # Average percentage of cache occupancy 622system.cpu.icache.tags.occ_percent::total 0.835396 # Average percentage of cache occupancy 623system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id 624system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id 625system.cpu.icache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id 626system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id 627system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id 628system.cpu.icache.tags.tag_accesses 515670821 # Number of tag accesses 629system.cpu.icache.tags.data_accesses 515670821 # Number of data accesses 630system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 631system.cpu.icache.ReadReq_hits::cpu.inst 257795451 # number of ReadReq hits 632system.cpu.icache.ReadReq_hits::total 257795451 # number of ReadReq hits 633system.cpu.icache.demand_hits::cpu.inst 257795451 # number of demand (read+write) hits 634system.cpu.icache.demand_hits::total 257795451 # number of demand (read+write) hits 635system.cpu.icache.overall_hits::cpu.inst 257795451 # number of overall hits 636system.cpu.icache.overall_hits::total 257795451 # number of overall hits 637system.cpu.icache.ReadReq_misses::cpu.inst 26640 # number of ReadReq misses 638system.cpu.icache.ReadReq_misses::total 26640 # number of ReadReq misses 639system.cpu.icache.demand_misses::cpu.inst 26640 # number of demand (read+write) misses 640system.cpu.icache.demand_misses::total 26640 # number of demand (read+write) misses 641system.cpu.icache.overall_misses::cpu.inst 26640 # number of overall misses 642system.cpu.icache.overall_misses::total 26640 # number of overall misses 643system.cpu.icache.ReadReq_miss_latency::cpu.inst 538801500 # number of ReadReq miss cycles 644system.cpu.icache.ReadReq_miss_latency::total 538801500 # number of ReadReq miss cycles 645system.cpu.icache.demand_miss_latency::cpu.inst 538801500 # number of demand (read+write) miss cycles 646system.cpu.icache.demand_miss_latency::total 538801500 # number of demand (read+write) miss cycles 647system.cpu.icache.overall_miss_latency::cpu.inst 538801500 # number of overall miss cycles 648system.cpu.icache.overall_miss_latency::total 538801500 # number of overall miss cycles 649system.cpu.icache.ReadReq_accesses::cpu.inst 257822091 # number of ReadReq accesses(hits+misses) 650system.cpu.icache.ReadReq_accesses::total 257822091 # number of ReadReq accesses(hits+misses) 651system.cpu.icache.demand_accesses::cpu.inst 257822091 # number of demand (read+write) accesses 652system.cpu.icache.demand_accesses::total 257822091 # number of demand (read+write) accesses 653system.cpu.icache.overall_accesses::cpu.inst 257822091 # number of overall (read+write) accesses 654system.cpu.icache.overall_accesses::total 257822091 # number of overall (read+write) accesses 655system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses 656system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses 657system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses 658system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses 659system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses 660system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses 661system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20225.281532 # average ReadReq miss latency 662system.cpu.icache.ReadReq_avg_miss_latency::total 20225.281532 # average ReadReq miss latency 663system.cpu.icache.demand_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency 664system.cpu.icache.demand_avg_miss_latency::total 20225.281532 # average overall miss latency 665system.cpu.icache.overall_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency 666system.cpu.icache.overall_avg_miss_latency::total 20225.281532 # average overall miss latency 667system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 668system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 669system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 670system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 671system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 672system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 673system.cpu.icache.writebacks::writebacks 24889 # number of writebacks 674system.cpu.icache.writebacks::total 24889 # number of writebacks 675system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26640 # number of ReadReq MSHR misses 676system.cpu.icache.ReadReq_mshr_misses::total 26640 # number of ReadReq MSHR misses 677system.cpu.icache.demand_mshr_misses::cpu.inst 26640 # number of demand (read+write) MSHR misses 678system.cpu.icache.demand_mshr_misses::total 26640 # number of demand (read+write) MSHR misses 679system.cpu.icache.overall_mshr_misses::cpu.inst 26640 # number of overall MSHR misses 680system.cpu.icache.overall_mshr_misses::total 26640 # number of overall MSHR misses 681system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 512162500 # number of ReadReq MSHR miss cycles 682system.cpu.icache.ReadReq_mshr_miss_latency::total 512162500 # number of ReadReq MSHR miss cycles 683system.cpu.icache.demand_mshr_miss_latency::cpu.inst 512162500 # number of demand (read+write) MSHR miss cycles 684system.cpu.icache.demand_mshr_miss_latency::total 512162500 # number of demand (read+write) MSHR miss cycles 685system.cpu.icache.overall_mshr_miss_latency::cpu.inst 512162500 # number of overall MSHR miss cycles 686system.cpu.icache.overall_mshr_miss_latency::total 512162500 # number of overall MSHR miss cycles 687system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses 688system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses 689system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses 690system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses 691system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses 692system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses 693system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19225.319069 # average ReadReq mshr miss latency 694system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19225.319069 # average ReadReq mshr miss latency 695system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency 696system.cpu.icache.demand_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency 697system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency 698system.cpu.icache.overall_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency 699system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 700system.cpu.l2cache.tags.replacements 258839 # number of replacements 701system.cpu.l2cache.tags.tagsinuse 32651.545544 # Cycle average of tags in use 702system.cpu.l2cache.tags.total_refs 1316953 # Total number of references to valid blocks. 703system.cpu.l2cache.tags.sampled_refs 291607 # Sample count of references to valid blocks. 704system.cpu.l2cache.tags.avg_refs 4.516191 # Average number of references to valid blocks. 705system.cpu.l2cache.tags.warmup_cycle 3958663000 # Cycle when the warmup percentage was hit. 706system.cpu.l2cache.tags.occ_blocks::writebacks 40.523746 # Average occupied blocks per requestor 707system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.271478 # Average occupied blocks per requestor 708system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.750321 # Average occupied blocks per requestor 709system.cpu.l2cache.tags.occ_percent::writebacks 0.001237 # Average percentage of cache occupancy 710system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002755 # Average percentage of cache occupancy 711system.cpu.l2cache.tags.occ_percent::cpu.data 0.992455 # Average percentage of cache occupancy 712system.cpu.l2cache.tags.occ_percent::total 0.996446 # Average percentage of cache occupancy 713system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 714system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id 715system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id 716system.cpu.l2cache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id 717system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2912 # Occupied blocks per task id 718system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29227 # Occupied blocks per task id 719system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 720system.cpu.l2cache.tags.tag_accesses 13160335 # Number of tag accesses 721system.cpu.l2cache.tags.data_accesses 13160335 # Number of data accesses 722system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 723system.cpu.l2cache.WritebackDirty_hits::writebacks 88684 # number of WritebackDirty hits 724system.cpu.l2cache.WritebackDirty_hits::total 88684 # number of WritebackDirty hits 725system.cpu.l2cache.WritebackClean_hits::writebacks 23557 # number of WritebackClean hits 726system.cpu.l2cache.WritebackClean_hits::total 23557 # number of WritebackClean hits 727system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits 728system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits 729system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24064 # number of ReadCleanReq hits 730system.cpu.l2cache.ReadCleanReq_hits::total 24064 # number of ReadCleanReq hits 731system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490275 # number of ReadSharedReq hits 732system.cpu.l2cache.ReadSharedReq_hits::total 490275 # number of ReadSharedReq hits 733system.cpu.l2cache.demand_hits::cpu.inst 24064 # number of demand (read+write) hits 734system.cpu.l2cache.demand_hits::cpu.data 493506 # number of demand (read+write) hits 735system.cpu.l2cache.demand_hits::total 517570 # number of demand (read+write) hits 736system.cpu.l2cache.overall_hits::cpu.inst 24064 # number of overall hits 737system.cpu.l2cache.overall_hits::cpu.data 493506 # number of overall hits 738system.cpu.l2cache.overall_hits::total 517570 # number of overall hits 739system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses 740system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses 741system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2576 # number of ReadCleanReq misses 742system.cpu.l2cache.ReadCleanReq_misses::total 2576 # number of ReadCleanReq misses 743system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses 744system.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses 745system.cpu.l2cache.demand_misses::cpu.inst 2576 # number of demand (read+write) misses 746system.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses 747system.cpu.l2cache.demand_misses::total 291266 # number of demand (read+write) misses 748system.cpu.l2cache.overall_misses::cpu.inst 2576 # number of overall misses 749system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses 750system.cpu.l2cache.overall_misses::total 291266 # number of overall misses 751system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5348515000 # number of ReadExReq miss cycles 752system.cpu.l2cache.ReadExReq_miss_latency::total 5348515000 # number of ReadExReq miss cycles 753system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 218253000 # number of ReadCleanReq miss cycles 754system.cpu.l2cache.ReadCleanReq_miss_latency::total 218253000 # number of ReadCleanReq miss cycles 755system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30325726000 # number of ReadSharedReq miss cycles 756system.cpu.l2cache.ReadSharedReq_miss_latency::total 30325726000 # number of ReadSharedReq miss cycles 757system.cpu.l2cache.demand_miss_latency::cpu.inst 218253000 # number of demand (read+write) miss cycles 758system.cpu.l2cache.demand_miss_latency::cpu.data 35674241000 # number of demand (read+write) miss cycles 759system.cpu.l2cache.demand_miss_latency::total 35892494000 # number of demand (read+write) miss cycles 760system.cpu.l2cache.overall_miss_latency::cpu.inst 218253000 # number of overall miss cycles 761system.cpu.l2cache.overall_miss_latency::cpu.data 35674241000 # number of overall miss cycles 762system.cpu.l2cache.overall_miss_latency::total 35892494000 # number of overall miss cycles 763system.cpu.l2cache.WritebackDirty_accesses::writebacks 88684 # number of WritebackDirty accesses(hits+misses) 764system.cpu.l2cache.WritebackDirty_accesses::total 88684 # number of WritebackDirty accesses(hits+misses) 765system.cpu.l2cache.WritebackClean_accesses::writebacks 23557 # number of WritebackClean accesses(hits+misses) 766system.cpu.l2cache.WritebackClean_accesses::total 23557 # number of WritebackClean accesses(hits+misses) 767system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) 768system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) 769system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26640 # number of ReadCleanReq accesses(hits+misses) 770system.cpu.l2cache.ReadCleanReq_accesses::total 26640 # number of ReadCleanReq accesses(hits+misses) 771system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712874 # number of ReadSharedReq accesses(hits+misses) 772system.cpu.l2cache.ReadSharedReq_accesses::total 712874 # number of ReadSharedReq accesses(hits+misses) 773system.cpu.l2cache.demand_accesses::cpu.inst 26640 # number of demand (read+write) accesses 774system.cpu.l2cache.demand_accesses::cpu.data 782196 # number of demand (read+write) accesses 775system.cpu.l2cache.demand_accesses::total 808836 # number of demand (read+write) accesses 776system.cpu.l2cache.overall_accesses::cpu.inst 26640 # number of overall (read+write) accesses 777system.cpu.l2cache.overall_accesses::cpu.data 782196 # number of overall (read+write) accesses 778system.cpu.l2cache.overall_accesses::total 808836 # number of overall (read+write) accesses 779system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses 780system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses 781system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096697 # miss rate for ReadCleanReq accesses 782system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096697 # miss rate for ReadCleanReq accesses 783system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses 784system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses 785system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096697 # miss rate for demand accesses 786system.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses 787system.cpu.l2cache.demand_miss_rate::total 0.360105 # miss rate for demand accesses 788system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096697 # miss rate for overall accesses 789system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses 790system.cpu.l2cache.overall_miss_rate::total 0.360105 # miss rate for overall accesses 791system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80926.525548 # average ReadExReq miss latency 792system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80926.525548 # average ReadExReq miss latency 793system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84725.543478 # average ReadCleanReq miss latency 794system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.543478 # average ReadCleanReq miss latency 795system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136234.780929 # average ReadSharedReq miss latency 796system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136234.780929 # average ReadSharedReq miss latency 797system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency 798system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency 799system.cpu.l2cache.demand_avg_miss_latency::total 123229.261225 # average overall miss latency 800system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency 801system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency 802system.cpu.l2cache.overall_avg_miss_latency::total 123229.261225 # average overall miss latency 803system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 804system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 805system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 806system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 807system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 808system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 809system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks 810system.cpu.l2cache.writebacks::total 66098 # number of writebacks 811system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits 812system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits 813system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 26 # number of ReadSharedReq MSHR hits 814system.cpu.l2cache.ReadSharedReq_mshr_hits::total 26 # number of ReadSharedReq MSHR hits 815system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits 816system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits 817system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits 818system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits 819system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits 820system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits 821system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses 822system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses 823system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2572 # number of ReadCleanReq MSHR misses 824system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2572 # number of ReadCleanReq MSHR misses 825system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses 826system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses 827system.cpu.l2cache.demand_mshr_misses::cpu.inst 2572 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses 829system.cpu.l2cache.demand_mshr_misses::total 291236 # number of demand (read+write) MSHR misses 830system.cpu.l2cache.overall_mshr_misses::cpu.inst 2572 # number of overall MSHR misses 831system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses 832system.cpu.l2cache.overall_mshr_misses::total 291236 # number of overall MSHR misses 833system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4687605000 # number of ReadExReq MSHR miss cycles 834system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4687605000 # number of ReadExReq MSHR miss cycles 835system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 192261000 # number of ReadCleanReq MSHR miss cycles 836system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 192261000 # number of ReadCleanReq MSHR miss cycles 837system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28098015500 # number of ReadSharedReq MSHR miss cycles 838system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28098015500 # number of ReadSharedReq MSHR miss cycles 839system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192261000 # number of demand (read+write) MSHR miss cycles 840system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32785620500 # number of demand (read+write) MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::total 32977881500 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192261000 # number of overall MSHR miss cycles 843system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32785620500 # number of overall MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::total 32977881500 # number of overall MSHR miss cycles 845system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses 846system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses 847system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for ReadCleanReq accesses 848system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096547 # mshr miss rate for ReadCleanReq accesses 849system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses 850system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses 851system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for demand accesses 852system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses 853system.cpu.l2cache.demand_mshr_miss_rate::total 0.360068 # mshr miss rate for demand accesses 854system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for overall accesses 855system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses 856system.cpu.l2cache.overall_mshr_miss_rate::total 0.360068 # mshr miss rate for overall accesses 857system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70926.525548 # average ReadExReq mshr miss latency 858system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70926.525548 # average ReadExReq mshr miss latency 859system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74751.555210 # average ReadCleanReq mshr miss latency 860system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74751.555210 # average ReadCleanReq mshr miss latency 861system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126241.797073 # average ReadSharedReq mshr miss latency 862system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126241.797073 # average ReadSharedReq mshr miss latency 863system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency 864system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency 865system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency 866system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency 867system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency 868system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency 869system.cpu.toL2Bus.snoop_filter.tot_requests 1611825 # Total number of requests made to the snoop filter. 870system.cpu.toL2Bus.snoop_filter.hit_single_requests 803048 # Number of requests hitting in the snoop filter with a single holder of the requested data. 871system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 872system.cpu.toL2Bus.snoop_filter.tot_snoops 2033 # Total number of snoops made to the snoop filter. 873system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2018 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 874system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 875system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 876system.cpu.toL2Bus.trans_dist::ReadResp 739513 # Transaction distribution 877system.cpu.toL2Bus.trans_dist::WritebackDirty 154782 # Transaction distribution 878system.cpu.toL2Bus.trans_dist::WritebackClean 24889 # Transaction distribution 879system.cpu.toL2Bus.trans_dist::CleanEvict 882157 # Transaction distribution 880system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution 881system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution 882system.cpu.toL2Bus.trans_dist::ReadCleanReq 26640 # Transaction distribution 883system.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution 884system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78168 # Packet count per connected master and slave (bytes) 885system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes) 886system.cpu.toL2Bus.pkt_count::total 2420660 # Packet count per connected master and slave (bytes) 887system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297792 # Cumulative packet size per connected master and slave (bytes) 888system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736320 # Cumulative packet size per connected master and slave (bytes) 889system.cpu.toL2Bus.pkt_size::total 59034112 # Cumulative packet size per connected master and slave (bytes) 890system.cpu.toL2Bus.snoops 258839 # Total snoops (count) 891system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) 892system.cpu.toL2Bus.snoop_fanout::samples 1067675 # Request fanout histogram 893system.cpu.toL2Bus.snoop_fanout::mean 0.005002 # Request fanout histogram 894system.cpu.toL2Bus.snoop_fanout::stdev 0.070750 # Request fanout histogram 895system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 896system.cpu.toL2Bus.snoop_fanout::0 1062349 99.50% 99.50% # Request fanout histogram 897system.cpu.toL2Bus.snoop_fanout::1 5311 0.50% 100.00% # Request fanout histogram 898system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram 899system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 900system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 901system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 902system.cpu.toL2Bus.snoop_fanout::total 1067675 # Request fanout histogram 903system.cpu.toL2Bus.reqLayer0.occupancy 919485500 # Layer occupancy (ticks) 904system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) 905system.cpu.toL2Bus.respLayer0.occupancy 39960496 # Layer occupancy (ticks) 906system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 907system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) 908system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) 909system.membus.snoop_filter.tot_requests 548040 # Total number of requests made to the snoop filter. 910system.membus.snoop_filter.hit_single_requests 256844 # Number of requests hitting in the snoop filter with a single holder of the requested data. 911system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 912system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 913system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 914system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 915system.membus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states 916system.membus.trans_dist::ReadResp 225144 # Transaction distribution 917system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution 918system.membus.trans_dist::CleanEvict 190707 # Transaction distribution 919system.membus.trans_dist::ReadExReq 66091 # Transaction distribution 920system.membus.trans_dist::ReadExResp 66091 # Transaction distribution 921system.membus.trans_dist::ReadSharedReq 225144 # Transaction distribution 922system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839275 # Packet count per connected master and slave (bytes) 923system.membus.pkt_count::total 839275 # Packet count per connected master and slave (bytes) 924system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22869312 # Cumulative packet size per connected master and slave (bytes) 925system.membus.pkt_size::total 22869312 # Cumulative packet size per connected master and slave (bytes) 926system.membus.snoops 0 # Total snoops (count) 927system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 928system.membus.snoop_fanout::samples 291235 # Request fanout histogram 929system.membus.snoop_fanout::mean 0 # Request fanout histogram 930system.membus.snoop_fanout::stdev 0 # Request fanout histogram 931system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 932system.membus.snoop_fanout::0 291235 100.00% 100.00% # Request fanout histogram 933system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 934system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 935system.membus.snoop_fanout::min_value 0 # Request fanout histogram 936system.membus.snoop_fanout::max_value 0 # Request fanout histogram 937system.membus.snoop_fanout::total 291235 # Request fanout histogram 938system.membus.reqLayer0.occupancy 917214500 # Layer occupancy (ticks) 939system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) 940system.membus.respLayer1.occupancy 1553534250 # Layer occupancy (ticks) 941system.membus.respLayer1.utilization 0.3 # Layer utilization (%) 942 943---------- End Simulation Statistics ---------- 944