stats.txt revision 10827
110515SN/A 210515SN/A---------- Begin Simulation Statistics ---------- 310827Sandreas.hansson@arm.comsim_seconds 47.526955 # Number of seconds simulated 410827Sandreas.hansson@arm.comsim_ticks 47526954967000 # Number of ticks simulated 510827Sandreas.hansson@arm.comfinal_tick 47526954967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 610515SN/Asim_freq 1000000000000 # Frequency of simulated ticks 710827Sandreas.hansson@arm.comhost_inst_rate 679404 # Simulator instruction rate (inst/s) 810827Sandreas.hansson@arm.comhost_op_rate 799114 # Simulator op (including micro ops) rate (op/s) 910827Sandreas.hansson@arm.comhost_tick_rate 36258651928 # Simulator tick rate (ticks/s) 1010827Sandreas.hansson@arm.comhost_mem_usage 756696 # Number of bytes of host memory used 1110827Sandreas.hansson@arm.comhost_seconds 1310.78 # Real time elapsed on the host 1210827Sandreas.hansson@arm.comsim_insts 890546366 # Number of instructions simulated 1310827Sandreas.hansson@arm.comsim_ops 1047459319 # Number of ops (including micro ops) simulated 1410515SN/Asystem.voltage_domain.voltage 1 # Voltage in Volts 1510515SN/Asystem.clk_domain.clock 1000 # Clock period in ticks 1610827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.dtb.walker 120896 # Number of bytes read from this memory 1710827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.itb.walker 123520 # Number of bytes read from this memory 1810827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.inst 3402100 # Number of bytes read from this memory 1910827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.data 13323656 # Number of bytes read from this memory 2010827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu0.l2cache.prefetcher 13846976 # Number of bytes read from this memory 2110827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.dtb.walker 139776 # Number of bytes read from this memory 2210827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.itb.walker 143808 # Number of bytes read from this memory 2310827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.inst 3041464 # Number of bytes read from this memory 2410827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.data 11124432 # Number of bytes read from this memory 2510827Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu1.l2cache.prefetcher 15361728 # Number of bytes read from this memory 2610827Sandreas.hansson@arm.comsystem.physmem.bytes_read::realview.ide 416704 # Number of bytes read from this memory 2710827Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 61045060 # Number of bytes read from this memory 2810827Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu0.inst 3402100 # Number of instructions bytes read from this memory 2910827Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu1.inst 3041464 # Number of instructions bytes read from this memory 3010827Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 6443564 # Number of instructions bytes read from this memory 3110827Sandreas.hansson@arm.comsystem.physmem.bytes_written::writebacks 78583104 # Number of bytes written to this memory 3210827Sandreas.hansson@arm.comsystem.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 3310585SN/Asystem.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 3410827Sandreas.hansson@arm.comsystem.physmem.bytes_written::total 78603688 # Number of bytes written to this memory 3510827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.dtb.walker 1889 # Number of read requests responded to by this memory 3610827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.itb.walker 1930 # Number of read requests responded to by this memory 3710827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.inst 93565 # Number of read requests responded to by this memory 3810827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.data 208195 # Number of read requests responded to by this memory 3910827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu0.l2cache.prefetcher 216359 # Number of read requests responded to by this memory 4010827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.dtb.walker 2184 # Number of read requests responded to by this memory 4110827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.itb.walker 2247 # Number of read requests responded to by this memory 4210827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.inst 47611 # Number of read requests responded to by this memory 4310827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.data 173832 # Number of read requests responded to by this memory 4410827Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu1.l2cache.prefetcher 240027 # Number of read requests responded to by this memory 4510827Sandreas.hansson@arm.comsystem.physmem.num_reads::realview.ide 6511 # Number of read requests responded to by this memory 4610827Sandreas.hansson@arm.comsystem.physmem.num_reads::total 994350 # Number of read requests responded to by this memory 4710827Sandreas.hansson@arm.comsystem.physmem.num_writes::writebacks 1227861 # Number of write requests responded to by this memory 4810827Sandreas.hansson@arm.comsystem.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 4910585SN/Asystem.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 5010827Sandreas.hansson@arm.comsystem.physmem.num_writes::total 1230435 # Number of write requests responded to by this memory 5110827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.dtb.walker 2544 # Total read bandwidth from this memory (bytes/s) 5210827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.itb.walker 2599 # Total read bandwidth from this memory (bytes/s) 5310827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.inst 71583 # Total read bandwidth from this memory (bytes/s) 5410827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.data 280339 # Total read bandwidth from this memory (bytes/s) 5510827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu0.l2cache.prefetcher 291350 # Total read bandwidth from this memory (bytes/s) 5610827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.dtb.walker 2941 # Total read bandwidth from this memory (bytes/s) 5710827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.itb.walker 3026 # Total read bandwidth from this memory (bytes/s) 5810827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.inst 63995 # Total read bandwidth from this memory (bytes/s) 5910827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.data 234066 # Total read bandwidth from this memory (bytes/s) 6010827Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu1.l2cache.prefetcher 323221 # Total read bandwidth from this memory (bytes/s) 6110827Sandreas.hansson@arm.comsystem.physmem.bw_read::realview.ide 8768 # Total read bandwidth from this memory (bytes/s) 6210827Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1284430 # Total read bandwidth from this memory (bytes/s) 6310827Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu0.inst 71583 # Instruction read bandwidth from this memory (bytes/s) 6410827Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu1.inst 63995 # Instruction read bandwidth from this memory (bytes/s) 6510827Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 135577 # Instruction read bandwidth from this memory (bytes/s) 6610827Sandreas.hansson@arm.comsystem.physmem.bw_write::writebacks 1653443 # Write bandwidth from this memory (bytes/s) 6710827Sandreas.hansson@arm.comsystem.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 6810585SN/Asystem.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 6910827Sandreas.hansson@arm.comsystem.physmem.bw_write::total 1653876 # Write bandwidth from this memory (bytes/s) 7010827Sandreas.hansson@arm.comsystem.physmem.bw_total::writebacks 1653443 # Total bandwidth to/from this memory (bytes/s) 7110827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.dtb.walker 2544 # Total bandwidth to/from this memory (bytes/s) 7210827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.itb.walker 2599 # Total bandwidth to/from this memory (bytes/s) 7310827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.inst 71583 # Total bandwidth to/from this memory (bytes/s) 7410827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.data 280772 # Total bandwidth to/from this memory (bytes/s) 7510827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu0.l2cache.prefetcher 291350 # Total bandwidth to/from this memory (bytes/s) 7610827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.dtb.walker 2941 # Total bandwidth to/from this memory (bytes/s) 7710827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.itb.walker 3026 # Total bandwidth to/from this memory (bytes/s) 7810827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.inst 63995 # Total bandwidth to/from this memory (bytes/s) 7910827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.data 234066 # Total bandwidth to/from this memory (bytes/s) 8010827Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu1.l2cache.prefetcher 323221 # Total bandwidth to/from this memory (bytes/s) 8110827Sandreas.hansson@arm.comsystem.physmem.bw_total::realview.ide 8768 # Total bandwidth to/from this memory (bytes/s) 8210827Sandreas.hansson@arm.comsystem.physmem.bw_total::total 2938306 # Total bandwidth to/from this memory (bytes/s) 8310827Sandreas.hansson@arm.comsystem.physmem.readReqs 994350 # Number of read requests accepted 8410827Sandreas.hansson@arm.comsystem.physmem.writeReqs 1902822 # Number of write requests accepted 8510827Sandreas.hansson@arm.comsystem.physmem.readBursts 994350 # Number of DRAM read bursts, including those serviced by the write queue 8610827Sandreas.hansson@arm.comsystem.physmem.writeBursts 1902822 # Number of DRAM write bursts, including those merged in the write queue 8710827Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 63617152 # Total number of bytes read from DRAM 8810827Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue 8910827Sandreas.hansson@arm.comsystem.physmem.bytesWritten 118663680 # Total number of bytes written to DRAM 9010827Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 61045060 # Total read bytes from the system interface side 9110827Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 121636456 # Total written bytes from the system interface side 9210827Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue 9310827Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 48679 # Number of DRAM write bursts merged with an existing one 9410827Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 115330 # Number of requests that are neither read nor write 9510827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::0 57482 # Per bank write bursts 9610827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::1 61474 # Per bank write bursts 9710827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 58055 # Per bank write bursts 9810827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 62815 # Per bank write bursts 9910827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::4 61744 # Per bank write bursts 10010827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 72443 # Per bank write bursts 10110827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 62137 # Per bank write bursts 10210827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 62898 # Per bank write bursts 10310827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 53757 # Per bank write bursts 10410827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 98485 # Per bank write bursts 10510827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 53699 # Per bank write bursts 10610827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 61424 # Per bank write bursts 10710827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 50178 # Per bank write bursts 10810827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::13 60766 # Per bank write bursts 10910827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 57507 # Per bank write bursts 11010827Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::15 59154 # Per bank write bursts 11110827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 114707 # Per bank write bursts 11210827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 119877 # Per bank write bursts 11310827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 118693 # Per bank write bursts 11410827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 118700 # Per bank write bursts 11510827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 118108 # Per bank write bursts 11610827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 125436 # Per bank write bursts 11710827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 113884 # Per bank write bursts 11810827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 116296 # Per bank write bursts 11910827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 112515 # Per bank write bursts 12010827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 116242 # Per bank write bursts 12110827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 112992 # Per bank write bursts 12210827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 118745 # Per bank write bursts 12310827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 107808 # Per bank write bursts 12410827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 111387 # Per bank write bursts 12510827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 114155 # Per bank write bursts 12610827Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 114575 # Per bank write bursts 12710515SN/Asystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 12810827Sandreas.hansson@arm.comsystem.physmem.numWrRetry 406 # Number of times write queue was full causing retry 12910827Sandreas.hansson@arm.comsystem.physmem.totGap 47526951912500 # Total gap between requests 13010515SN/Asystem.physmem.readPktSize::0 0 # Read request sizes (log2) 13110515SN/Asystem.physmem.readPktSize::1 0 # Read request sizes (log2) 13210515SN/Asystem.physmem.readPktSize::2 43195 # Read request sizes (log2) 13310827Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 25 # Read request sizes (log2) 13410515SN/Asystem.physmem.readPktSize::4 5 # Read request sizes (log2) 13510515SN/Asystem.physmem.readPktSize::5 0 # Read request sizes (log2) 13610827Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 951125 # Read request sizes (log2) 13710515SN/Asystem.physmem.writePktSize::0 0 # Write request sizes (log2) 13810515SN/Asystem.physmem.writePktSize::1 0 # Write request sizes (log2) 13910515SN/Asystem.physmem.writePktSize::2 2 # Write request sizes (log2) 14010827Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 2572 # Write request sizes (log2) 14110515SN/Asystem.physmem.writePktSize::4 0 # Write request sizes (log2) 14210515SN/Asystem.physmem.writePktSize::5 0 # Write request sizes (log2) 14310827Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 1900248 # Write request sizes (log2) 14410827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::0 698116 # What read queue length does an incoming req see 14510827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 83658 # What read queue length does an incoming req see 14610827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::2 42191 # What read queue length does an incoming req see 14710827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::3 36638 # What read queue length does an incoming req see 14810827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::4 31495 # What read queue length does an incoming req see 14910827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 28119 # What read queue length does an incoming req see 15010827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 24839 # What read queue length does an incoming req see 15110827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 21358 # What read queue length does an incoming req see 15210827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 17624 # What read queue length does an incoming req see 15310827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 4596 # What read queue length does an incoming req see 15410827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 1385 # What read queue length does an incoming req see 15510827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 1018 # What read queue length does an incoming req see 15610827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 839 # What read queue length does an incoming req see 15710827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 651 # What read queue length does an incoming req see 15810827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 464 # What read queue length does an incoming req see 15910827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 363 # What read queue length does an incoming req see 16010827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see 16110827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 218 # What read queue length does an incoming req see 16210827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see 16310827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see 16410827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 16510827Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 16610628SN/Asystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 16710628SN/Asystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 16810628SN/Asystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 16910628SN/Asystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 17010515SN/Asystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 17110515SN/Asystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 17210515SN/Asystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 17310515SN/Asystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 17410515SN/Asystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 17510515SN/Asystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 17610515SN/Asystem.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 17710515SN/Asystem.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 17810515SN/Asystem.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 17910515SN/Asystem.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 18010515SN/Asystem.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 18110515SN/Asystem.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 18210515SN/Asystem.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 18310515SN/Asystem.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 18410515SN/Asystem.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 18510515SN/Asystem.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 18610515SN/Asystem.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 18710515SN/Asystem.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 18810515SN/Asystem.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 18910515SN/Asystem.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 19010515SN/Asystem.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 19110827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 55966 # What write queue length does an incoming req see 19210827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 69244 # What write queue length does an incoming req see 19310827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 86453 # What write queue length does an incoming req see 19410827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 95710 # What write queue length does an incoming req see 19510827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 99723 # What write queue length does an incoming req see 19610827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 98450 # What write queue length does an incoming req see 19710827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 98652 # What write queue length does an incoming req see 19810827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 98653 # What write queue length does an incoming req see 19910827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 101180 # What write queue length does an incoming req see 20010827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 101256 # What write queue length does an incoming req see 20110827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 102685 # What write queue length does an incoming req see 20210827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 108850 # What write queue length does an incoming req see 20310827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 104999 # What write queue length does an incoming req see 20410827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 104785 # What write queue length does an incoming req see 20510827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 118151 # What write queue length does an incoming req see 20610827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 108223 # What write queue length does an incoming req see 20710827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 102687 # What write queue length does an incoming req see 20810827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 99179 # What write queue length does an incoming req see 20910827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 6890 # What write queue length does an incoming req see 21010827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 5415 # What write queue length does an incoming req see 21110827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 5566 # What write queue length does an incoming req see 21210827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 6838 # What write queue length does an incoming req see 21310827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 6775 # What write queue length does an incoming req see 21410827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 6308 # What write queue length does an incoming req see 21510827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 6158 # What write queue length does an incoming req see 21610827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 7224 # What write queue length does an incoming req see 21710827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 5430 # What write queue length does an incoming req see 21810827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 4899 # What write queue length does an incoming req see 21910827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 4456 # What write queue length does an incoming req see 22010827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 5091 # What write queue length does an incoming req see 22110827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 4051 # What write queue length does an incoming req see 22210827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 3523 # What write queue length does an incoming req see 22310827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 3763 # What write queue length does an incoming req see 22410827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 2982 # What write queue length does an incoming req see 22510827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 2416 # What write queue length does an incoming req see 22610827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 1572 # What write queue length does an incoming req see 22710827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 1266 # What write queue length does an incoming req see 22810827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 928 # What write queue length does an incoming req see 22910827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 971 # What write queue length does an incoming req see 23010827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 818 # What write queue length does an incoming req see 23110827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 686 # What write queue length does an incoming req see 23210827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 685 # What write queue length does an incoming req see 23310827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 630 # What write queue length does an incoming req see 23410827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 505 # What write queue length does an incoming req see 23510827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 480 # What write queue length does an incoming req see 23610827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 450 # What write queue length does an incoming req see 23710827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 474 # What write queue length does an incoming req see 23810827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 421 # What write queue length does an incoming req see 23910827Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 1611 # What write queue length does an incoming req see 24010827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::samples 1054851 # Bytes accessed per row activation 24110827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 172.802142 # Bytes accessed per row activation 24210827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 106.115345 # Bytes accessed per row activation 24310827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 242.100455 # Bytes accessed per row activation 24410827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::0-127 681651 64.62% 64.62% # Bytes accessed per row activation 24510827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::128-255 201380 19.09% 83.71% # Bytes accessed per row activation 24610827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::256-383 48895 4.64% 88.35% # Bytes accessed per row activation 24710827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::384-511 24340 2.31% 90.65% # Bytes accessed per row activation 24810827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::512-639 17755 1.68% 92.34% # Bytes accessed per row activation 24910827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::640-767 11649 1.10% 93.44% # Bytes accessed per row activation 25010827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::768-895 8558 0.81% 94.25% # Bytes accessed per row activation 25110827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::896-1023 7940 0.75% 95.01% # Bytes accessed per row activation 25210827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::1024-1151 52683 4.99% 100.00% # Bytes accessed per row activation 25310827Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::total 1054851 # Bytes accessed per row activation 25410827Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::samples 92018 # Reads before turning the bus around for writes 25510827Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::mean 10.802300 # Reads before turning the bus around for writes 25610827Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::stdev 106.341779 # Reads before turning the bus around for writes 25710827Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::0-1023 92015 100.00% 100.00% # Reads before turning the bus around for writes 25810827Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 25910585SN/Asystem.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 26010628SN/Asystem.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 26110827Sandreas.hansson@arm.comsystem.physmem.rdPerTurnAround::total 92018 # Reads before turning the bus around for writes 26210827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::samples 92018 # Writes before turning the bus around for reads 26310827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::mean 20.149536 # Writes before turning the bus around for reads 26410827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::gmean 18.827281 # Writes before turning the bus around for reads 26510827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::stdev 17.009129 # Writes before turning the bus around for reads 26610827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::16-31 90131 97.95% 97.95% # Writes before turning the bus around for reads 26710827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::32-47 760 0.83% 98.78% # Writes before turning the bus around for reads 26810827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::48-63 32 0.03% 98.81% # Writes before turning the bus around for reads 26910827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::64-79 41 0.04% 98.85% # Writes before turning the bus around for reads 27010827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::80-95 142 0.15% 99.01% # Writes before turning the bus around for reads 27110827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::96-111 182 0.20% 99.21% # Writes before turning the bus around for reads 27210827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::112-127 347 0.38% 99.58% # Writes before turning the bus around for reads 27310827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::128-143 116 0.13% 99.71% # Writes before turning the bus around for reads 27410827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::144-159 35 0.04% 99.75% # Writes before turning the bus around for reads 27510827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads 27610827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::176-191 63 0.07% 99.83% # Writes before turning the bus around for reads 27710827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::192-207 31 0.03% 99.86% # Writes before turning the bus around for reads 27810827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::208-223 15 0.02% 99.88% # Writes before turning the bus around for reads 27910827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::224-239 6 0.01% 99.89% # Writes before turning the bus around for reads 28010827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::240-255 1 0.00% 99.89% # Writes before turning the bus around for reads 28110827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::256-271 4 0.00% 99.89% # Writes before turning the bus around for reads 28210827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::272-287 5 0.01% 99.90% # Writes before turning the bus around for reads 28310827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads 28410827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads 28510827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::320-335 16 0.02% 99.93% # Writes before turning the bus around for reads 28610827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads 28710827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::352-367 24 0.03% 99.97% # Writes before turning the bus around for reads 28810827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads 28910827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads 29010827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads 29110827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads 29210827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::432-447 1 0.00% 99.98% # Writes before turning the bus around for reads 29310827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::448-463 1 0.00% 99.98% # Writes before turning the bus around for reads 29410827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads 29510827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::480-495 1 0.00% 99.99% # Writes before turning the bus around for reads 29610827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::496-511 1 0.00% 99.99% # Writes before turning the bus around for reads 29710827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::512-527 1 0.00% 99.99% # Writes before turning the bus around for reads 29810827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads 29910827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads 30010827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::560-575 2 0.00% 100.00% # Writes before turning the bus around for reads 30110827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::576-591 2 0.00% 100.00% # Writes before turning the bus around for reads 30210827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads 30310827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads 30410827Sandreas.hansson@arm.comsystem.physmem.wrPerTurnAround::total 92018 # Writes before turning the bus around for reads 30510827Sandreas.hansson@arm.comsystem.physmem.totQLat 36585898476 # Total ticks spent queuing 30610827Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 55223735976 # Total ticks spent from burst creation until serviced by the DRAM 30710827Sandreas.hansson@arm.comsystem.physmem.totBusLat 4970090000 # Total ticks spent in databus transfers 30810827Sandreas.hansson@arm.comsystem.physmem.avgQLat 36806.07 # Average queueing delay per DRAM burst 30910515SN/Asystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 31010827Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 55556.07 # Average memory access latency per DRAM burst 31110827Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s 31210827Sandreas.hansson@arm.comsystem.physmem.avgWrBW 2.50 # Average achieved write bandwidth in MiByte/s 31310827Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s 31410827Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 2.56 # Average system write bandwidth in MiByte/s 31510515SN/Asystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 31610827Sandreas.hansson@arm.comsystem.physmem.busUtil 0.03 # Data bus utilization in percentage 31710515SN/Asystem.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 31810628SN/Asystem.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 31910827Sandreas.hansson@arm.comsystem.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing 32010827Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing 32110827Sandreas.hansson@arm.comsystem.physmem.readRowHits 744165 # Number of row buffer hits during reads 32210827Sandreas.hansson@arm.comsystem.physmem.writeRowHits 1049121 # Number of row buffer hits during writes 32310827Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 74.86 # Row buffer hit rate for reads 32410827Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate 56.58 # Row buffer hit rate for writes 32510827Sandreas.hansson@arm.comsystem.physmem.avgGap 16404601.42 # Average gap between requests 32610827Sandreas.hansson@arm.comsystem.physmem.pageHitRate 62.96 # Row buffer hit rate, read and write combined 32710827Sandreas.hansson@arm.comsystem.physmem_0.actEnergy 4105851120 # Energy for activate commands per rank (pJ) 32810827Sandreas.hansson@arm.comsystem.physmem_0.preEnergy 2240295750 # Energy for precharge commands per rank (pJ) 32910827Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 3892535400 # Energy for read commands per rank (pJ) 33010827Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 6128142480 # Energy for write commands per rank (pJ) 33110827Sandreas.hansson@arm.comsystem.physmem_0.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ) 33210827Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 1214897373855 # Energy for active background per rank (pJ) 33310827Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 27450471155250 # Energy for precharge background per rank (pJ) 33410827Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 31785964742895 # Total energy per rank (pJ) 33510827Sandreas.hansson@arm.comsystem.physmem_0.averagePower 668.798736 # Core power per rank (mW) 33610827Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::IDLE 45665609957576 # Time in different power states 33710827Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::REF 1587029340000 # Time in different power states 33810628SN/Asystem.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 33910827Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 274315218424 # Time in different power states 34010628SN/Asystem.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 34110827Sandreas.hansson@arm.comsystem.physmem_1.actEnergy 3868822440 # Energy for activate commands per rank (pJ) 34210827Sandreas.hansson@arm.comsystem.physmem_1.preEnergy 2110964625 # Energy for precharge commands per rank (pJ) 34310827Sandreas.hansson@arm.comsystem.physmem_1.readEnergy 3860766000 # Energy for read commands per rank (pJ) 34410827Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 5886555120 # Energy for write commands per rank (pJ) 34510827Sandreas.hansson@arm.comsystem.physmem_1.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ) 34610827Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 1202076105075 # Energy for active background per rank (pJ) 34710827Sandreas.hansson@arm.comsystem.physmem_1.preBackEnergy 27461717882250 # Energy for precharge background per rank (pJ) 34810827Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 31783750484550 # Total energy per rank (pJ) 34910827Sandreas.hansson@arm.comsystem.physmem_1.averagePower 668.752146 # Core power per rank (mW) 35010827Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::IDLE 45684364167822 # Time in different power states 35110827Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::REF 1587029340000 # Time in different power states 35210628SN/Asystem.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 35310827Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 255557515928 # Time in different power states 35410628SN/Asystem.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 35510515SN/Asystem.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 35610515SN/Asystem.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 35710515SN/Asystem.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 35810515SN/Asystem.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 35910515SN/Asystem.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 36010515SN/Asystem.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 36110515SN/Asystem.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 36210515SN/Asystem.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 36310515SN/Asystem.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 36410515SN/Asystem.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 36510515SN/Asystem.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 36610515SN/Asystem.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 36710515SN/Asystem.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 36810515SN/Asystem.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 36910515SN/Asystem.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 37010515SN/Asystem.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 37110515SN/Asystem.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 37210515SN/Asystem.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 37310515SN/Asystem.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 37410515SN/Asystem.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 37510515SN/Asystem.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 37610515SN/Asystem.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 37710515SN/Asystem.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 37810515SN/Asystem.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 37910515SN/Asystem.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 38010515SN/Asystem.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 38110535SN/Asystem.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 38210535SN/Asystem.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 38310535SN/Asystem.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 38410726SN/Asystem.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 38510726SN/Asystem.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 38610726SN/Asystem.cf0.dma_write_txs 1670 # Number of DMA write transactions. 38710515SN/Asystem.cpu_clk_domain.clock 500 # Clock period in ticks 38810628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 38910628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 39010628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39110628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 39210628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 39310628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39410628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 39510628SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 39610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 39710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 39810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 39910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 40010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 40110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 40210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 40310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 40410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 40510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 40610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 40710535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 40810535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 40910535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 41010535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 41110535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 41210535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 41310535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 41410535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 41510535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 41610535SN/Asystem.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 41710827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walks 101631 # Table walker walks requested 41810827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLong 101631 # Table walker walks initiated with long descriptors 41910827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9048 # Level at which table walker walks with long descriptors terminate 42010827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76119 # Level at which table walker walks with long descriptors terminate 42110827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting 42210827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::samples 101620 # Table walker wait (enqueue to first request) latency 42310827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::mean 0.113167 # Table walker wait (enqueue to first request) latency 42410827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::stdev 36.075158 # Table walker wait (enqueue to first request) latency 42510827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::0-1023 101619 100.00% 100.00% # Table walker wait (enqueue to first request) latency 42610827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 42710827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkWaitTime::total 101620 # Table walker wait (enqueue to first request) latency 42810827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::samples 85178 # Table walker service (enqueue to completion) latency 42910827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::mean 19101.889572 # Table walker service (enqueue to completion) latency 43010827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::gmean 17045.635811 # Table walker service (enqueue to completion) latency 43110827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::stdev 15664.933997 # Table walker service (enqueue to completion) latency 43210827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::0-65535 84047 98.67% 98.67% # Table walker service (enqueue to completion) latency 43310827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::65536-131071 953 1.12% 99.79% # Table walker service (enqueue to completion) latency 43410827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::131072-196607 46 0.05% 99.85% # Table walker service (enqueue to completion) latency 43510827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::196608-262143 63 0.07% 99.92% # Table walker service (enqueue to completion) latency 43610827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::262144-327679 53 0.06% 99.98% # Table walker service (enqueue to completion) latency 43710827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 43810827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 43910628SN/Asystem.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44010628SN/Asystem.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44110827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44210827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 44310827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkCompletionTime::total 85178 # Table walker service (enqueue to completion) latency 44410827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::samples 6479942056 # Table walker pending requests distribution 44510827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::mean 1.123756 # Table walker pending requests distribution 44610827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::0 -801929896 -12.38% -12.38% # Table walker pending requests distribution 44710827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::1 7281871952 112.38% 100.00% # Table walker pending requests distribution 44810827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walksPending::total 6479942056 # Table walker pending requests distribution 44910827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::4K 76120 89.38% 89.38% # Table walker page sizes translated 45010827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::2M 9048 10.62% 100.00% # Table walker page sizes translated 45110827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkPageSizes::total 85168 # Table walker page sizes translated 45210827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101631 # Table walker requests started/completed, data/inst 45310628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45410827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101631 # Table walker requests started/completed, data/inst 45510827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85168 # Table walker requests started/completed, data/inst 45610628SN/Asystem.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45710827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85168 # Table walker requests started/completed, data/inst 45810827Sandreas.hansson@arm.comsystem.cpu0.dtb.walker.walkRequestOrigin::total 186799 # Table walker requests started/completed, data/inst 45910535SN/Asystem.cpu0.dtb.inst_hits 0 # ITB inst hits 46010535SN/Asystem.cpu0.dtb.inst_misses 0 # ITB inst misses 46110827Sandreas.hansson@arm.comsystem.cpu0.dtb.read_hits 83767358 # DTB read hits 46210827Sandreas.hansson@arm.comsystem.cpu0.dtb.read_misses 74871 # DTB read misses 46310827Sandreas.hansson@arm.comsystem.cpu0.dtb.write_hits 75914688 # DTB write hits 46410827Sandreas.hansson@arm.comsystem.cpu0.dtb.write_misses 26760 # DTB write misses 46510535SN/Asystem.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 46610535SN/Asystem.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 46710827Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID 46810827Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID 46910827Sandreas.hansson@arm.comsystem.cpu0.dtb.flush_entries 32159 # Number of entries that have been flushed from TLB 47010535SN/Asystem.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 47110827Sandreas.hansson@arm.comsystem.cpu0.dtb.prefetch_faults 3900 # Number of TLB faults due to prefetch 47210535SN/Asystem.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 47310827Sandreas.hansson@arm.comsystem.cpu0.dtb.perms_faults 8424 # Number of TLB faults due to permissions restrictions 47410827Sandreas.hansson@arm.comsystem.cpu0.dtb.read_accesses 83842229 # DTB read accesses 47510827Sandreas.hansson@arm.comsystem.cpu0.dtb.write_accesses 75941448 # DTB write accesses 47610535SN/Asystem.cpu0.dtb.inst_accesses 0 # ITB inst accesses 47710827Sandreas.hansson@arm.comsystem.cpu0.dtb.hits 159682046 # DTB hits 47810827Sandreas.hansson@arm.comsystem.cpu0.dtb.misses 101631 # DTB misses 47910827Sandreas.hansson@arm.comsystem.cpu0.dtb.accesses 159783677 # DTB accesses 48010628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 48110628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 48210628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 48310628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 48410628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 48510628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48610628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 48710628SN/Asystem.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 49110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 49210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 49410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 49710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 49810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 49910535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 50010535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 50110535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 50210535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 50310535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 50410535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 50510535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 50610535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 50710535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 50810535SN/Asystem.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 50910827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walks 55722 # Table walker walks requested 51010827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLong 55722 # Table walker walks initiated with long descriptors 51110827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level2 543 # Level at which table walker walks with long descriptors terminate 51210827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walksLongTerminationLevel::Level3 49598 # Level at which table walker walks with long descriptors terminate 51310827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::samples 55722 # Table walker wait (enqueue to first request) latency 51410827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::0 55722 100.00% 100.00% # Table walker wait (enqueue to first request) latency 51510827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkWaitTime::total 55722 # Table walker wait (enqueue to first request) latency 51610827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::samples 50141 # Table walker service (enqueue to completion) latency 51710827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::mean 22337.612912 # Table walker service (enqueue to completion) latency 51810827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::gmean 19289.783493 # Table walker service (enqueue to completion) latency 51910827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::stdev 21041.520478 # Table walker service (enqueue to completion) latency 52010827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::0-65535 48785 97.30% 97.30% # Table walker service (enqueue to completion) latency 52110827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::65536-131071 1144 2.28% 99.58% # Table walker service (enqueue to completion) latency 52210827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::131072-196607 57 0.11% 99.69% # Table walker service (enqueue to completion) latency 52310827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::196608-262143 79 0.16% 99.85% # Table walker service (enqueue to completion) latency 52410827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::262144-327679 56 0.11% 99.96% # Table walker service (enqueue to completion) latency 52510827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.03% 99.99% # Table walker service (enqueue to completion) latency 52610827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 52710827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 52810827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 52910827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkCompletionTime::total 50141 # Table walker service (enqueue to completion) latency 53010726SN/Asystem.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution 53110726SN/Asystem.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution 53210726SN/Asystem.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution 53310827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::4K 49598 98.92% 98.92% # Table walker page sizes translated 53410827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::2M 543 1.08% 100.00% # Table walker page sizes translated 53510827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkPageSizes::total 50141 # Table walker page sizes translated 53610628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 53710827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55722 # Table walker requests started/completed, data/inst 53810827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Requested::total 55722 # Table walker requests started/completed, data/inst 53910628SN/Asystem.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 54010827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50141 # Table walker requests started/completed, data/inst 54110827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin_Completed::total 50141 # Table walker requests started/completed, data/inst 54210827Sandreas.hansson@arm.comsystem.cpu0.itb.walker.walkRequestOrigin::total 105863 # Table walker requests started/completed, data/inst 54310827Sandreas.hansson@arm.comsystem.cpu0.itb.inst_hits 444122432 # ITB inst hits 54410827Sandreas.hansson@arm.comsystem.cpu0.itb.inst_misses 55722 # ITB inst misses 54510535SN/Asystem.cpu0.itb.read_hits 0 # DTB read hits 54610535SN/Asystem.cpu0.itb.read_misses 0 # DTB read misses 54710535SN/Asystem.cpu0.itb.write_hits 0 # DTB write hits 54810535SN/Asystem.cpu0.itb.write_misses 0 # DTB write misses 54910535SN/Asystem.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 55010535SN/Asystem.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55110827Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID 55210827Sandreas.hansson@arm.comsystem.cpu0.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID 55310827Sandreas.hansson@arm.comsystem.cpu0.itb.flush_entries 22526 # Number of entries that have been flushed from TLB 55410535SN/Asystem.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 55510535SN/Asystem.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 55610535SN/Asystem.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 55710535SN/Asystem.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 55810535SN/Asystem.cpu0.itb.read_accesses 0 # DTB read accesses 55910535SN/Asystem.cpu0.itb.write_accesses 0 # DTB write accesses 56010827Sandreas.hansson@arm.comsystem.cpu0.itb.inst_accesses 444178154 # ITB inst accesses 56110827Sandreas.hansson@arm.comsystem.cpu0.itb.hits 444122432 # DTB hits 56210827Sandreas.hansson@arm.comsystem.cpu0.itb.misses 55722 # DTB misses 56310827Sandreas.hansson@arm.comsystem.cpu0.itb.accesses 444178154 # DTB accesses 56410827Sandreas.hansson@arm.comsystem.cpu0.numCycles 95053909934 # number of cpu cycles simulated 56510535SN/Asystem.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 56610535SN/Asystem.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 56710827Sandreas.hansson@arm.comsystem.cpu0.committedInsts 443872382 # Number of instructions committed 56810827Sandreas.hansson@arm.comsystem.cpu0.committedOps 521690846 # Number of ops (including micro ops) committed 56910827Sandreas.hansson@arm.comsystem.cpu0.num_int_alu_accesses 479475231 # Number of integer alu accesses 57010827Sandreas.hansson@arm.comsystem.cpu0.num_fp_alu_accesses 421225 # Number of float alu accesses 57110827Sandreas.hansson@arm.comsystem.cpu0.num_func_calls 26535732 # number of times a function call or return occured 57210827Sandreas.hansson@arm.comsystem.cpu0.num_conditional_control_insts 67239811 # number of instructions that are conditional controls 57310827Sandreas.hansson@arm.comsystem.cpu0.num_int_insts 479475231 # number of integer instructions 57410827Sandreas.hansson@arm.comsystem.cpu0.num_fp_insts 421225 # number of float instructions 57510827Sandreas.hansson@arm.comsystem.cpu0.num_int_register_reads 693782505 # number of times the integer registers were read 57610827Sandreas.hansson@arm.comsystem.cpu0.num_int_register_writes 380162379 # number of times the integer registers were written 57710827Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_reads 701849 # number of times the floating registers were read 57810827Sandreas.hansson@arm.comsystem.cpu0.num_fp_register_writes 304628 # number of times the floating registers were written 57910827Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_reads 115037577 # number of times the CC registers were read 58010827Sandreas.hansson@arm.comsystem.cpu0.num_cc_register_writes 114748059 # number of times the CC registers were written 58110827Sandreas.hansson@arm.comsystem.cpu0.num_mem_refs 159672530 # number of memory refs 58210827Sandreas.hansson@arm.comsystem.cpu0.num_load_insts 83761106 # Number of load instructions 58310827Sandreas.hansson@arm.comsystem.cpu0.num_store_insts 75911424 # Number of store instructions 58410827Sandreas.hansson@arm.comsystem.cpu0.num_idle_cycles 93959856753.206024 # Number of idle cycles 58510827Sandreas.hansson@arm.comsystem.cpu0.num_busy_cycles 1094053180.793977 # Number of busy cycles 58610827Sandreas.hansson@arm.comsystem.cpu0.not_idle_fraction 0.011510 # Percentage of non-idle cycles 58710827Sandreas.hansson@arm.comsystem.cpu0.idle_fraction 0.988490 # Percentage of idle cycles 58810827Sandreas.hansson@arm.comsystem.cpu0.Branches 99058393 # Number of branches fetched 58910827Sandreas.hansson@arm.comsystem.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 59010827Sandreas.hansson@arm.comsystem.cpu0.op_class::IntAlu 361081858 69.17% 69.17% # Class of executed instruction 59110827Sandreas.hansson@arm.comsystem.cpu0.op_class::IntMult 1125018 0.22% 69.39% # Class of executed instruction 59210827Sandreas.hansson@arm.comsystem.cpu0.op_class::IntDiv 61306 0.01% 69.40% # Class of executed instruction 59310827Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 59410827Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 59510827Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 59610827Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 59710827Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 59810827Sandreas.hansson@arm.comsystem.cpu0.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 59910827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 60010827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 60110827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 60210827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 60310827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 60410827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 60510827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 60610827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 60710827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 60810827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 60910827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 61010827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 61110827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 61210827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 61310827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 61410827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 61510827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMisc 43308 0.01% 69.41% # Class of executed instruction 61610827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 61710827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 61810827Sandreas.hansson@arm.comsystem.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 61910827Sandreas.hansson@arm.comsystem.cpu0.op_class::MemRead 83761106 16.05% 85.46% # Class of executed instruction 62010827Sandreas.hansson@arm.comsystem.cpu0.op_class::MemWrite 75911424 14.54% 100.00% # Class of executed instruction 62110535SN/Asystem.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 62210535SN/Asystem.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 62310827Sandreas.hansson@arm.comsystem.cpu0.op_class::total 521984020 # Class of executed instruction 62410535SN/Asystem.cpu0.kern.inst.arm 0 # number of arm instructions executed 62510827Sandreas.hansson@arm.comsystem.cpu0.kern.inst.quiesce 5106 # number of quiesce instructions executed 62610827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.replacements 5414405 # number of replacements 62710827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tagsinuse 480.206026 # Cycle average of tags in use 62810827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.total_refs 154030593 # Total number of references to valid blocks. 62910827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.sampled_refs 5414914 # Sample count of references to valid blocks. 63010827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.avg_refs 28.445621 # Average number of references to valid blocks. 63110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.warmup_cycle 4071814500 # Cycle when the warmup percentage was hit. 63210827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_blocks::cpu0.data 480.206026 # Average occupied blocks per requestor 63310827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::cpu0.data 0.937902 # Average percentage of cache occupancy 63410827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_percent::total 0.937902 # Average percentage of cache occupancy 63510827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 63610827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 63710827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id 63810827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id 63910827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 64010827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.tag_accesses 324790756 # Number of tag accesses 64110827Sandreas.hansson@arm.comsystem.cpu0.dcache.tags.data_accesses 324790756 # Number of data accesses 64210827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::cpu0.data 77996551 # number of ReadReq hits 64310827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_hits::total 77996551 # number of ReadReq hits 64410827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::cpu0.data 71694037 # number of WriteReq hits 64510827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_hits::total 71694037 # number of WriteReq hits 64610827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::cpu0.data 187802 # number of SoftPFReq hits 64710827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_hits::total 187802 # number of SoftPFReq hits 64810827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 131287 # number of WriteInvalidateReq hits 64910827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_hits::total 131287 # number of WriteInvalidateReq hits 65010827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1831493 # number of LoadLockedReq hits 65110827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_hits::total 1831493 # number of LoadLockedReq hits 65210827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787873 # number of StoreCondReq hits 65310827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_hits::total 1787873 # number of StoreCondReq hits 65410827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::cpu0.data 149690588 # number of demand (read+write) hits 65510827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_hits::total 149690588 # number of demand (read+write) hits 65610827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::cpu0.data 149878390 # number of overall hits 65710827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_hits::total 149878390 # number of overall hits 65810827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::cpu0.data 2964325 # number of ReadReq misses 65910827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_misses::total 2964325 # number of ReadReq misses 66010827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::cpu0.data 1343066 # number of WriteReq misses 66110827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_misses::total 1343066 # number of WriteReq misses 66210827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::cpu0.data 617580 # number of SoftPFReq misses 66310827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_misses::total 617580 # number of SoftPFReq misses 66410827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 739156 # number of WriteInvalidateReq misses 66510827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_misses::total 739156 # number of WriteInvalidateReq misses 66610827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153043 # number of LoadLockedReq misses 66710827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_misses::total 153043 # number of LoadLockedReq misses 66810827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::cpu0.data 195288 # number of StoreCondReq misses 66910827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_misses::total 195288 # number of StoreCondReq misses 67010827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::cpu0.data 4307391 # number of demand (read+write) misses 67110827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_misses::total 4307391 # number of demand (read+write) misses 67210827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::cpu0.data 4924971 # number of overall misses 67310827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_misses::total 4924971 # number of overall misses 67410827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44154787210 # number of ReadReq miss cycles 67510827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_latency::total 44154787210 # number of ReadReq miss cycles 67610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26046845450 # number of WriteReq miss cycles 67710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_latency::total 26046845450 # number of WriteReq miss cycles 67810827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30884044772 # number of WriteInvalidateReq miss cycles 67910827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30884044772 # number of WriteInvalidateReq miss cycles 68010827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2257944026 # number of LoadLockedReq miss cycles 68110827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_latency::total 2257944026 # number of LoadLockedReq miss cycles 68210827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4202199390 # number of StoreCondReq miss cycles 68310827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_latency::total 4202199390 # number of StoreCondReq miss cycles 68410827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2186500 # number of StoreCondFailReq miss cycles 68510827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_miss_latency::total 2186500 # number of StoreCondFailReq miss cycles 68610827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::cpu0.data 70201632660 # number of demand (read+write) miss cycles 68710827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_latency::total 70201632660 # number of demand (read+write) miss cycles 68810827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::cpu0.data 70201632660 # number of overall miss cycles 68910827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_latency::total 70201632660 # number of overall miss cycles 69010827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::cpu0.data 80960876 # number of ReadReq accesses(hits+misses) 69110827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_accesses::total 80960876 # number of ReadReq accesses(hits+misses) 69210827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::cpu0.data 73037103 # number of WriteReq accesses(hits+misses) 69310827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_accesses::total 73037103 # number of WriteReq accesses(hits+misses) 69410827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::cpu0.data 805382 # number of SoftPFReq accesses(hits+misses) 69510827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_accesses::total 805382 # number of SoftPFReq accesses(hits+misses) 69610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 870443 # number of WriteInvalidateReq accesses(hits+misses) 69710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_accesses::total 870443 # number of WriteInvalidateReq accesses(hits+misses) 69810827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1984536 # number of LoadLockedReq accesses(hits+misses) 69910827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_accesses::total 1984536 # number of LoadLockedReq accesses(hits+misses) 70010827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1983161 # number of StoreCondReq accesses(hits+misses) 70110827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_accesses::total 1983161 # number of StoreCondReq accesses(hits+misses) 70210827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::cpu0.data 153997979 # number of demand (read+write) accesses 70310827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_accesses::total 153997979 # number of demand (read+write) accesses 70410827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::cpu0.data 154803361 # number of overall (read+write) accesses 70510827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_accesses::total 154803361 # number of overall (read+write) accesses 70610827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036614 # miss rate for ReadReq accesses 70710827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_miss_rate::total 0.036614 # miss rate for ReadReq accesses 70810827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018389 # miss rate for WriteReq accesses 70910827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_miss_rate::total 0.018389 # miss rate for WriteReq accesses 71010827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766816 # miss rate for SoftPFReq accesses 71110827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_miss_rate::total 0.766816 # miss rate for SoftPFReq accesses 71210827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.849172 # miss rate for WriteInvalidateReq accesses 71310827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.849172 # miss rate for WriteInvalidateReq accesses 71410827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077118 # miss rate for LoadLockedReq accesses 71510827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077118 # miss rate for LoadLockedReq accesses 71610827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098473 # miss rate for StoreCondReq accesses 71710827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_miss_rate::total 0.098473 # miss rate for StoreCondReq accesses 71810827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::cpu0.data 0.027970 # miss rate for demand accesses 71910827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_miss_rate::total 0.027970 # miss rate for demand accesses 72010827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::cpu0.data 0.031814 # miss rate for overall accesses 72110827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_miss_rate::total 0.031814 # miss rate for overall accesses 72210827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14895.393457 # average ReadReq miss latency 72310827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_miss_latency::total 14895.393457 # average ReadReq miss latency 72410827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19393.570718 # average WriteReq miss latency 72510827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_miss_latency::total 19393.570718 # average WriteReq miss latency 72610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41782.850673 # average WriteInvalidateReq miss latency 72710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41782.850673 # average WriteInvalidateReq miss latency 72810827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14753.657639 # average LoadLockedReq miss latency 72910827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14753.657639 # average LoadLockedReq miss latency 73010827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21517.960090 # average StoreCondReq miss latency 73110827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21517.960090 # average StoreCondReq miss latency 73210535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 73310535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 73410827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16297.947565 # average overall miss latency 73510827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_miss_latency::total 16297.947565 # average overall miss latency 73610827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14254.222545 # average overall miss latency 73710827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_miss_latency::total 14254.222545 # average overall miss latency 73810535SN/Asystem.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 73910535SN/Asystem.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 74010535SN/Asystem.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 74110535SN/Asystem.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 74210535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 74310535SN/Asystem.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 74410585SN/Asystem.cpu0.dcache.fast_writes 0 # number of fast writes performed 74510535SN/Asystem.cpu0.dcache.cache_copies 0 # number of cache copies performed 74610827Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::writebacks 3655915 # number of writebacks 74710827Sandreas.hansson@arm.comsystem.cpu0.dcache.writebacks::total 3655915 # number of writebacks 74810827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 33290 # number of ReadReq MSHR hits 74910827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_hits::total 33290 # number of ReadReq MSHR hits 75010827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21376 # number of WriteReq MSHR hits 75110827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_hits::total 21376 # number of WriteReq MSHR hits 75210827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42886 # number of LoadLockedReq MSHR hits 75310827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_hits::total 42886 # number of LoadLockedReq MSHR hits 75410827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::cpu0.data 54666 # number of demand (read+write) MSHR hits 75510827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_hits::total 54666 # number of demand (read+write) MSHR hits 75610827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::cpu0.data 54666 # number of overall MSHR hits 75710827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_hits::total 54666 # number of overall MSHR hits 75810827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2931035 # number of ReadReq MSHR misses 75910827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_misses::total 2931035 # number of ReadReq MSHR misses 76010827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1321690 # number of WriteReq MSHR misses 76110827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_misses::total 1321690 # number of WriteReq MSHR misses 76210827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 611921 # number of SoftPFReq MSHR misses 76310827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_misses::total 611921 # number of SoftPFReq MSHR misses 76410827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 739156 # number of WriteInvalidateReq MSHR misses 76510827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 739156 # number of WriteInvalidateReq MSHR misses 76610827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 110157 # number of LoadLockedReq MSHR misses 76710827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_misses::total 110157 # number of LoadLockedReq MSHR misses 76810827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195288 # number of StoreCondReq MSHR misses 76910827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_misses::total 195288 # number of StoreCondReq MSHR misses 77010827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::cpu0.data 4252725 # number of demand (read+write) MSHR misses 77110827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_misses::total 4252725 # number of demand (read+write) MSHR misses 77210827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::cpu0.data 4864646 # number of overall MSHR misses 77310827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_misses::total 4864646 # number of overall MSHR misses 77410827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable 77510827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable::total 16584 # number of ReadReq MSHR uncacheable 77610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable 77710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable::total 18033 # number of WriteReq MSHR uncacheable 77810827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses 77910827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_misses::total 34617 # number of overall MSHR uncacheable misses 78010827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38329059920 # number of ReadReq MSHR miss cycles 78110827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_latency::total 38329059920 # number of ReadReq MSHR miss cycles 78210827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23455096050 # number of WriteReq MSHR miss cycles 78310827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_latency::total 23455096050 # number of WriteReq MSHR miss cycles 78410827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13388812156 # number of SoftPFReq MSHR miss cycles 78510827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13388812156 # number of SoftPFReq MSHR miss cycles 78610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29772038228 # number of WriteInvalidateReq MSHR miss cycles 78710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29772038228 # number of WriteInvalidateReq MSHR miss cycles 78810827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1440580476 # number of LoadLockedReq MSHR miss cycles 78910827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1440580476 # number of LoadLockedReq MSHR miss cycles 79010827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3899742610 # number of StoreCondReq MSHR miss cycles 79110827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3899742610 # number of StoreCondReq MSHR miss cycles 79210827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2117500 # number of StoreCondFailReq MSHR miss cycles 79310827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2117500 # number of StoreCondFailReq MSHR miss cycles 79410827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61784155970 # number of demand (read+write) MSHR miss cycles 79510827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_latency::total 61784155970 # number of demand (read+write) MSHR miss cycles 79610827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75172968126 # number of overall MSHR miss cycles 79710827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_latency::total 75172968126 # number of overall MSHR miss cycles 79810827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2701006250 # number of ReadReq MSHR uncacheable cycles 79910827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2701006250 # number of ReadReq MSHR uncacheable cycles 80010827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2792188500 # number of WriteReq MSHR uncacheable cycles 80110827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2792188500 # number of WriteReq MSHR uncacheable cycles 80210827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5493194750 # number of overall MSHR uncacheable cycles 80310827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_uncacheable_latency::total 5493194750 # number of overall MSHR uncacheable cycles 80410827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036203 # mshr miss rate for ReadReq accesses 80510827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036203 # mshr miss rate for ReadReq accesses 80610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018096 # mshr miss rate for WriteReq accesses 80710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018096 # mshr miss rate for WriteReq accesses 80810827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759790 # mshr miss rate for SoftPFReq accesses 80910827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759790 # mshr miss rate for SoftPFReq accesses 81010827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.849172 # mshr miss rate for WriteInvalidateReq accesses 81110827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.849172 # mshr miss rate for WriteInvalidateReq accesses 81210827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055508 # mshr miss rate for LoadLockedReq accesses 81310827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055508 # mshr miss rate for LoadLockedReq accesses 81410827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098473 # mshr miss rate for StoreCondReq accesses 81510827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098473 # mshr miss rate for StoreCondReq accesses 81610827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027615 # mshr miss rate for demand accesses 81710827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_mshr_miss_rate::total 0.027615 # mshr miss rate for demand accesses 81810827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031425 # mshr miss rate for overall accesses 81910827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_mshr_miss_rate::total 0.031425 # mshr miss rate for overall accesses 82010827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13076.971077 # average ReadReq mshr miss latency 82110827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13076.971077 # average ReadReq mshr miss latency 82210827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17746.291528 # average WriteReq mshr miss latency 82310827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17746.291528 # average WriteReq mshr miss latency 82410827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21879.968421 # average SoftPFReq mshr miss latency 82510827Sandreas.hansson@arm.comsystem.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21879.968421 # average SoftPFReq mshr miss latency 82610827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 40278.423267 # average WriteInvalidateReq mshr miss latency 82710827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 40278.423267 # average WriteInvalidateReq mshr miss latency 82810827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13077.520956 # average LoadLockedReq mshr miss latency 82910827Sandreas.hansson@arm.comsystem.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13077.520956 # average LoadLockedReq mshr miss latency 83010827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19969.187098 # average StoreCondReq mshr miss latency 83110827Sandreas.hansson@arm.comsystem.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19969.187098 # average StoreCondReq mshr miss latency 83210535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 83310535SN/Asystem.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 83410827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14528.133366 # average overall mshr miss latency 83510827Sandreas.hansson@arm.comsystem.cpu0.dcache.demand_avg_mshr_miss_latency::total 14528.133366 # average overall mshr miss latency 83610827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15452.916435 # average overall mshr miss latency 83710827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_miss_latency::total 15452.916435 # average overall mshr miss latency 83810827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162868.201278 # average ReadReq mshr uncacheable latency 83910827Sandreas.hansson@arm.comsystem.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162868.201278 # average ReadReq mshr uncacheable latency 84010827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154837.714191 # average WriteReq mshr uncacheable latency 84110827Sandreas.hansson@arm.comsystem.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154837.714191 # average WriteReq mshr uncacheable latency 84210827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 158684.887483 # average overall mshr uncacheable latency 84310827Sandreas.hansson@arm.comsystem.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 158684.887483 # average overall mshr uncacheable latency 84410535SN/Asystem.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 84510827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.replacements 5032307 # number of replacements 84610827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tagsinuse 511.899757 # Cycle average of tags in use 84710827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.total_refs 439089613 # Total number of references to valid blocks. 84810827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.sampled_refs 5032819 # Sample count of references to valid blocks. 84910827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.avg_refs 87.245262 # Average number of references to valid blocks. 85010827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.warmup_cycle 33435686250 # Cycle when the warmup percentage was hit. 85110827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899757 # Average occupied blocks per requestor 85210726SN/Asystem.cpu0.icache.tags.occ_percent::cpu0.inst 0.999804 # Average percentage of cache occupancy 85310726SN/Asystem.cpu0.icache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy 85410535SN/Asystem.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 85510827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 85610827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id 85710827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 85810535SN/Asystem.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 85910827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.tag_accesses 893277683 # Number of tag accesses 86010827Sandreas.hansson@arm.comsystem.cpu0.icache.tags.data_accesses 893277683 # Number of data accesses 86110827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::cpu0.inst 439089613 # number of ReadReq hits 86210827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_hits::total 439089613 # number of ReadReq hits 86310827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::cpu0.inst 439089613 # number of demand (read+write) hits 86410827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_hits::total 439089613 # number of demand (read+write) hits 86510827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::cpu0.inst 439089613 # number of overall hits 86610827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_hits::total 439089613 # number of overall hits 86710827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::cpu0.inst 5032819 # number of ReadReq misses 86810827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_misses::total 5032819 # number of ReadReq misses 86910827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::cpu0.inst 5032819 # number of demand (read+write) misses 87010827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_misses::total 5032819 # number of demand (read+write) misses 87110827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::cpu0.inst 5032819 # number of overall misses 87210827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_misses::total 5032819 # number of overall misses 87310827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52854361147 # number of ReadReq miss cycles 87410827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_latency::total 52854361147 # number of ReadReq miss cycles 87510827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::cpu0.inst 52854361147 # number of demand (read+write) miss cycles 87610827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_latency::total 52854361147 # number of demand (read+write) miss cycles 87710827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::cpu0.inst 52854361147 # number of overall miss cycles 87810827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_latency::total 52854361147 # number of overall miss cycles 87910827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::cpu0.inst 444122432 # number of ReadReq accesses(hits+misses) 88010827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_accesses::total 444122432 # number of ReadReq accesses(hits+misses) 88110827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::cpu0.inst 444122432 # number of demand (read+write) accesses 88210827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_accesses::total 444122432 # number of demand (read+write) accesses 88310827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::cpu0.inst 444122432 # number of overall (read+write) accesses 88410827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_accesses::total 444122432 # number of overall (read+write) accesses 88510827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011332 # miss rate for ReadReq accesses 88610827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_miss_rate::total 0.011332 # miss rate for ReadReq accesses 88710827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::cpu0.inst 0.011332 # miss rate for demand accesses 88810827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_miss_rate::total 0.011332 # miss rate for demand accesses 88910827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::cpu0.inst 0.011332 # miss rate for overall accesses 89010827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_miss_rate::total 0.011332 # miss rate for overall accesses 89110827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10501.939598 # average ReadReq miss latency 89210827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_miss_latency::total 10501.939598 # average ReadReq miss latency 89310827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10501.939598 # average overall miss latency 89410827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_miss_latency::total 10501.939598 # average overall miss latency 89510827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10501.939598 # average overall miss latency 89610827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_miss_latency::total 10501.939598 # average overall miss latency 89710535SN/Asystem.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 89810535SN/Asystem.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 89910535SN/Asystem.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 90010535SN/Asystem.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 90110535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 90210535SN/Asystem.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 90310535SN/Asystem.cpu0.icache.fast_writes 0 # number of fast writes performed 90410535SN/Asystem.cpu0.icache.cache_copies 0 # number of cache copies performed 90510827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5032819 # number of ReadReq MSHR misses 90610827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_misses::total 5032819 # number of ReadReq MSHR misses 90710827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::cpu0.inst 5032819 # number of demand (read+write) MSHR misses 90810827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_misses::total 5032819 # number of demand (read+write) MSHR misses 90910827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::cpu0.inst 5032819 # number of overall MSHR misses 91010827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_misses::total 5032819 # number of overall MSHR misses 91110827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 91210827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 91310827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 91410827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 91510827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 47804251855 # number of ReadReq MSHR miss cycles 91610827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_latency::total 47804251855 # number of ReadReq MSHR miss cycles 91710827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 47804251855 # number of demand (read+write) MSHR miss cycles 91810827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_latency::total 47804251855 # number of demand (read+write) MSHR miss cycles 91910827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 47804251855 # number of overall MSHR miss cycles 92010827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_latency::total 47804251855 # number of overall MSHR miss cycles 92110726SN/Asystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of ReadReq MSHR uncacheable cycles 92210726SN/Asystem.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3811870500 # number of ReadReq MSHR uncacheable cycles 92310726SN/Asystem.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of overall MSHR uncacheable cycles 92410726SN/Asystem.cpu0.icache.overall_mshr_uncacheable_latency::total 3811870500 # number of overall MSHR uncacheable cycles 92510827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for ReadReq accesses 92610827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011332 # mshr miss rate for ReadReq accesses 92710827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for demand accesses 92810827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_mshr_miss_rate::total 0.011332 # mshr miss rate for demand accesses 92910827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for overall accesses 93010827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_mshr_miss_rate::total 0.011332 # mshr miss rate for overall accesses 93110827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average ReadReq mshr miss latency 93210827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9498.504090 # average ReadReq mshr miss latency 93310827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average overall mshr miss latency 93410827Sandreas.hansson@arm.comsystem.cpu0.icache.demand_avg_mshr_miss_latency::total 9498.504090 # average overall mshr miss latency 93510827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average overall mshr miss latency 93610827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_miss_latency::total 9498.504090 # average overall mshr miss latency 93710827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000 # average ReadReq mshr uncacheable latency 93810827Sandreas.hansson@arm.comsystem.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88391.200000 # average ReadReq mshr uncacheable latency 93910827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000 # average overall mshr uncacheable latency 94010827Sandreas.hansson@arm.comsystem.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88391.200000 # average overall mshr uncacheable latency 94110535SN/Asystem.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 94210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.num_hwpf_issued 7211191 # number of hwpf issued 94310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfIdentified 7211221 # number of prefetch candidates identified 94410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue 94510628SN/Asystem.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 94610628SN/Asystem.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 94710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.prefetcher.pfSpanPage 945331 # number of prefetches not generated due to page crossing 94810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.replacements 2374120 # number of replacements 94910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tagsinuse 16169.428044 # Cycle average of tags in use 95010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.total_refs 10531211 # Total number of references to valid blocks. 95110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.sampled_refs 2389368 # Sample count of references to valid blocks. 95210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.avg_refs 4.407530 # Average number of references to valid blocks. 95310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.warmup_cycle 5341335500 # Cycle when the warmup percentage was hit. 95410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::writebacks 8264.618229 # Average occupied blocks per requestor 95510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 69.150581 # Average occupied blocks per requestor 95610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 77.449352 # Average occupied blocks per requestor 95710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3311.410043 # Average occupied blocks per requestor 95810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.data 3382.587139 # Average occupied blocks per requestor 95910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1064.212699 # Average occupied blocks per requestor 96010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::writebacks 0.504432 # Average percentage of cache occupancy 96110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004221 # Average percentage of cache occupancy 96210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004727 # Average percentage of cache occupancy 96310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.202112 # Average percentage of cache occupancy 96410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.data 0.206457 # Average percentage of cache occupancy 96510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.064954 # Average percentage of cache occupancy 96610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_percent::total 0.986904 # Average percentage of cache occupancy 96710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1022 1373 # Occupied blocks per task id 96810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id 96910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_blocks::1024 13790 # Occupied blocks per task id 97010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 97110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::2 173 # Occupied blocks per task id 97210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::3 780 # Occupied blocks per task id 97310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1022::4 417 # Occupied blocks per task id 97410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id 97510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id 97610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 97710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id 97810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3709 # Occupied blocks per task id 97910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6679 # Occupied blocks per task id 98010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3275 # Occupied blocks per task id 98110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1022 0.083801 # Percentage of cache occupancy per task id 98210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id 98310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.occ_task_id_percent::1024 0.841675 # Percentage of cache occupancy per task id 98410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.tag_accesses 244043620 # Number of tag accesses 98510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.tags.data_accesses 244043620 # Number of data accesses 98610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 211402 # number of ReadReq hits 98710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 128647 # number of ReadReq hits 98810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.inst 4517111 # number of ReadReq hits 98910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::cpu0.data 2702351 # number of ReadReq hits 99010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_hits::total 7559511 # number of ReadReq hits 99110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::writebacks 3655914 # number of Writeback hits 99210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_hits::total 3655914 # number of Writeback hits 99310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 175642 # number of WriteInvalidateReq hits 99410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_hits::total 175642 # number of WriteInvalidateReq hits 99510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::cpu0.data 102383 # number of UpgradeReq hits 99610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_hits::total 102383 # number of UpgradeReq hits 99710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 30801 # number of SCUpgradeReq hits 99810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_hits::total 30801 # number of SCUpgradeReq hits 99910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::cpu0.data 876779 # number of ReadExReq hits 100010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_hits::total 876779 # number of ReadExReq hits 100110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.dtb.walker 211402 # number of demand (read+write) hits 100210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.itb.walker 128647 # number of demand (read+write) hits 100310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.inst 4517111 # number of demand (read+write) hits 100410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::cpu0.data 3579130 # number of demand (read+write) hits 100510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_hits::total 8436290 # number of demand (read+write) hits 100610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.dtb.walker 211402 # number of overall hits 100710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.itb.walker 128647 # number of overall hits 100810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.inst 4517111 # number of overall hits 100910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::cpu0.data 3579130 # number of overall hits 101010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_hits::total 8436290 # number of overall hits 101110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10881 # number of ReadReq misses 101210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8892 # number of ReadReq misses 101310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.inst 515708 # number of ReadReq misses 101410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::cpu0.data 950762 # number of ReadReq misses 101510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_misses::total 1486243 # number of ReadReq misses 101610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 562136 # number of WriteInvalidateReq misses 101710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_misses::total 562136 # number of WriteInvalidateReq misses 101810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::cpu0.data 120119 # number of UpgradeReq misses 101910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_misses::total 120119 # number of UpgradeReq misses 102010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 164484 # number of SCUpgradeReq misses 102110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_misses::total 164484 # number of SCUpgradeReq misses 102210726SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses 102310726SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 102410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::cpu0.data 240029 # number of ReadExReq misses 102510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_misses::total 240029 # number of ReadExReq misses 102610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10881 # number of demand (read+write) misses 102710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.itb.walker 8892 # number of demand (read+write) misses 102810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.inst 515708 # number of demand (read+write) misses 102910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::cpu0.data 1190791 # number of demand (read+write) misses 103010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_misses::total 1726272 # number of demand (read+write) misses 103110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10881 # number of overall misses 103210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.itb.walker 8892 # number of overall misses 103310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.inst 515708 # number of overall misses 103410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::cpu0.data 1190791 # number of overall misses 103510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_misses::total 1726272 # number of overall misses 103610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 393469249 # number of ReadReq miss cycles 103710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 355451999 # number of ReadReq miss cycles 103810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15907969852 # number of ReadReq miss cycles 103910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 31938942740 # number of ReadReq miss cycles 104010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_latency::total 48595833840 # number of ReadReq miss cycles 104110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 181717619 # number of WriteInvalidateReq miss cycles 104210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 181717619 # number of WriteInvalidateReq miss cycles 104310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2563026586 # number of UpgradeReq miss cycles 104410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_latency::total 2563026586 # number of UpgradeReq miss cycles 104510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3399427212 # number of SCUpgradeReq miss cycles 104610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3399427212 # number of SCUpgradeReq miss cycles 104710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2070498 # number of SCUpgradeFailReq miss cycles 104810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2070498 # number of SCUpgradeFailReq miss cycles 104910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12166293140 # number of ReadExReq miss cycles 105010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_latency::total 12166293140 # number of ReadExReq miss cycles 105110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 393469249 # number of demand (read+write) miss cycles 105210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 355451999 # number of demand (read+write) miss cycles 105310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.inst 15907969852 # number of demand (read+write) miss cycles 105410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::cpu0.data 44105235880 # number of demand (read+write) miss cycles 105510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_latency::total 60762126980 # number of demand (read+write) miss cycles 105610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 393469249 # number of overall miss cycles 105710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 355451999 # number of overall miss cycles 105810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.inst 15907969852 # number of overall miss cycles 105910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::cpu0.data 44105235880 # number of overall miss cycles 106010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_latency::total 60762126980 # number of overall miss cycles 106110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 222283 # number of ReadReq accesses(hits+misses) 106210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 137539 # number of ReadReq accesses(hits+misses) 106310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5032819 # number of ReadReq accesses(hits+misses) 106410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::cpu0.data 3653113 # number of ReadReq accesses(hits+misses) 106510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_accesses::total 9045754 # number of ReadReq accesses(hits+misses) 106610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::writebacks 3655914 # number of Writeback accesses(hits+misses) 106710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.Writeback_accesses::total 3655914 # number of Writeback accesses(hits+misses) 106810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 737778 # number of WriteInvalidateReq accesses(hits+misses) 106910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_accesses::total 737778 # number of WriteInvalidateReq accesses(hits+misses) 107010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 222502 # number of UpgradeReq accesses(hits+misses) 107110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_accesses::total 222502 # number of UpgradeReq accesses(hits+misses) 107210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195285 # number of SCUpgradeReq accesses(hits+misses) 107310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_accesses::total 195285 # number of SCUpgradeReq accesses(hits+misses) 107410726SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 107510726SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 107610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1116808 # number of ReadExReq accesses(hits+misses) 107710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_accesses::total 1116808 # number of ReadExReq accesses(hits+misses) 107810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 222283 # number of demand (read+write) accesses 107910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.itb.walker 137539 # number of demand (read+write) accesses 108010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.inst 5032819 # number of demand (read+write) accesses 108110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_accesses::cpu0.data 4769921 # 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miss rate for ReadReq accesses 109010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102469 # miss rate for ReadReq accesses 109110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.260261 # miss rate for ReadReq accesses 109210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_miss_rate::total 0.164303 # miss rate for ReadReq accesses 109310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.761931 # miss rate for WriteInvalidateReq accesses 109410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.761931 # miss rate for WriteInvalidateReq accesses 109510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.539856 # miss rate for UpgradeReq accesses 109610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_miss_rate::total 0.539856 # miss rate for UpgradeReq accesses 109710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.842277 # miss rate for SCUpgradeReq accesses 109810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.842277 # miss rate for SCUpgradeReq accesses 109910535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 110010535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 110110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.214924 # miss rate for ReadExReq accesses 110210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_miss_rate::total 0.214924 # miss rate for ReadExReq accesses 110310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for demand accesses 110410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064651 # miss rate for demand accesses 110510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102469 # miss rate for demand accesses 110610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::cpu0.data 0.249646 # miss rate for demand accesses 110710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_miss_rate::total 0.169866 # miss rate for demand accesses 110810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for overall accesses 110910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064651 # miss rate for overall accesses 111010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102469 # miss rate for overall accesses 111110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::cpu0.data 0.249646 # miss rate for overall accesses 111210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_miss_rate::total 0.169866 # miss rate for overall accesses 111310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average ReadReq miss latency 111410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39974.358862 # average ReadReq miss latency 111510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30846.854910 # average ReadReq miss latency 111610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33592.994609 # average ReadReq miss latency 111710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_miss_latency::total 32697.098550 # average ReadReq miss latency 111810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 323.262732 # average WriteInvalidateReq miss latency 111910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 323.262732 # average WriteInvalidateReq miss latency 112010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21337.395300 # average UpgradeReq miss latency 112110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21337.395300 # average UpgradeReq miss latency 112210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20667.221201 # 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average overall miss latency 113110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37038.603651 # average overall miss latency 113210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_miss_latency::total 35198.466395 # average overall miss latency 113310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average overall miss latency 113410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39974.358862 # average overall miss latency 113510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30846.854910 # average overall miss latency 113610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37038.603651 # average overall miss latency 113710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_miss_latency::total 35198.466395 # average overall miss latency 113810628SN/Asystem.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 113910535SN/Asystem.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 114010628SN/Asystem.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 114110535SN/Asystem.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 114210628SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 114310535SN/Asystem.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 114410535SN/Asystem.cpu0.l2cache.fast_writes 0 # number of fast writes performed 114510535SN/Asystem.cpu0.l2cache.cache_copies 0 # number of cache copies performed 114610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::writebacks 1321734 # number of writebacks 114710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.writebacks::total 1321734 # number of writebacks 114810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 498 # 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number of HardPFReq MSHR miss cycles 119810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32139076466 # number of HardPFReq MSHR miss cycles 119910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24223804784 # number of WriteInvalidateReq MSHR miss cycles 120010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 24223804784 # number of WriteInvalidateReq MSHR miss cycles 120110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2466827080 # number of UpgradeReq MSHR miss cycles 120210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2466827080 # number of UpgradeReq MSHR miss cycles 120310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2435399890 # number of SCUpgradeReq MSHR miss cycles 120410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2435399890 # number of SCUpgradeReq MSHR miss cycles 120510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1771498 # number of SCUpgradeFailReq MSHR miss cycles 120610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1771498 # number of SCUpgradeFailReq MSHR miss cycles 120710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9980703954 # number of ReadExReq MSHR miss cycles 120810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9980703954 # number of ReadExReq MSHR miss cycles 120910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of demand (read+write) MSHR miss cycles 121010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 297082001 # number of demand (read+write) MSHR miss cycles 121110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 12538366148 # number of demand (read+write) MSHR miss cycles 121210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 35656808127 # number of demand (read+write) MSHR miss cycles 121310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_latency::total 48814446527 # number of demand (read+write) MSHR miss cycles 121410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of overall MSHR miss cycles 121510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 297082001 # number of overall MSHR miss cycles 121610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 12538366148 # number of overall MSHR miss cycles 121710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 35656808127 # number of overall MSHR miss cycles 121810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32139076466 # number of overall MSHR miss cycles 121910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_latency::total 80953522993 # number of overall MSHR miss cycles 122010726SN/Asystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of ReadReq MSHR uncacheable cycles 122110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2568327500 # number of ReadReq MSHR uncacheable cycles 122210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6036578500 # number of ReadReq MSHR uncacheable cycles 122310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2656940000 # number of WriteReq MSHR uncacheable cycles 122410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2656940000 # number of WriteReq MSHR uncacheable cycles 122510726SN/Asystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of overall MSHR uncacheable cycles 122610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5225267500 # number of overall MSHR uncacheable cycles 122710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8693518500 # number of overall MSHR uncacheable cycles 122810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for ReadReq accesses 122910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for ReadReq accesses 123010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for ReadReq accesses 123110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.260124 # mshr miss rate for ReadReq accesses 123210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.164248 # mshr miss rate for ReadReq accesses 123310535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 123410535SN/Asystem.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 123510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.761931 # mshr miss rate for WriteInvalidateReq accesses 123610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.761931 # mshr miss rate for WriteInvalidateReq accesses 123710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.539856 # mshr miss rate for UpgradeReq accesses 123810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.539856 # mshr miss rate for UpgradeReq accesses 123910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.842277 # mshr miss rate for SCUpgradeReq accesses 124010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.842277 # mshr miss rate for SCUpgradeReq accesses 124110535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 124210535SN/Asystem.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 124310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.209542 # mshr miss rate for ReadExReq accesses 124410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.209542 # mshr miss rate for ReadExReq accesses 124510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for demand accesses 124610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for demand accesses 124710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for demand accesses 124810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248281 # mshr miss rate for demand accesses 124910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_mshr_miss_rate::total 0.169225 # mshr miss rate for demand accesses 125010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for overall accesses 125110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for overall accesses 125210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for overall accesses 125310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248281 # mshr miss rate for overall accesses 125410535SN/Asystem.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 125510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_mshr_miss_rate::total 0.234079 # mshr miss rate for overall accesses 125610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average ReadReq mshr miss latency 125710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average ReadReq mshr miss latency 125810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average ReadReq mshr miss latency 125910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27019.969370 # average ReadReq mshr miss latency 126010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26137.555619 # average ReadReq mshr miss latency 126110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779 # average HardPFReq mshr miss latency 126210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48763.839779 # average HardPFReq mshr miss latency 126310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43092.427427 # average WriteInvalidateReq mshr miss latency 126410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43092.427427 # average WriteInvalidateReq mshr miss latency 126510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20536.526944 # average UpgradeReq mshr miss latency 126610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20536.526944 # average UpgradeReq mshr miss latency 126710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14806.302680 # average SCUpgradeReq mshr miss latency 126810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14806.302680 # average SCUpgradeReq mshr miss latency 126910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 590499.333333 # average SCUpgradeFailReq mshr miss latency 127010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590499.333333 # average SCUpgradeFailReq mshr miss latency 127110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42649.300285 # average ReadExReq mshr miss latency 127210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42649.300285 # average ReadExReq mshr miss latency 127310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average overall mshr miss latency 127410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average overall mshr miss latency 127510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average overall mshr miss latency 127610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30108.376322 # average overall mshr miss latency 127710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28384.403274 # average overall mshr miss latency 127810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average overall mshr miss latency 127910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average overall mshr miss latency 128010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average overall mshr miss latency 128110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30108.376322 # average overall mshr miss latency 128210827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779 # average overall mshr miss latency 128310827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34030.685975 # average overall mshr miss latency 128410827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average ReadReq mshr uncacheable latency 128510827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154867.794260 # average ReadReq mshr uncacheable latency 128610827Sandreas.hansson@arm.comsystem.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101099.976553 # average ReadReq mshr uncacheable latency 128710827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147337.658737 # average WriteReq mshr uncacheable latency 128810827Sandreas.hansson@arm.comsystem.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 147337.658737 # average WriteReq mshr uncacheable latency 128910827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average overall mshr uncacheable latency 129010827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 150945.128116 # average overall mshr uncacheable latency 129110827Sandreas.hansson@arm.comsystem.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111825.248900 # average overall mshr uncacheable latency 129210535SN/Asystem.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 129310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadReq 11389901 # Transaction distribution 129410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadResp 9301467 # Transaction distribution 129510827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution 129610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteResp 18033 # Transaction distribution 129710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::Writeback 3655914 # Transaction distribution 129810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::HardPFReq 950949 # Transaction distribution 129910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1103178 # Transaction distribution 130010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 737778 # Transaction distribution 130110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeReq 440847 # Transaction distribution 130210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeReq 362789 # Transaction distribution 130310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeResp 484218 # Transaction distribution 130410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution 130510827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution 130610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExReq 1248974 # Transaction distribution 130710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.trans_dist::ReadExResp 1125262 # Transaction distribution 130810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10151888 # Packet count per connected master and slave (bytes) 130910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15745151 # Packet count per connected master and slave (bytes) 131010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 304033 # Packet count per connected master and slave (bytes) 131110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 517558 # Packet count per connected master and slave (bytes) 131210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_count::total 26718630 # Packet count per connected master and slave (bytes) 131310827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 322272916 # Cumulative packet size per connected master and slave (bytes) 131410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 593126965 # Cumulative packet size per connected master and slave (bytes) 131510827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1100312 # Cumulative packet size per connected master and slave (bytes) 131610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1778264 # Cumulative packet size per connected master and slave (bytes) 131710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.pkt_size::total 918278457 # Cumulative packet size per connected master and slave (bytes) 131810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoops 4307980 # Total snoops (count) 131910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::samples 19190741 # Request fanout histogram 132010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::mean 1.234424 # Request fanout histogram 132110827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::stdev 0.423639 # Request fanout histogram 132210535SN/Asystem.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 132310535SN/Asystem.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 132410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::1 14691964 76.56% 76.56% # Request fanout histogram 132510827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::2 4498777 23.44% 100.00% # Request fanout histogram 132610535SN/Asystem.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 132710827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 132810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 132910827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoop_fanout::total 19190741 # Request fanout histogram 133010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.reqLayer0.occupancy 11979643994 # Layer occupancy (ticks) 133110535SN/Asystem.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 133210827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.snoopLayer0.occupancy 187059488 # Layer occupancy (ticks) 133310535SN/Asystem.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 133410827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer0.occupancy 7611089646 # Layer occupancy (ticks) 133510535SN/Asystem.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 133610827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer1.occupancy 7824710310 # Layer occupancy (ticks) 133710535SN/Asystem.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 133810827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer2.occupancy 166780001 # Layer occupancy (ticks) 133910535SN/Asystem.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 134010827Sandreas.hansson@arm.comsystem.cpu0.toL2Bus.respLayer3.occupancy 295551751 # Layer occupancy (ticks) 134110535SN/Asystem.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 134210628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 134310628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134410628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 134510628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 134610628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 134710628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 134810628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134910628SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 135010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 135110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 135210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 135310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 135410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 135510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 135610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 135710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 135810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 135910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 136010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 136110535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 136210535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 136310535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 136410535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 136510535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 136610535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 136710535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 136810535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 136910535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 137010535SN/Asystem.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 137110827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walks 115983 # Table walker walks requested 137210827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLong 115983 # Table walker walks initiated with long descriptors 137310827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11170 # Level at which table walker walks with long descriptors terminate 137410827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89969 # Level at which table walker walks with long descriptors terminate 137510827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting 137610827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::samples 115964 # Table walker wait (enqueue to first request) latency 137710827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::mean 0.064675 # Table walker wait (enqueue to first request) latency 137810827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::stdev 22.024176 # Table walker wait (enqueue to first request) latency 137910827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::0-511 115963 100.00% 100.00% # Table walker wait (enqueue to first request) latency 138010726SN/Asystem.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 138110827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkWaitTime::total 115964 # Table walker wait (enqueue to first request) latency 138210827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::samples 101158 # Table walker service (enqueue to completion) latency 138310827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::mean 19050.238172 # Table walker service (enqueue to completion) latency 138410827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::gmean 17171.563979 # Table walker service (enqueue to completion) latency 138510827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::stdev 14858.973019 # Table walker service (enqueue to completion) latency 138610827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::0-65535 99918 98.77% 98.77% # Table walker service (enqueue to completion) latency 138710827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::65536-131071 1061 1.05% 99.82% # Table walker service (enqueue to completion) latency 138810827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.03% 99.86% # Table walker service (enqueue to completion) latency 138910827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::196608-262143 72 0.07% 99.93% # Table walker service (enqueue to completion) latency 139010827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::262144-327679 53 0.05% 99.98% # Table walker service (enqueue to completion) latency 139110827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 139210827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 139310827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 139410827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 139510827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkCompletionTime::total 101158 # Table walker service (enqueue to completion) latency 139610827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::samples 3223072220 # Table walker pending requests distribution 139710827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::mean 0.344065 # Table walker pending requests distribution 139810827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::stdev 0.475063 # Table walker pending requests distribution 139910827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::0 2114124352 65.59% 65.59% # Table walker pending requests distribution 140010827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::1 1108947868 34.41% 100.00% # Table walker pending requests distribution 140110827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walksPending::total 3223072220 # Table walker pending requests distribution 140210827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::4K 89969 88.96% 88.96% # Table walker page sizes translated 140310827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::2M 11170 11.04% 100.00% # Table walker page sizes translated 140410827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkPageSizes::total 101139 # Table walker page sizes translated 140510827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 115983 # Table walker requests started/completed, data/inst 140610628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 140710827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Requested::total 115983 # Table walker requests started/completed, data/inst 140810827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 101139 # Table walker requests started/completed, data/inst 140910628SN/Asystem.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 141010827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin_Completed::total 101139 # Table walker requests started/completed, data/inst 141110827Sandreas.hansson@arm.comsystem.cpu1.dtb.walker.walkRequestOrigin::total 217122 # Table walker requests started/completed, data/inst 141210535SN/Asystem.cpu1.dtb.inst_hits 0 # ITB inst hits 141310535SN/Asystem.cpu1.dtb.inst_misses 0 # ITB inst misses 141410827Sandreas.hansson@arm.comsystem.cpu1.dtb.read_hits 83993689 # DTB read hits 141510827Sandreas.hansson@arm.comsystem.cpu1.dtb.read_misses 86321 # DTB read misses 141610827Sandreas.hansson@arm.comsystem.cpu1.dtb.write_hits 76478778 # DTB write hits 141710827Sandreas.hansson@arm.comsystem.cpu1.dtb.write_misses 29662 # DTB write misses 141810535SN/Asystem.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 141910535SN/Asystem.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142010827Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID 142110827Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID 142210827Sandreas.hansson@arm.comsystem.cpu1.dtb.flush_entries 42752 # Number of entries that have been flushed from TLB 142310535SN/Asystem.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 142410827Sandreas.hansson@arm.comsystem.cpu1.dtb.prefetch_faults 4958 # Number of TLB faults due to prefetch 142510535SN/Asystem.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 142610827Sandreas.hansson@arm.comsystem.cpu1.dtb.perms_faults 11385 # Number of TLB faults due to permissions restrictions 142710827Sandreas.hansson@arm.comsystem.cpu1.dtb.read_accesses 84080010 # DTB read accesses 142810827Sandreas.hansson@arm.comsystem.cpu1.dtb.write_accesses 76508440 # DTB write accesses 142910535SN/Asystem.cpu1.dtb.inst_accesses 0 # ITB inst accesses 143010827Sandreas.hansson@arm.comsystem.cpu1.dtb.hits 160472467 # DTB hits 143110827Sandreas.hansson@arm.comsystem.cpu1.dtb.misses 115983 # DTB misses 143210827Sandreas.hansson@arm.comsystem.cpu1.dtb.accesses 160588450 # DTB accesses 143310628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 143410628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 143510628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 143610628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 143710628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 143810628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 143910628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 144010628SN/Asystem.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 144110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 144210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 144310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 144410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 144510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 144610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 144710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 144810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 144910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 145010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 145210535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 145310535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 145410535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 145510535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 145610535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 145710535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 145810535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 145910535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 146010535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 146110535SN/Asystem.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 146210827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walks 60651 # Table walker walks requested 146310827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLong 60651 # Table walker walks initiated with long descriptors 146410827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level2 616 # Level at which table walker walks with long descriptors terminate 146510827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksLongTerminationLevel::Level3 54731 # Level at which table walker walks with long descriptors terminate 146610827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::samples 60651 # Table walker wait (enqueue to first request) latency 146710827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::0 60651 100.00% 100.00% # Table walker wait (enqueue to first request) latency 146810827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkWaitTime::total 60651 # Table walker wait (enqueue to first request) latency 146910827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::samples 55347 # Table walker service (enqueue to completion) latency 147010827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::mean 21982.528123 # Table walker service (enqueue to completion) latency 147110827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::gmean 19135.216139 # Table walker service (enqueue to completion) latency 147210827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::stdev 20466.687075 # Table walker service (enqueue to completion) latency 147310827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::0-65535 53969 97.51% 97.51% # Table walker service (enqueue to completion) latency 147410827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::65536-131071 1178 2.13% 99.64% # Table walker service (enqueue to completion) latency 147510827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::131072-196607 42 0.08% 99.71% # Table walker service (enqueue to completion) latency 147610827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.12% 99.84% # Table walker service (enqueue to completion) latency 147710827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::262144-327679 60 0.11% 99.95% # Table walker service (enqueue to completion) latency 147810827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.04% 99.98% # Table walker service (enqueue to completion) latency 147910827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 148010827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 148110827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 148210827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkCompletionTime::total 55347 # Table walker service (enqueue to completion) latency 148310827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::samples 2053569352 # Table walker pending requests distribution 148410827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::0 2053569352 100.00% 100.00% # Table walker pending requests distribution 148510827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walksPending::total 2053569352 # Table walker pending requests distribution 148610827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::4K 54731 98.89% 98.89% # Table walker page sizes translated 148710827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::2M 616 1.11% 100.00% # Table walker page sizes translated 148810827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkPageSizes::total 55347 # Table walker page sizes translated 148910628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 149010827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60651 # Table walker requests started/completed, data/inst 149110827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Requested::total 60651 # Table walker requests started/completed, data/inst 149210628SN/Asystem.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 149310827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55347 # Table walker requests started/completed, data/inst 149410827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin_Completed::total 55347 # Table walker requests started/completed, data/inst 149510827Sandreas.hansson@arm.comsystem.cpu1.itb.walker.walkRequestOrigin::total 115998 # Table walker requests started/completed, data/inst 149610827Sandreas.hansson@arm.comsystem.cpu1.itb.inst_hits 446979774 # ITB inst hits 149710827Sandreas.hansson@arm.comsystem.cpu1.itb.inst_misses 60651 # ITB inst misses 149810535SN/Asystem.cpu1.itb.read_hits 0 # DTB read hits 149910535SN/Asystem.cpu1.itb.read_misses 0 # DTB read misses 150010535SN/Asystem.cpu1.itb.write_hits 0 # DTB write hits 150110535SN/Asystem.cpu1.itb.write_misses 0 # DTB write misses 150210535SN/Asystem.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 150310535SN/Asystem.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 150410827Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID 150510827Sandreas.hansson@arm.comsystem.cpu1.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID 150610827Sandreas.hansson@arm.comsystem.cpu1.itb.flush_entries 29800 # Number of entries that have been flushed from TLB 150710535SN/Asystem.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 150810535SN/Asystem.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 150910535SN/Asystem.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 151010535SN/Asystem.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 151110535SN/Asystem.cpu1.itb.read_accesses 0 # DTB read accesses 151210535SN/Asystem.cpu1.itb.write_accesses 0 # DTB write accesses 151310827Sandreas.hansson@arm.comsystem.cpu1.itb.inst_accesses 447040425 # ITB inst accesses 151410827Sandreas.hansson@arm.comsystem.cpu1.itb.hits 446979774 # DTB hits 151510827Sandreas.hansson@arm.comsystem.cpu1.itb.misses 60651 # DTB misses 151610827Sandreas.hansson@arm.comsystem.cpu1.itb.accesses 447040425 # DTB accesses 151710827Sandreas.hansson@arm.comsystem.cpu1.numCycles 95053909934 # number of cpu cycles simulated 151810535SN/Asystem.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 151910535SN/Asystem.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 152010827Sandreas.hansson@arm.comsystem.cpu1.committedInsts 446673984 # Number of instructions committed 152110827Sandreas.hansson@arm.comsystem.cpu1.committedOps 525768473 # Number of ops (including micro ops) committed 152210827Sandreas.hansson@arm.comsystem.cpu1.num_int_alu_accesses 482657433 # Number of integer alu accesses 152310827Sandreas.hansson@arm.comsystem.cpu1.num_fp_alu_accesses 472663 # Number of float alu accesses 152410827Sandreas.hansson@arm.comsystem.cpu1.num_func_calls 26533376 # number of times a function call or return occured 152510827Sandreas.hansson@arm.comsystem.cpu1.num_conditional_control_insts 68272280 # number of instructions that are conditional controls 152610827Sandreas.hansson@arm.comsystem.cpu1.num_int_insts 482657433 # number of integer instructions 152710827Sandreas.hansson@arm.comsystem.cpu1.num_fp_insts 472663 # number of float instructions 152810827Sandreas.hansson@arm.comsystem.cpu1.num_int_register_reads 706740468 # number of times the integer registers were read 152910827Sandreas.hansson@arm.comsystem.cpu1.num_int_register_writes 383340050 # number of times the integer registers were written 153010827Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_reads 750974 # number of times the floating registers were read 153110827Sandreas.hansson@arm.comsystem.cpu1.num_fp_register_writes 430296 # number of times the floating registers were written 153210827Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_reads 118015071 # number of times the CC registers were read 153310827Sandreas.hansson@arm.comsystem.cpu1.num_cc_register_writes 117677935 # number of times the CC registers were written 153410827Sandreas.hansson@arm.comsystem.cpu1.num_mem_refs 160465117 # number of memory refs 153510827Sandreas.hansson@arm.comsystem.cpu1.num_load_insts 83993061 # Number of load instructions 153610827Sandreas.hansson@arm.comsystem.cpu1.num_store_insts 76472056 # Number of store instructions 153710827Sandreas.hansson@arm.comsystem.cpu1.num_idle_cycles 93999959015.450027 # Number of idle cycles 153810827Sandreas.hansson@arm.comsystem.cpu1.num_busy_cycles 1053950918.549978 # Number of busy cycles 153910827Sandreas.hansson@arm.comsystem.cpu1.not_idle_fraction 0.011088 # Percentage of non-idle cycles 154010827Sandreas.hansson@arm.comsystem.cpu1.idle_fraction 0.988912 # Percentage of idle cycles 154110827Sandreas.hansson@arm.comsystem.cpu1.Branches 99666047 # Number of branches fetched 154210827Sandreas.hansson@arm.comsystem.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 154310827Sandreas.hansson@arm.comsystem.cpu1.op_class::IntAlu 364374913 69.26% 69.26% # Class of executed instruction 154410827Sandreas.hansson@arm.comsystem.cpu1.op_class::IntMult 1108574 0.21% 69.47% # Class of executed instruction 154510827Sandreas.hansson@arm.comsystem.cpu1.op_class::IntDiv 57501 0.01% 69.48% # Class of executed instruction 154610827Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction 154710827Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction 154810827Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction 154910827Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction 155010827Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction 155110827Sandreas.hansson@arm.comsystem.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction 155210827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction 155310827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction 155410827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction 155510827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction 155610827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction 155710827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction 155810827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction 155910827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction 156010827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction 156110827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction 156210827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction 156310827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction 156410827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction 156510827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction 156610827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction 156710827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction 156810827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMisc 68224 0.01% 69.50% # Class of executed instruction 156910827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction 157010827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction 157110827Sandreas.hansson@arm.comsystem.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction 157210827Sandreas.hansson@arm.comsystem.cpu1.op_class::MemRead 83993061 15.97% 85.46% # Class of executed instruction 157310827Sandreas.hansson@arm.comsystem.cpu1.op_class::MemWrite 76472056 14.54% 100.00% # Class of executed instruction 157410535SN/Asystem.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 157510535SN/Asystem.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 157610827Sandreas.hansson@arm.comsystem.cpu1.op_class::total 526074372 # Class of executed instruction 157710535SN/Asystem.cpu1.kern.inst.arm 0 # number of arm instructions executed 157810827Sandreas.hansson@arm.comsystem.cpu1.kern.inst.quiesce 14059 # number of quiesce instructions executed 157910827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.replacements 5413042 # number of replacements 158010827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tagsinuse 455.092206 # Cycle average of tags in use 158110827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.total_refs 154856630 # Total number of references to valid blocks. 158210827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.sampled_refs 5413554 # Sample count of references to valid blocks. 158310827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.avg_refs 28.605354 # Average number of references to valid blocks. 158410827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.warmup_cycle 8382280704500 # Cycle when the warmup percentage was hit. 158510827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_blocks::cpu1.data 455.092206 # Average occupied blocks per requestor 158610827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::cpu1.data 0.888852 # Average percentage of cache occupancy 158710827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_percent::total 0.888852 # Average percentage of cache occupancy 158810827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 158910827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 159010827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id 159110827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id 159210827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 159310827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 159410827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.tag_accesses 326337345 # Number of tag accesses 159510827Sandreas.hansson@arm.comsystem.cpu1.dcache.tags.data_accesses 326337345 # Number of data accesses 159610827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::cpu1.data 78172197 # number of ReadReq hits 159710827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_hits::total 78172197 # number of ReadReq hits 159810827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::cpu1.data 72471418 # number of WriteReq hits 159910827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_hits::total 72471418 # number of WriteReq hits 160010827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::cpu1.data 183858 # number of SoftPFReq hits 160110827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_hits::total 183858 # number of SoftPFReq hits 160210827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197039 # number of WriteInvalidateReq hits 160310827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_hits::total 197039 # number of WriteInvalidateReq hits 160410827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1730902 # number of LoadLockedReq hits 160510827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_hits::total 1730902 # number of LoadLockedReq hits 160610827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::cpu1.data 1704111 # number of StoreCondReq hits 160710827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_hits::total 1704111 # number of StoreCondReq hits 160810827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::cpu1.data 150643615 # number of demand (read+write) hits 160910827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_hits::total 150643615 # number of demand (read+write) hits 161010827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::cpu1.data 150827473 # number of overall hits 161110827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_hits::total 150827473 # number of overall hits 161210827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::cpu1.data 3026410 # number of ReadReq misses 161310827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_misses::total 3026410 # number of ReadReq misses 161410827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::cpu1.data 1374450 # number of WriteReq misses 161510827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_misses::total 1374450 # number of WriteReq misses 161610827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::cpu1.data 681215 # number of SoftPFReq misses 161710827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_misses::total 681215 # number of SoftPFReq misses 161810827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 497314 # number of WriteInvalidateReq misses 161910827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_misses::total 497314 # number of WriteInvalidateReq misses 162010827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::cpu1.data 177400 # number of LoadLockedReq misses 162110827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_misses::total 177400 # number of LoadLockedReq misses 162210827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::cpu1.data 202765 # number of StoreCondReq misses 162310827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_misses::total 202765 # number of StoreCondReq misses 162410827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::cpu1.data 4400860 # number of demand (read+write) misses 162510827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_misses::total 4400860 # number of demand (read+write) misses 162610827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::cpu1.data 5082075 # number of overall misses 162710827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_misses::total 5082075 # number of overall misses 162810827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::cpu1.data 44105582717 # number of ReadReq miss cycles 162910827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_latency::total 44105582717 # number of ReadReq miss cycles 163010827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::cpu1.data 23281173553 # number of WriteReq miss cycles 163110827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_latency::total 23281173553 # number of WriteReq miss cycles 163210827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13579881027 # number of WriteInvalidateReq miss cycles 163310827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13579881027 # number of WriteInvalidateReq miss cycles 163410827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2688373759 # number of LoadLockedReq miss cycles 163510827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_latency::total 2688373759 # number of LoadLockedReq miss cycles 163610827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4348203540 # number of StoreCondReq miss cycles 163710827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_latency::total 4348203540 # number of StoreCondReq miss cycles 163810827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1867000 # number of StoreCondFailReq miss cycles 163910827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_miss_latency::total 1867000 # number of StoreCondFailReq miss cycles 164010827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::cpu1.data 67386756270 # number of demand (read+write) miss cycles 164110827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_latency::total 67386756270 # number of demand (read+write) miss cycles 164210827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::cpu1.data 67386756270 # number of overall miss cycles 164310827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_latency::total 67386756270 # number of overall miss cycles 164410827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::cpu1.data 81198607 # number of ReadReq accesses(hits+misses) 164510827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_accesses::total 81198607 # number of ReadReq accesses(hits+misses) 164610827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::cpu1.data 73845868 # number of WriteReq accesses(hits+misses) 164710827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_accesses::total 73845868 # number of WriteReq accesses(hits+misses) 164810827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::cpu1.data 865073 # number of SoftPFReq accesses(hits+misses) 164910827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_accesses::total 865073 # number of SoftPFReq accesses(hits+misses) 165010827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 694353 # number of WriteInvalidateReq accesses(hits+misses) 165110827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_accesses::total 694353 # number of WriteInvalidateReq accesses(hits+misses) 165210827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1908302 # number of LoadLockedReq accesses(hits+misses) 165310827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_accesses::total 1908302 # number of LoadLockedReq accesses(hits+misses) 165410827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1906876 # number of StoreCondReq accesses(hits+misses) 165510827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_accesses::total 1906876 # number of StoreCondReq accesses(hits+misses) 165610827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::cpu1.data 155044475 # number of demand (read+write) accesses 165710827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_accesses::total 155044475 # number of demand (read+write) accesses 165810827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::cpu1.data 155909548 # number of overall (read+write) accesses 165910827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_accesses::total 155909548 # number of overall (read+write) accesses 166010827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037272 # miss rate for ReadReq accesses 166110827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_miss_rate::total 0.037272 # miss rate for ReadReq accesses 166210827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018612 # miss rate for WriteReq accesses 166310827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_miss_rate::total 0.018612 # miss rate for WriteReq accesses 166410827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787465 # miss rate for SoftPFReq accesses 166510827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_miss_rate::total 0.787465 # miss rate for SoftPFReq accesses 166610827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.716226 # miss rate for WriteInvalidateReq accesses 166710827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.716226 # miss rate for WriteInvalidateReq accesses 166810827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092962 # miss rate for LoadLockedReq accesses 166910827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092962 # miss rate for LoadLockedReq accesses 167010827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106334 # miss rate for StoreCondReq accesses 167110827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_miss_rate::total 0.106334 # miss rate for StoreCondReq accesses 167210827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::cpu1.data 0.028385 # miss rate for demand accesses 167310827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_miss_rate::total 0.028385 # miss rate for demand accesses 167410827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::cpu1.data 0.032596 # miss rate for overall accesses 167510827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_miss_rate::total 0.032596 # miss rate for overall accesses 167610827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14573.564956 # average ReadReq miss latency 167710827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_miss_latency::total 14573.564956 # average ReadReq miss latency 167810827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16938.537999 # average WriteReq miss latency 167910827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_miss_latency::total 16938.537999 # average WriteReq miss latency 168010827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27306.452316 # average WriteInvalidateReq miss latency 168110827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27306.452316 # average WriteInvalidateReq miss latency 168210827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15154.305293 # average LoadLockedReq miss latency 168310827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15154.305293 # average LoadLockedReq miss latency 168410827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21444.546840 # average StoreCondReq miss latency 168510827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21444.546840 # average StoreCondReq miss latency 168610535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 168710535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 168810827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15312.179045 # average overall miss latency 168910827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_miss_latency::total 15312.179045 # average overall miss latency 169010827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13259.693387 # average overall miss latency 169110827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_miss_latency::total 13259.693387 # average overall miss latency 169210535SN/Asystem.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 169310535SN/Asystem.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 169410535SN/Asystem.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 169510535SN/Asystem.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 169610535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 169710535SN/Asystem.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 169810585SN/Asystem.cpu1.dcache.fast_writes 0 # number of fast writes performed 169910535SN/Asystem.cpu1.dcache.cache_copies 0 # number of cache copies performed 170010827Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::writebacks 3550271 # number of writebacks 170110827Sandreas.hansson@arm.comsystem.cpu1.dcache.writebacks::total 3550271 # number of writebacks 170210827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18006 # number of ReadReq MSHR hits 170310827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_hits::total 18006 # number of ReadReq MSHR hits 170410827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 425 # number of WriteReq MSHR hits 170510827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_hits::total 425 # number of WriteReq MSHR hits 170610827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44886 # number of LoadLockedReq MSHR hits 170710827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_hits::total 44886 # number of LoadLockedReq MSHR hits 170810827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::cpu1.data 18431 # number of demand (read+write) MSHR hits 170910827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_hits::total 18431 # number of demand (read+write) MSHR hits 171010827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::cpu1.data 18431 # number of overall MSHR hits 171110827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_hits::total 18431 # number of overall MSHR hits 171210827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3008404 # number of ReadReq MSHR misses 171310827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_misses::total 3008404 # number of ReadReq MSHR misses 171410827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1374025 # number of WriteReq MSHR misses 171510827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_misses::total 1374025 # number of WriteReq MSHR misses 171610827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 681215 # number of SoftPFReq MSHR misses 171710827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_misses::total 681215 # number of SoftPFReq MSHR misses 171810827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 497314 # number of WriteInvalidateReq MSHR misses 171910827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 497314 # number of WriteInvalidateReq MSHR misses 172010827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 132514 # number of LoadLockedReq MSHR misses 172110827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_misses::total 132514 # number of LoadLockedReq MSHR misses 172210827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202765 # number of StoreCondReq MSHR misses 172310827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_misses::total 202765 # number of StoreCondReq MSHR misses 172410827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::cpu1.data 4382429 # number of demand (read+write) MSHR misses 172510827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_misses::total 4382429 # number of demand (read+write) MSHR misses 172610827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::cpu1.data 5063644 # number of overall MSHR misses 172710827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_misses::total 5063644 # number of overall MSHR misses 172810827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21725 # number of ReadReq MSHR uncacheable 172910827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable::total 21725 # number of ReadReq MSHR uncacheable 173010827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable 173110827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable::total 20113 # number of WriteReq MSHR uncacheable 173210827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 41838 # number of overall MSHR uncacheable misses 173310827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_misses::total 41838 # number of overall MSHR uncacheable misses 173410827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38446720676 # number of ReadReq MSHR miss cycles 173510827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_latency::total 38446720676 # number of ReadReq MSHR miss cycles 173610827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21137642197 # number of WriteReq MSHR miss cycles 173710827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_latency::total 21137642197 # number of WriteReq MSHR miss cycles 173810827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13605784836 # number of SoftPFReq MSHR miss cycles 173910827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605784836 # number of SoftPFReq MSHR miss cycles 174010827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12830642973 # number of WriteInvalidateReq MSHR miss cycles 174110827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12830642973 # number of WriteInvalidateReq MSHR miss cycles 174210827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1690394742 # number of LoadLockedReq MSHR miss cycles 174310827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1690394742 # number of LoadLockedReq MSHR miss cycles 174410827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4033173960 # number of StoreCondReq MSHR miss cycles 174510827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4033173960 # number of StoreCondReq MSHR miss cycles 174610827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1807000 # number of StoreCondFailReq MSHR miss cycles 174710827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1807000 # number of StoreCondFailReq MSHR miss cycles 174810827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 59584362873 # number of demand (read+write) MSHR miss cycles 174910827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_latency::total 59584362873 # number of demand (read+write) MSHR miss cycles 175010827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 73190147709 # number of overall MSHR miss cycles 175110827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_latency::total 73190147709 # number of overall MSHR miss cycles 175210827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3727466501 # number of ReadReq MSHR uncacheable cycles 175310827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3727466501 # number of ReadReq MSHR uncacheable cycles 175410827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3465674500 # number of WriteReq MSHR uncacheable cycles 175510827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3465674500 # number of WriteReq MSHR uncacheable cycles 175610827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7193141001 # number of overall MSHR uncacheable cycles 175710827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_uncacheable_latency::total 7193141001 # number of overall MSHR uncacheable cycles 175810827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037050 # mshr miss rate for ReadReq accesses 175910827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037050 # mshr miss rate for ReadReq accesses 176010827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018607 # mshr miss rate for WriteReq accesses 176110827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018607 # mshr miss rate for WriteReq accesses 176210827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787465 # mshr miss rate for SoftPFReq accesses 176310827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787465 # mshr miss rate for SoftPFReq accesses 176410827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.716226 # mshr miss rate for WriteInvalidateReq accesses 176510827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.716226 # mshr miss rate for WriteInvalidateReq accesses 176610827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069441 # mshr miss rate for LoadLockedReq accesses 176710827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069441 # mshr miss rate for LoadLockedReq accesses 176810827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106334 # mshr miss rate for StoreCondReq accesses 176910827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106334 # mshr miss rate for StoreCondReq accesses 177010827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028266 # mshr miss rate for demand accesses 177110827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_mshr_miss_rate::total 0.028266 # mshr miss rate for demand accesses 177210827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032478 # mshr miss rate for overall accesses 177310827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_mshr_miss_rate::total 0.032478 # mshr miss rate for overall accesses 177410827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12779.773154 # average ReadReq mshr miss latency 177510827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12779.773154 # average ReadReq mshr miss latency 177610827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15383.739158 # average WriteReq mshr miss latency 177710827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15383.739158 # average WriteReq mshr miss latency 177810827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19972.820381 # average SoftPFReq mshr miss latency 177910827Sandreas.hansson@arm.comsystem.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19972.820381 # average SoftPFReq mshr miss latency 178010827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25799.882917 # average WriteInvalidateReq mshr miss latency 178110827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25799.882917 # average WriteInvalidateReq mshr miss latency 178210827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12756.348325 # average LoadLockedReq mshr miss latency 178310827Sandreas.hansson@arm.comsystem.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12756.348325 # average LoadLockedReq mshr miss latency 178410827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19890.878406 # average StoreCondReq mshr miss latency 178510827Sandreas.hansson@arm.comsystem.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19890.878406 # average StoreCondReq mshr miss latency 178610535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 178710535SN/Asystem.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 178810827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13596.195825 # average overall mshr miss latency 178910827Sandreas.hansson@arm.comsystem.cpu1.dcache.demand_avg_mshr_miss_latency::total 13596.195825 # average overall mshr miss latency 179010827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14454.046870 # average overall mshr miss latency 179110827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_miss_latency::total 14454.046870 # average overall mshr miss latency 179210827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171574.982785 # average ReadReq mshr uncacheable latency 179310827Sandreas.hansson@arm.comsystem.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171574.982785 # average ReadReq mshr uncacheable latency 179410827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172310.172525 # average WriteReq mshr uncacheable latency 179510827Sandreas.hansson@arm.comsystem.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172310.172525 # average WriteReq mshr uncacheable latency 179610827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171928.414384 # average overall mshr uncacheable latency 179710827Sandreas.hansson@arm.comsystem.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171928.414384 # average overall mshr uncacheable latency 179810535SN/Asystem.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 179910827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.replacements 4892397 # number of replacements 180010827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tagsinuse 496.394395 # Cycle average of tags in use 180110827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.total_refs 442086860 # Total number of references to valid blocks. 180210827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.sampled_refs 4892909 # Sample count of references to valid blocks. 180310827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.avg_refs 90.352561 # Average number of references to valid blocks. 180410827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.warmup_cycle 8382252985250 # Cycle when the warmup percentage was hit. 180510827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_blocks::cpu1.inst 496.394395 # Average occupied blocks per requestor 180610827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::cpu1.inst 0.969520 # Average percentage of cache occupancy 180710827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.occ_percent::total 0.969520 # Average percentage of cache occupancy 180810535SN/Asystem.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 180910827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 181010827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id 181110827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id 181210827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id 181310535SN/Asystem.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 181410827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.tag_accesses 898852462 # Number of tag accesses 181510827Sandreas.hansson@arm.comsystem.cpu1.icache.tags.data_accesses 898852462 # Number of data accesses 181610827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::cpu1.inst 442086860 # number of ReadReq hits 181710827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_hits::total 442086860 # number of ReadReq hits 181810827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::cpu1.inst 442086860 # number of demand (read+write) hits 181910827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_hits::total 442086860 # number of demand (read+write) hits 182010827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::cpu1.inst 442086860 # number of overall hits 182110827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_hits::total 442086860 # number of overall hits 182210827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::cpu1.inst 4892914 # number of ReadReq misses 182310827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_misses::total 4892914 # number of ReadReq misses 182410827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::cpu1.inst 4892914 # number of demand (read+write) misses 182510827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_misses::total 4892914 # number of demand (read+write) misses 182610827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::cpu1.inst 4892914 # number of overall misses 182710827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_misses::total 4892914 # number of overall misses 182810827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51771462698 # number of ReadReq miss cycles 182910827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_latency::total 51771462698 # number of ReadReq miss cycles 183010827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::cpu1.inst 51771462698 # number of demand (read+write) miss cycles 183110827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_latency::total 51771462698 # number of demand (read+write) miss cycles 183210827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::cpu1.inst 51771462698 # number of overall miss cycles 183310827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_latency::total 51771462698 # number of overall miss cycles 183410827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::cpu1.inst 446979774 # number of ReadReq accesses(hits+misses) 183510827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_accesses::total 446979774 # number of ReadReq accesses(hits+misses) 183610827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::cpu1.inst 446979774 # number of demand (read+write) accesses 183710827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_accesses::total 446979774 # number of demand (read+write) accesses 183810827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::cpu1.inst 446979774 # number of overall (read+write) accesses 183910827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_accesses::total 446979774 # number of overall (read+write) accesses 184010827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010947 # miss rate for ReadReq accesses 184110827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_miss_rate::total 0.010947 # miss rate for ReadReq accesses 184210827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::cpu1.inst 0.010947 # miss rate for demand accesses 184310827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_miss_rate::total 0.010947 # miss rate for demand accesses 184410827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::cpu1.inst 0.010947 # miss rate for overall accesses 184510827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_miss_rate::total 0.010947 # miss rate for overall accesses 184610827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10580.905918 # average ReadReq miss latency 184710827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_miss_latency::total 10580.905918 # average ReadReq miss latency 184810827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10580.905918 # average overall miss latency 184910827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_miss_latency::total 10580.905918 # average overall miss latency 185010827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10580.905918 # average overall miss latency 185110827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_miss_latency::total 10580.905918 # average overall miss latency 185210535SN/Asystem.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 185310535SN/Asystem.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 185410535SN/Asystem.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 185510535SN/Asystem.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 185610535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 185710535SN/Asystem.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 185810535SN/Asystem.cpu1.icache.fast_writes 0 # number of fast writes performed 185910535SN/Asystem.cpu1.icache.cache_copies 0 # number of cache copies performed 186010827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4892914 # number of ReadReq MSHR misses 186110827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_misses::total 4892914 # number of ReadReq MSHR misses 186210827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::cpu1.inst 4892914 # number of demand (read+write) MSHR misses 186310827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_misses::total 4892914 # number of demand (read+write) MSHR misses 186410827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::cpu1.inst 4892914 # number of overall MSHR misses 186510827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_misses::total 4892914 # number of overall MSHR misses 186610827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 186710827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 186810827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 186910827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 187010827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 46862593334 # number of ReadReq MSHR miss cycles 187110827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_latency::total 46862593334 # number of ReadReq MSHR miss cycles 187210827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 46862593334 # number of demand (read+write) MSHR miss cycles 187310827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_latency::total 46862593334 # number of demand (read+write) MSHR miss cycles 187410827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 46862593334 # number of overall MSHR miss cycles 187510827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_latency::total 46862593334 # number of overall MSHR miss cycles 187610827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10105750 # number of ReadReq MSHR uncacheable cycles 187710827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10105750 # number of ReadReq MSHR uncacheable cycles 187810827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10105750 # number of overall MSHR uncacheable cycles 187910827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_uncacheable_latency::total 10105750 # number of overall MSHR uncacheable cycles 188010827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for ReadReq accesses 188110827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_mshr_miss_rate::total 0.010947 # mshr miss rate for ReadReq accesses 188210827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for demand accesses 188310827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_mshr_miss_rate::total 0.010947 # mshr miss rate for demand accesses 188410827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for overall accesses 188510827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_mshr_miss_rate::total 0.010947 # mshr miss rate for overall accesses 188610827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average ReadReq mshr miss latency 188710827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9577.645005 # average ReadReq mshr miss latency 188810827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average overall mshr miss latency 188910827Sandreas.hansson@arm.comsystem.cpu1.icache.demand_avg_mshr_miss_latency::total 9577.645005 # average overall mshr miss latency 189010827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average overall mshr miss latency 189110827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_miss_latency::total 9577.645005 # average overall mshr miss latency 189210827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545 # average ReadReq mshr uncacheable latency 189310827Sandreas.hansson@arm.comsystem.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91870.454545 # average ReadReq mshr uncacheable latency 189410827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545 # average overall mshr uncacheable latency 189510827Sandreas.hansson@arm.comsystem.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91870.454545 # average overall mshr uncacheable latency 189610535SN/Asystem.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 189710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.num_hwpf_issued 7631682 # number of hwpf issued 189810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfIdentified 7631760 # number of prefetch candidates identified 189910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfBufferHit 35 # number of redundant prefetches already in prefetch queue 190010628SN/Asystem.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 190110628SN/Asystem.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 190210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.prefetcher.pfSpanPage 935080 # number of prefetches not generated due to page crossing 190310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.replacements 2142260 # number of replacements 190410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tagsinuse 13497.078408 # Cycle average of tags in use 190510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.total_refs 10799538 # Total number of references to valid blocks. 190610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.sampled_refs 2158371 # Sample count of references to valid blocks. 190710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.avg_refs 5.003560 # Average number of references to valid blocks. 190810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.warmup_cycle 9893608612000 # Cycle when the warmup percentage was hit. 190910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::writebacks 5297.531895 # Average occupied blocks per requestor 191010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 78.016993 # Average occupied blocks per requestor 191110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.104378 # Average occupied blocks per requestor 191210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3470.735386 # Average occupied blocks per requestor 191310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.data 3768.987855 # Average occupied blocks per requestor 191410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 794.701900 # Average occupied blocks per requestor 191510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::writebacks 0.323336 # Average percentage of cache occupancy 191610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004762 # Average percentage of cache occupancy 191710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005316 # Average percentage of cache occupancy 191810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.211837 # Average percentage of cache occupancy 191910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.data 0.230041 # Average percentage of cache occupancy 192010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048505 # Average percentage of cache occupancy 192110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_percent::total 0.823796 # Average percentage of cache occupancy 192210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1022 1633 # Occupied blocks per task id 192310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id 192410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_blocks::1024 14403 # Occupied blocks per task id 192510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::1 31 # Occupied blocks per task id 192610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id 192710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::3 713 # Occupied blocks per task id 192810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1022::4 761 # Occupied blocks per task id 192910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::3 32 # Occupied blocks per task id 193010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1023::4 43 # Occupied blocks per task id 193110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 193210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id 193310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1571 # Occupied blocks per task id 193410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5509 # Occupied blocks per task id 193510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6302 # Occupied blocks per task id 193610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1022 0.099670 # Percentage of cache occupancy per task id 193710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id 193810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.occ_task_id_percent::1024 0.879089 # Percentage of cache occupancy per task id 193910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.tag_accesses 240281832 # Number of tag accesses 194010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.tags.data_accesses 240281832 # Number of data accesses 194110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 248777 # number of ReadReq hits 194210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141659 # number of ReadReq hits 194310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.inst 4360207 # number of ReadReq hits 194410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::cpu1.data 2869888 # number of ReadReq hits 194510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_hits::total 7620531 # number of ReadReq hits 194610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::writebacks 3550270 # number of Writeback hits 194710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_hits::total 3550270 # number of Writeback hits 194810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 228063 # number of WriteInvalidateReq hits 194910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_hits::total 228063 # number of WriteInvalidateReq hits 195010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::cpu1.data 73786 # number of UpgradeReq hits 195110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_hits::total 73786 # number of UpgradeReq hits 195210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35221 # number of SCUpgradeReq hits 195310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_hits::total 35221 # number of SCUpgradeReq hits 195410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::cpu1.data 953536 # number of ReadExReq hits 195510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_hits::total 953536 # number of ReadExReq hits 195610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.dtb.walker 248777 # number of demand (read+write) hits 195710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.itb.walker 141659 # number of demand (read+write) hits 195810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.inst 4360207 # number of demand (read+write) hits 195910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::cpu1.data 3823424 # number of demand (read+write) hits 196010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_hits::total 8574067 # number of demand (read+write) hits 196110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.dtb.walker 248777 # number of overall hits 196210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.itb.walker 141659 # number of overall hits 196310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.inst 4360207 # number of overall hits 196410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::cpu1.data 3823424 # number of overall hits 196510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_hits::total 8574067 # number of overall hits 196610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9961 # number of ReadReq misses 196710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7958 # number of ReadReq misses 196810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.inst 532707 # number of ReadReq misses 196910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::cpu1.data 952245 # number of ReadReq misses 197010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_misses::total 1502871 # number of ReadReq misses 197110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 197210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses 197310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 267701 # number of WriteInvalidateReq misses 197410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_misses::total 267701 # number of WriteInvalidateReq misses 197510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120750 # number of UpgradeReq misses 197610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_misses::total 120750 # number of UpgradeReq misses 197710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167539 # number of SCUpgradeReq misses 197810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_misses::total 167539 # number of SCUpgradeReq misses 197910726SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 198010726SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 198110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::cpu1.data 227703 # number of ReadExReq misses 198210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_misses::total 227703 # number of ReadExReq misses 198310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9961 # number of demand (read+write) misses 198410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.itb.walker 7958 # number of demand (read+write) misses 198510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.inst 532707 # number of demand (read+write) misses 198610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::cpu1.data 1179948 # number of demand (read+write) misses 198710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_misses::total 1730574 # number of demand (read+write) misses 198810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9961 # number of overall misses 198910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.itb.walker 7958 # number of overall misses 199010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.inst 532707 # number of overall misses 199110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::cpu1.data 1179948 # number of overall misses 199210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_misses::total 1730574 # number of overall misses 199310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 394640977 # number of ReadReq miss cycles 199410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 358915726 # number of ReadReq miss cycles 199510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 16056528318 # number of ReadReq miss cycles 199610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 31264991014 # number of ReadReq miss cycles 199710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_miss_latency::total 48075076035 # number of ReadReq miss cycles 199810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 240883663 # number of WriteInvalidateReq miss cycles 199910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 240883663 # number of WriteInvalidateReq miss cycles 200010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2642176746 # number of UpgradeReq miss cycles 200110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_miss_latency::total 2642176746 # number of UpgradeReq miss cycles 200210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3519293594 # number of SCUpgradeReq miss cycles 200310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3519293594 # number of SCUpgradeReq miss cycles 200410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1767000 # number of SCUpgradeFailReq miss cycles 200510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1767000 # number of SCUpgradeFailReq miss cycles 200610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9869071556 # number of ReadExReq miss cycles 200710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_miss_latency::total 9869071556 # number of ReadExReq miss cycles 200810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 394640977 # number of demand (read+write) miss cycles 200910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358915726 # number of demand (read+write) miss cycles 201010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.inst 16056528318 # number of demand (read+write) miss cycles 201110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::cpu1.data 41134062570 # number of demand (read+write) miss cycles 201210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_miss_latency::total 57944147591 # number of demand (read+write) miss cycles 201310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 394640977 # number of overall miss cycles 201410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358915726 # number of overall miss cycles 201510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.inst 16056528318 # number of overall miss cycles 201610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::cpu1.data 41134062570 # number of overall miss cycles 201710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_latency::total 57944147591 # number of overall miss cycles 201810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 258738 # number of ReadReq accesses(hits+misses) 201910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149617 # number of ReadReq accesses(hits+misses) 202010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4892914 # number of ReadReq accesses(hits+misses) 202110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::cpu1.data 3822133 # number of ReadReq accesses(hits+misses) 202210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_accesses::total 9123402 # number of ReadReq accesses(hits+misses) 202310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::writebacks 3550271 # number of Writeback accesses(hits+misses) 202410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_accesses::total 3550271 # number of Writeback accesses(hits+misses) 202510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 495764 # number of WriteInvalidateReq accesses(hits+misses) 202610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_accesses::total 495764 # number of WriteInvalidateReq accesses(hits+misses) 202710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 194536 # number of UpgradeReq accesses(hits+misses) 202810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_accesses::total 194536 # number of UpgradeReq accesses(hits+misses) 202910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202760 # number of SCUpgradeReq accesses(hits+misses) 203010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_accesses::total 202760 # number of SCUpgradeReq accesses(hits+misses) 203110726SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 203210726SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 203310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1181239 # number of ReadExReq accesses(hits+misses) 203410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_accesses::total 1181239 # number of ReadExReq accesses(hits+misses) 203510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 258738 # number of demand (read+write) accesses 203610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149617 # number of demand (read+write) accesses 203710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.inst 4892914 # number of demand (read+write) accesses 203810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::cpu1.data 5003372 # number of demand (read+write) accesses 203910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_accesses::total 10304641 # number of demand (read+write) accesses 204010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 258738 # number of overall (read+write) accesses 204110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149617 # number of overall (read+write) accesses 204210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.inst 4892914 # number of overall (read+write) accesses 204310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::cpu1.data 5003372 # number of overall (read+write) accesses 204410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_accesses::total 10304641 # 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miss rate for overall accesses 206910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.108873 # miss rate for overall accesses 207010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::cpu1.data 0.235831 # miss rate for overall accesses 207110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_miss_rate::total 0.167941 # miss rate for overall accesses 207210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average ReadReq miss latency 207310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45101.247298 # average ReadReq miss latency 207410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30141.387889 # average ReadReq miss latency 207510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32832.927465 # average ReadReq miss latency 207610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_miss_latency::total 31988.824081 # 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number of demand (read+write) MSHR misses 213810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.inst 532707 # number of demand (read+write) MSHR misses 213910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::cpu1.data 1172319 # number of demand (read+write) MSHR misses 214010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_misses::total 1722945 # number of demand (read+write) MSHR misses 214110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9961 # number of overall MSHR misses 214210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7958 # number of overall MSHR misses 214310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.inst 532707 # number of overall MSHR misses 214410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.data 1172319 # number of overall MSHR misses 214510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 707306 # number of overall MSHR misses 214610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_misses::total 2430251 # number of overall MSHR misses 214710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 214810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21725 # number of ReadReq MSHR uncacheable 214910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21835 # number of ReadReq MSHR uncacheable 215010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable 215110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20113 # number of WriteReq MSHR uncacheable 215210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 215310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 41838 # number of overall MSHR uncacheable misses 215410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_misses::total 41948 # number of overall MSHR uncacheable misses 215510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of ReadReq MSHR miss cycles 215610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 306561274 # number of ReadReq MSHR miss cycles 215710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 12577785182 # number of ReadReq MSHR miss cycles 215810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 24989286886 # number of ReadReq MSHR miss cycles 215910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_latency::total 38202866865 # number of ReadReq MSHR miss cycles 216010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 35407537019 # number of HardPFReq MSHR miss cycles 216110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 35407537019 # number of HardPFReq MSHR miss cycles 216210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9092223824 # number of WriteInvalidateReq MSHR miss cycles 216310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 9092223824 # number of WriteInvalidateReq MSHR miss cycles 216410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2448079564 # number of UpgradeReq MSHR miss cycles 216510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2448079564 # number of UpgradeReq MSHR miss cycles 216610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2512705540 # number of SCUpgradeReq MSHR miss cycles 216710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2512705540 # number of SCUpgradeReq MSHR miss cycles 216810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1507000 # number of SCUpgradeFailReq MSHR miss cycles 216910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1507000 # number of SCUpgradeFailReq MSHR miss cycles 217010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7591763498 # number of ReadExReq MSHR miss cycles 217110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7591763498 # number of ReadExReq MSHR miss cycles 217210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of demand (read+write) MSHR miss cycles 217310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 306561274 # number of demand (read+write) MSHR miss cycles 217410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12577785182 # number of demand (read+write) MSHR miss cycles 217510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32581050384 # number of demand (read+write) MSHR miss cycles 217610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_latency::total 45794630363 # number of demand (read+write) MSHR miss cycles 217710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of overall MSHR miss cycles 217810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 306561274 # number of overall MSHR miss cycles 217910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12577785182 # number of overall MSHR miss cycles 218010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32581050384 # number of overall MSHR miss cycles 218110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 35407537019 # number of overall MSHR miss cycles 218210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_latency::total 81202167382 # number of overall MSHR miss cycles 218310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9241250 # number of ReadReq MSHR uncacheable cycles 218410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3553660750 # number of ReadReq MSHR uncacheable cycles 218510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3562902000 # number of ReadReq MSHR uncacheable cycles 218610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3314826000 # number of WriteReq MSHR uncacheable cycles 218710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3314826000 # number of WriteReq MSHR uncacheable cycles 218810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9241250 # number of overall MSHR uncacheable cycles 218910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 6868486750 # number of overall MSHR uncacheable cycles 219010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_uncacheable_latency::total 6877728000 # number of overall MSHR uncacheable cycles 219110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for ReadReq accesses 219210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for ReadReq accesses 219310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for ReadReq accesses 219410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.249027 # mshr miss rate for ReadReq accesses 219510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.164680 # mshr miss rate for ReadReq accesses 219610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 219710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 219810535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 219910535SN/Asystem.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 220010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.539975 # mshr miss rate for WriteInvalidateReq accesses 220110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.539975 # mshr miss rate for WriteInvalidateReq accesses 220210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.620708 # mshr miss rate for UpgradeReq accesses 220310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.620708 # mshr miss rate for UpgradeReq accesses 220410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826292 # mshr miss rate for SCUpgradeReq accesses 220510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.826292 # mshr miss rate for SCUpgradeReq accesses 220610535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 220710535SN/Asystem.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 220810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.186673 # mshr miss rate for ReadExReq accesses 220910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.186673 # mshr miss rate for ReadExReq accesses 221010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for demand accesses 221110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for demand accesses 221210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for demand accesses 221310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for demand accesses 221410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_mshr_miss_rate::total 0.167201 # mshr miss rate for demand accesses 221510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for overall accesses 221610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for overall accesses 221710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for overall accesses 221810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for overall accesses 221910535SN/Asystem.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 222010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_mshr_miss_rate::total 0.235840 # mshr miss rate for overall accesses 222110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average ReadReq mshr miss latency 222210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average ReadReq mshr miss latency 222310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average ReadReq mshr miss latency 222410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26254.408047 # average ReadReq mshr miss latency 222510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25427.233229 # average ReadReq mshr miss latency 222610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average HardPFReq mshr miss latency 222710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50059.715341 # average HardPFReq mshr miss latency 222810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33964.227957 # average WriteInvalidateReq mshr miss latency 222910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33964.227957 # average WriteInvalidateReq mshr miss latency 223010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20273.950841 # average UpgradeReq mshr miss latency 223110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20273.950841 # average UpgradeReq mshr miss latency 223210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14997.735095 # average SCUpgradeReq mshr miss latency 223310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14997.735095 # average SCUpgradeReq mshr miss latency 223410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 301400 # average SCUpgradeFailReq mshr miss latency 223510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 301400 # average SCUpgradeFailReq mshr miss latency 223610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34428.829592 # average ReadExReq mshr miss latency 223710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34428.829592 # average ReadExReq mshr miss latency 223810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency 223910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency 224010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency 224110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency 224210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26579.275811 # average overall mshr miss latency 224310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency 224410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency 224510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency 224610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency 224710827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average overall mshr miss latency 224810827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33413.078477 # average overall mshr miss latency 224910827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average ReadReq mshr uncacheable latency 225010827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163574.718067 # average ReadReq mshr uncacheable latency 225110827Sandreas.hansson@arm.comsystem.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163173.895123 # average ReadReq mshr uncacheable latency 225210827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 164810.122806 # average WriteReq mshr uncacheable latency 225310827Sandreas.hansson@arm.comsystem.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164810.122806 # average WriteReq mshr uncacheable latency 225410827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average overall mshr uncacheable latency 225510827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164168.620632 # average overall mshr uncacheable latency 225610827Sandreas.hansson@arm.comsystem.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163958.424716 # average overall mshr uncacheable latency 225710535SN/Asystem.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 225810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadReq 11407818 # Transaction distribution 225910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadResp 9339972 # Transaction distribution 226010827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution 226110827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteResp 20113 # Transaction distribution 226210827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::Writeback 3550271 # Transaction distribution 226310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::HardPFReq 1013669 # Transaction distribution 226410827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1157980 # Transaction distribution 226510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495764 # Transaction distribution 226610827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeReq 395206 # Transaction distribution 226710827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeReq 367201 # Transaction distribution 226810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeResp 457834 # Transaction distribution 226910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution 227010827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution 227110827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExReq 1341582 # Transaction distribution 227210827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.trans_dist::ReadExResp 1187599 # Transaction distribution 227310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9786048 # Packet count per connected master and slave (bytes) 227410827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15579584 # Packet count per connected master and slave (bytes) 227510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 330806 # Packet count per connected master and slave (bytes) 227610827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 594855 # Packet count per connected master and slave (bytes) 227710827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_count::total 26291293 # Packet count per connected master and slave (bytes) 227810827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 313146936 # Cumulative packet size per connected master and slave (bytes) 227910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 585201818 # Cumulative packet size per connected master and slave (bytes) 228010827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1196936 # Cumulative packet size per connected master and slave (bytes) 228110827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2069904 # Cumulative packet size per connected master and slave (bytes) 228210827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.pkt_size::total 901615594 # Cumulative packet size per connected master and slave (bytes) 228310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoops 4634762 # Total snoops (count) 228410827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::samples 19271924 # Request fanout histogram 228510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::mean 1.253755 # Request fanout histogram 228610827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::stdev 0.435159 # Request fanout histogram 228710535SN/Asystem.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 228810535SN/Asystem.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 228910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::1 14381570 74.62% 74.62% # Request fanout histogram 229010827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::2 4890354 25.38% 100.00% # Request fanout histogram 229110535SN/Asystem.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 229210827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 229310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 229410827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoop_fanout::total 19271924 # Request fanout histogram 229510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.reqLayer0.occupancy 11505600998 # Layer occupancy (ticks) 229610535SN/Asystem.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 229710827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.snoopLayer0.occupancy 168563993 # Layer occupancy (ticks) 229810535SN/Asystem.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 229910827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer0.occupancy 7347478432 # Layer occupancy (ticks) 230010535SN/Asystem.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 230110827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer1.occupancy 8042476622 # Layer occupancy (ticks) 230210535SN/Asystem.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 230310827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer2.occupancy 181503274 # Layer occupancy (ticks) 230410535SN/Asystem.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 230510827Sandreas.hansson@arm.comsystem.cpu1.toL2Bus.respLayer3.occupancy 336447522 # Layer occupancy (ticks) 230610535SN/Asystem.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 230710827Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadReq 40366 # Transaction distribution 230810827Sandreas.hansson@arm.comsystem.iobus.trans_dist::ReadResp 40366 # Transaction distribution 230910827Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteReq 136641 # Transaction distribution 231010827Sandreas.hansson@arm.comsystem.iobus.trans_dist::WriteResp 29913 # Transaction distribution 231110726SN/Asystem.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 231210827Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) 231310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 231410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 231510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 231610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 231710535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 231810535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 231910535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 232010535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 232110535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 232210726SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 232310535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 232410535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 232510535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 232610535SN/Asystem.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 232710827Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.bridge.master::total 122716 # Packet count per connected master and slave (bytes) 232810827Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) 232910827Sandreas.hansson@arm.comsystem.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) 233010535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 233110535SN/Asystem.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 233210827Sandreas.hansson@arm.comsystem.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes) 233310827Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) 233410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 233510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 233610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 233710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 233810535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 233910535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 234010535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 234110535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 234210535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 234310726SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 234410535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 234510535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 234610535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 234710535SN/Asystem.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 234810827Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.bridge.master::total 155823 # Cumulative packet size per connected master and slave (bytes) 234910827Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) 235010827Sandreas.hansson@arm.comsystem.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) 235110535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 235210535SN/Asystem.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 235310827Sandreas.hansson@arm.comsystem.iobus.pkt_size::total 7496797 # Cumulative packet size per connected master and slave (bytes) 235410827Sandreas.hansson@arm.comsystem.iobus.reqLayer0.occupancy 36274000 # Layer occupancy (ticks) 235510535SN/Asystem.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 235610535SN/Asystem.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 235710535SN/Asystem.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 235810535SN/Asystem.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 235910535SN/Asystem.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 236010535SN/Asystem.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 236110535SN/Asystem.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 236210535SN/Asystem.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 236310535SN/Asystem.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 236410535SN/Asystem.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 236510535SN/Asystem.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 236610535SN/Asystem.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 236710535SN/Asystem.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 236810535SN/Asystem.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 236910535SN/Asystem.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 237010535SN/Asystem.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 237110535SN/Asystem.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 237210535SN/Asystem.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 237310535SN/Asystem.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 237410726SN/Asystem.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) 237510535SN/Asystem.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 237610535SN/Asystem.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 237710535SN/Asystem.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 237810535SN/Asystem.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 237910535SN/Asystem.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 238010535SN/Asystem.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 238110535SN/Asystem.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 238210827Sandreas.hansson@arm.comsystem.iobus.reqLayer27.occupancy 607607215 # Layer occupancy (ticks) 238310535SN/Asystem.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 238410535SN/Asystem.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 238510535SN/Asystem.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 238610827Sandreas.hansson@arm.comsystem.iobus.respLayer0.occupancy 92806000 # Layer occupancy (ticks) 238710535SN/Asystem.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 238810827Sandreas.hansson@arm.comsystem.iobus.respLayer3.occupancy 148515621 # Layer occupancy (ticks) 238910535SN/Asystem.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 239010726SN/Asystem.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) 239110535SN/Asystem.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 239210827Sandreas.hansson@arm.comsystem.iocache.tags.replacements 115613 # number of replacements 239310827Sandreas.hansson@arm.comsystem.iocache.tags.tagsinuse 11.298152 # Cycle average of tags in use 239410535SN/Asystem.iocache.tags.total_refs 3 # Total number of references to valid blocks. 239510827Sandreas.hansson@arm.comsystem.iocache.tags.sampled_refs 115629 # Sample count of references to valid blocks. 239610535SN/Asystem.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 239710827Sandreas.hansson@arm.comsystem.iocache.tags.warmup_cycle 9179138787000 # Cycle when the warmup percentage was hit. 239810827Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ethernet 7.392909 # Average occupied blocks per requestor 239910827Sandreas.hansson@arm.comsystem.iocache.tags.occ_blocks::realview.ide 3.905243 # Average occupied blocks per requestor 240010827Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ethernet 0.462057 # Average percentage of cache occupancy 240110827Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::realview.ide 0.244078 # Average percentage of cache occupancy 240210827Sandreas.hansson@arm.comsystem.iocache.tags.occ_percent::total 0.706135 # Average percentage of cache occupancy 240310535SN/Asystem.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 240410535SN/Asystem.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 240510535SN/Asystem.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 240610827Sandreas.hansson@arm.comsystem.iocache.tags.tag_accesses 1040838 # Number of tag accesses 240710827Sandreas.hansson@arm.comsystem.iocache.tags.data_accesses 1040838 # Number of data accesses 240810535SN/Asystem.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 240910827Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses 241010827Sandreas.hansson@arm.comsystem.iocache.ReadReq_misses::total 8918 # number of ReadReq misses 241110535SN/Asystem.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 241210535SN/Asystem.iocache.WriteReq_misses::total 3 # number of WriteReq misses 241310726SN/Asystem.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 241410726SN/Asystem.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 241510535SN/Asystem.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 241610827Sandreas.hansson@arm.comsystem.iocache.demand_misses::realview.ide 8881 # number of demand (read+write) misses 241710827Sandreas.hansson@arm.comsystem.iocache.demand_misses::total 8921 # number of demand (read+write) misses 241810535SN/Asystem.iocache.overall_misses::realview.ethernet 40 # number of overall misses 241910827Sandreas.hansson@arm.comsystem.iocache.overall_misses::realview.ide 8881 # number of overall misses 242010827Sandreas.hansson@arm.comsystem.iocache.overall_misses::total 8921 # number of overall misses 242110726SN/Asystem.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles 242210827Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::realview.ide 1629816861 # number of ReadReq miss cycles 242310827Sandreas.hansson@arm.comsystem.iocache.ReadReq_miss_latency::total 1635012361 # number of ReadReq miss cycles 242410726SN/Asystem.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 242510726SN/Asystem.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 242610827Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::realview.ide 19901379733 # number of WriteInvalidateReq miss cycles 242710827Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_miss_latency::total 19901379733 # number of WriteInvalidateReq miss cycles 242810726SN/Asystem.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles 242910827Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::realview.ide 1629816861 # number of demand (read+write) miss cycles 243010827Sandreas.hansson@arm.comsystem.iocache.demand_miss_latency::total 1635381361 # number of demand (read+write) miss cycles 243110726SN/Asystem.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles 243210827Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::realview.ide 1629816861 # number of overall miss cycles 243310827Sandreas.hansson@arm.comsystem.iocache.overall_miss_latency::total 1635381361 # number of overall miss cycles 243410535SN/Asystem.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 243510827Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) 243610827Sandreas.hansson@arm.comsystem.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) 243710535SN/Asystem.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 243810535SN/Asystem.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 243910726SN/Asystem.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 244010726SN/Asystem.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 244110535SN/Asystem.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 244210827Sandreas.hansson@arm.comsystem.iocache.demand_accesses::realview.ide 8881 # number of demand (read+write) accesses 244310827Sandreas.hansson@arm.comsystem.iocache.demand_accesses::total 8921 # number of demand (read+write) accesses 244410535SN/Asystem.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 244510827Sandreas.hansson@arm.comsystem.iocache.overall_accesses::realview.ide 8881 # number of overall (read+write) accesses 244610827Sandreas.hansson@arm.comsystem.iocache.overall_accesses::total 8921 # number of overall (read+write) accesses 244710535SN/Asystem.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 244810535SN/Asystem.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 244910535SN/Asystem.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 245010535SN/Asystem.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 245110535SN/Asystem.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 245210585SN/Asystem.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 245310585SN/Asystem.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 245410535SN/Asystem.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 245510535SN/Asystem.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 245610535SN/Asystem.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 245710535SN/Asystem.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 245810535SN/Asystem.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 245910535SN/Asystem.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 246010726SN/Asystem.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency 246110827Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::realview.ide 183517.268438 # average ReadReq miss latency 246210827Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_miss_latency::total 183338.457165 # average ReadReq miss latency 246310726SN/Asystem.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 246410726SN/Asystem.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 246510827Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186468.215773 # average WriteInvalidateReq miss latency 246610827Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_miss_latency::total 186468.215773 # average WriteInvalidateReq miss latency 246710726SN/Asystem.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency 246810827Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::realview.ide 183517.268438 # average overall miss latency 246910827Sandreas.hansson@arm.comsystem.iocache.demand_avg_miss_latency::total 183318.166237 # average overall miss latency 247010726SN/Asystem.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency 247110827Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::realview.ide 183517.268438 # average overall miss latency 247210827Sandreas.hansson@arm.comsystem.iocache.overall_avg_miss_latency::total 183318.166237 # average overall miss latency 247310827Sandreas.hansson@arm.comsystem.iocache.blocked_cycles::no_mshrs 110961 # number of cycles access was blocked 247410535SN/Asystem.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 247510827Sandreas.hansson@arm.comsystem.iocache.blocked::no_mshrs 16203 # number of cycles access was blocked 247610535SN/Asystem.iocache.blocked::no_targets 0 # number of cycles access was blocked 247710827Sandreas.hansson@arm.comsystem.iocache.avg_blocked_cycles::no_mshrs 6.848176 # average number of cycles each access was blocked 247810535SN/Asystem.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 247910585SN/Asystem.iocache.fast_writes 0 # number of fast writes performed 248010535SN/Asystem.iocache.cache_copies 0 # number of cache copies performed 248110827Sandreas.hansson@arm.comsystem.iocache.writebacks::writebacks 106702 # number of writebacks 248210827Sandreas.hansson@arm.comsystem.iocache.writebacks::total 106702 # number of writebacks 248310535SN/Asystem.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 248410827Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::realview.ide 8881 # number of ReadReq MSHR misses 248510827Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_misses::total 8918 # number of ReadReq MSHR misses 248610535SN/Asystem.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 248710535SN/Asystem.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 248810726SN/Asystem.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses 248910726SN/Asystem.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses 249010535SN/Asystem.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 249110827Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::realview.ide 8881 # number of demand (read+write) MSHR misses 249210827Sandreas.hansson@arm.comsystem.iocache.demand_mshr_misses::total 8921 # number of demand (read+write) MSHR misses 249310535SN/Asystem.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 249410827Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::realview.ide 8881 # number of overall MSHR misses 249510827Sandreas.hansson@arm.comsystem.iocache.overall_mshr_misses::total 8921 # number of overall MSHR misses 249610726SN/Asystem.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles 249710827Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::realview.ide 1166890035 # number of ReadReq MSHR miss cycles 249810827Sandreas.hansson@arm.comsystem.iocache.ReadReq_mshr_miss_latency::total 1170160535 # number of ReadReq MSHR miss cycles 249910726SN/Asystem.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles 250010726SN/Asystem.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles 250110827Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14351455801 # number of WriteInvalidateReq MSHR miss cycles 250210827Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_mshr_miss_latency::total 14351455801 # number of WriteInvalidateReq MSHR miss cycles 250310726SN/Asystem.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles 250410827Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::realview.ide 1166890035 # number of demand (read+write) MSHR miss cycles 250510827Sandreas.hansson@arm.comsystem.iocache.demand_mshr_miss_latency::total 1170373535 # number of demand (read+write) MSHR miss cycles 250610726SN/Asystem.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles 250710827Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::realview.ide 1166890035 # number of overall MSHR miss cycles 250810827Sandreas.hansson@arm.comsystem.iocache.overall_mshr_miss_latency::total 1170373535 # number of overall MSHR miss cycles 250910535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 251010535SN/Asystem.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 251110535SN/Asystem.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 251210535SN/Asystem.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 251310535SN/Asystem.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 251410585SN/Asystem.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 251510585SN/Asystem.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 251610535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 251710535SN/Asystem.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 251810535SN/Asystem.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 251910535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 252010535SN/Asystem.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 252110535SN/Asystem.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 252210726SN/Asystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency 252310827Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131391.739106 # average ReadReq mshr miss latency 252410827Sandreas.hansson@arm.comsystem.iocache.ReadReq_avg_mshr_miss_latency::total 131213.336510 # average ReadReq mshr miss latency 252510726SN/Asystem.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency 252610726SN/Asystem.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency 252710827Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134467.579276 # average WriteInvalidateReq mshr miss latency 252810827Sandreas.hansson@arm.comsystem.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134467.579276 # average WriteInvalidateReq mshr miss latency 252910726SN/Asystem.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency 253010827Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::realview.ide 131391.739106 # average overall mshr miss latency 253110827Sandreas.hansson@arm.comsystem.iocache.demand_avg_mshr_miss_latency::total 131193.087658 # average overall mshr miss latency 253210726SN/Asystem.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency 253310827Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::realview.ide 131391.739106 # average overall mshr miss latency 253410827Sandreas.hansson@arm.comsystem.iocache.overall_avg_mshr_miss_latency::total 131193.087658 # average overall mshr miss latency 253510535SN/Asystem.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 253610827Sandreas.hansson@arm.comsystem.l2c.tags.replacements 1448041 # number of replacements 253710827Sandreas.hansson@arm.comsystem.l2c.tags.tagsinuse 64131.287175 # Cycle average of tags in use 253810827Sandreas.hansson@arm.comsystem.l2c.tags.total_refs 4245095 # Total number of references to valid blocks. 253910827Sandreas.hansson@arm.comsystem.l2c.tags.sampled_refs 1507106 # Sample count of references to valid blocks. 254010827Sandreas.hansson@arm.comsystem.l2c.tags.avg_refs 2.816720 # Average number of references to valid blocks. 254110827Sandreas.hansson@arm.comsystem.l2c.tags.warmup_cycle 11172879000 # Cycle when the warmup percentage was hit. 254210827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::writebacks 19347.050639 # Average occupied blocks per requestor 254310827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.dtb.walker 116.894544 # Average occupied blocks per requestor 254410827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.itb.walker 154.865125 # Average occupied blocks per requestor 254510827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.inst 3200.431152 # Average occupied blocks per requestor 254610827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.data 7856.746302 # Average occupied blocks per requestor 254710827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9704.320174 # Average occupied blocks per requestor 254810827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.dtb.walker 227.109782 # Average occupied blocks per requestor 254910827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.itb.walker 297.906768 # Average occupied blocks per requestor 255010827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.inst 3324.337079 # Average occupied blocks per requestor 255110827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.data 8639.334854 # Average occupied blocks per requestor 255210827Sandreas.hansson@arm.comsystem.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11262.290757 # Average occupied blocks per requestor 255310827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::writebacks 0.295213 # Average percentage of cache occupancy 255410827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.dtb.walker 0.001784 # Average percentage of cache occupancy 255510827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.itb.walker 0.002363 # Average percentage of cache occupancy 255610827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.inst 0.048835 # Average percentage of cache occupancy 255710827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.data 0.119884 # Average percentage of cache occupancy 255810827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148076 # Average percentage of cache occupancy 255910827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.dtb.walker 0.003465 # Average percentage of cache occupancy 256010827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.itb.walker 0.004546 # Average percentage of cache occupancy 256110827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.inst 0.050725 # Average percentage of cache occupancy 256210827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.data 0.131826 # Average percentage of cache occupancy 256310827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.171849 # Average percentage of cache occupancy 256410827Sandreas.hansson@arm.comsystem.l2c.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy 256510827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1022 10716 # Occupied blocks per task id 256610827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1023 318 # Occupied blocks per task id 256710827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_blocks::1024 48031 # Occupied blocks per task id 256810827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id 256910827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::2 38 # Occupied blocks per task id 257010827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::3 439 # Occupied blocks per task id 257110827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1022::4 10237 # Occupied blocks per task id 257210827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1023::4 318 # Occupied blocks per task id 257310827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 257410827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 257510827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::2 1326 # Occupied blocks per task id 257610827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::3 4887 # Occupied blocks per task id 257710827Sandreas.hansson@arm.comsystem.l2c.tags.age_task_id_blocks_1024::4 41702 # Occupied blocks per task id 257810827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1022 0.163513 # Percentage of cache occupancy per task id 257910827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1023 0.004852 # Percentage of cache occupancy per task id 258010827Sandreas.hansson@arm.comsystem.l2c.tags.occ_task_id_percent::1024 0.732895 # Percentage of cache occupancy per task id 258110827Sandreas.hansson@arm.comsystem.l2c.tags.tag_accesses 58352089 # Number of tag accesses 258210827Sandreas.hansson@arm.comsystem.l2c.tags.data_accesses 58352089 # Number of data accesses 258310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.dtb.walker 5485 # number of ReadReq hits 258410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.itb.walker 4305 # number of ReadReq hits 258510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.inst 465111 # number of ReadReq hits 258610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.data 536784 # number of ReadReq hits 258710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 265347 # number of ReadReq hits 258810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.dtb.walker 5257 # number of ReadReq hits 258910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.itb.walker 3875 # number of ReadReq hits 259010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.inst 485070 # number of ReadReq hits 259110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.data 556488 # number of ReadReq hits 259210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 285641 # number of ReadReq hits 259310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_hits::total 2613363 # number of ReadReq hits 259410827Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::writebacks 2374848 # number of Writeback hits 259510827Sandreas.hansson@arm.comsystem.l2c.Writeback_hits::total 2374848 # number of Writeback hits 259610827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::cpu0.data 123464 # number of WriteInvalidateReq hits 259710827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::cpu1.data 121626 # number of WriteInvalidateReq hits 259810827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_hits::total 245090 # number of WriteInvalidateReq hits 259910827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu0.data 24332 # number of UpgradeReq hits 260010827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::cpu1.data 31013 # number of UpgradeReq hits 260110827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_hits::total 55345 # number of UpgradeReq hits 260210827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu0.data 5518 # number of SCUpgradeReq hits 260310827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::cpu1.data 6203 # number of SCUpgradeReq hits 260410827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_hits::total 11721 # number of SCUpgradeReq hits 260510827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu0.data 54595 # number of ReadExReq hits 260610827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::cpu1.data 49708 # number of ReadExReq hits 260710827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_hits::total 104303 # number of ReadExReq hits 260810827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.dtb.walker 5485 # number of demand (read+write) hits 260910827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.itb.walker 4305 # number of demand (read+write) hits 261010827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.inst 465111 # number of demand (read+write) hits 261110827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.data 591379 # number of demand (read+write) hits 261210827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu0.l2cache.prefetcher 265347 # number of demand (read+write) hits 261310827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.dtb.walker 5257 # number of demand (read+write) hits 261410827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.itb.walker 3875 # number of demand (read+write) hits 261510827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.inst 485070 # number of demand (read+write) hits 261610827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.data 606196 # number of demand (read+write) hits 261710827Sandreas.hansson@arm.comsystem.l2c.demand_hits::cpu1.l2cache.prefetcher 285641 # number of demand (read+write) hits 261810827Sandreas.hansson@arm.comsystem.l2c.demand_hits::total 2717666 # number of demand (read+write) hits 261910827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.dtb.walker 5485 # number of overall hits 262010827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.itb.walker 4305 # number of overall hits 262110827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.inst 465111 # number of overall hits 262210827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.data 591379 # number of overall hits 262310827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu0.l2cache.prefetcher 265347 # number of overall hits 262410827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.dtb.walker 5257 # number of overall hits 262510827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.itb.walker 3875 # number of overall hits 262610827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.inst 485070 # number of overall hits 262710827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.data 606196 # number of overall hits 262810827Sandreas.hansson@arm.comsystem.l2c.overall_hits::cpu1.l2cache.prefetcher 285641 # number of overall hits 262910827Sandreas.hansson@arm.comsystem.l2c.overall_hits::total 2717666 # number of overall hits 263010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.dtb.walker 1889 # number of ReadReq misses 263110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.itb.walker 1930 # number of ReadReq misses 263210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.inst 50597 # number of ReadReq misses 263310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.data 131294 # number of ReadReq misses 263410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 216525 # number of ReadReq misses 263510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.dtb.walker 2185 # number of ReadReq misses 263610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.itb.walker 2247 # number of ReadReq misses 263710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.inst 47637 # number of ReadReq misses 263810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.data 122248 # number of ReadReq misses 263910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 240093 # number of ReadReq misses 264010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_misses::total 816645 # number of ReadReq misses 264110827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::cpu0.data 431801 # number of WriteInvalidateReq misses 264210827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::cpu1.data 136823 # number of WriteInvalidateReq misses 264310827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_misses::total 568624 # number of WriteInvalidateReq misses 264410827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu0.data 44180 # number of UpgradeReq misses 264510827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::cpu1.data 43907 # number of UpgradeReq misses 264610827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_misses::total 88087 # number of UpgradeReq misses 264710827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu0.data 9646 # number of SCUpgradeReq misses 264810827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::cpu1.data 11002 # number of SCUpgradeReq misses 264910827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_misses::total 20648 # number of SCUpgradeReq misses 265010827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu0.data 78703 # number of ReadExReq misses 265110827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::cpu1.data 53921 # number of ReadExReq misses 265210827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_misses::total 132624 # number of ReadExReq misses 265310827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.dtb.walker 1889 # number of demand (read+write) misses 265410827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.itb.walker 1930 # number of demand (read+write) misses 265510827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.inst 50597 # number of demand (read+write) misses 265610827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.data 209997 # number of demand (read+write) misses 265710827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu0.l2cache.prefetcher 216525 # number of demand (read+write) misses 265810827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.dtb.walker 2185 # number of demand (read+write) misses 265910827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.itb.walker 2247 # number of demand (read+write) misses 266010827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.inst 47637 # number of demand (read+write) misses 266110827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.data 176169 # number of demand (read+write) misses 266210827Sandreas.hansson@arm.comsystem.l2c.demand_misses::cpu1.l2cache.prefetcher 240093 # number of demand (read+write) misses 266310827Sandreas.hansson@arm.comsystem.l2c.demand_misses::total 949269 # number of demand (read+write) misses 266410827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.dtb.walker 1889 # number of overall misses 266510827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.itb.walker 1930 # number of overall misses 266610827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.inst 50597 # number of overall misses 266710827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.data 209997 # number of overall misses 266810827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu0.l2cache.prefetcher 216525 # number of overall misses 266910827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.dtb.walker 2185 # number of overall misses 267010827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.itb.walker 2247 # number of overall misses 267110827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.inst 47637 # number of overall misses 267210827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.data 176169 # number of overall misses 267310827Sandreas.hansson@arm.comsystem.l2c.overall_misses::cpu1.l2cache.prefetcher 240093 # number of overall misses 267410827Sandreas.hansson@arm.comsystem.l2c.overall_misses::total 949269 # number of overall misses 267510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.dtb.walker 170785750 # number of ReadReq miss cycles 267610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.itb.walker 176668500 # number of ReadReq miss cycles 267710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.inst 4301026862 # number of ReadReq miss cycles 267810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.data 11907133634 # number of ReadReq miss cycles 267910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of ReadReq miss cycles 268010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.dtb.walker 192678771 # number of ReadReq miss cycles 268110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.itb.walker 202084771 # number of ReadReq miss cycles 268210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.inst 4020493910 # number of ReadReq miss cycles 268310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.data 11059922872 # number of ReadReq miss cycles 268410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of ReadReq miss cycles 268510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_latency::total 90717840977 # number of ReadReq miss cycles 268610827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_latency::cpu0.data 51822854 # number of WriteInvalidateReq miss cycles 268710827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41218687 # number of WriteInvalidateReq miss cycles 268810827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_latency::total 93041541 # number of WriteInvalidateReq miss cycles 268910827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu0.data 233428095 # number of UpgradeReq miss cycles 269010827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::cpu1.data 271641854 # number of UpgradeReq miss cycles 269110827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_latency::total 505069949 # number of UpgradeReq miss cycles 269210827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu0.data 51474876 # number of SCUpgradeReq miss cycles 269310827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::cpu1.data 56093222 # number of SCUpgradeReq miss cycles 269410827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_latency::total 107568098 # number of SCUpgradeReq miss cycles 269510827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu0.data 6900295884 # number of ReadExReq miss cycles 269610827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::cpu1.data 4492674608 # number of ReadExReq miss cycles 269710827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_latency::total 11392970492 # number of ReadExReq miss cycles 269810827Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.dtb.walker 170785750 # number of demand (read+write) miss cycles 269910827Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.itb.walker 176668500 # number of demand (read+write) miss cycles 270010827Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.inst 4301026862 # number of demand (read+write) miss cycles 270110827Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.data 18807429518 # number of demand (read+write) miss cycles 270210827Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of demand (read+write) miss cycles 270310827Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.dtb.walker 192678771 # number of demand (read+write) miss cycles 270410827Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.itb.walker 202084771 # number of demand (read+write) miss cycles 270510827Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.inst 4020493910 # number of demand (read+write) miss cycles 270610827Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.data 15552597480 # number of demand (read+write) miss cycles 270710827Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of demand (read+write) miss cycles 270810827Sandreas.hansson@arm.comsystem.l2c.demand_miss_latency::total 102110811469 # number of demand (read+write) miss cycles 270910827Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.dtb.walker 170785750 # number of overall miss cycles 271010827Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.itb.walker 176668500 # number of overall miss cycles 271110827Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.inst 4301026862 # number of overall miss cycles 271210827Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.data 18807429518 # number of overall miss cycles 271310827Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of overall miss cycles 271410827Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.dtb.walker 192678771 # number of overall miss cycles 271510827Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.itb.walker 202084771 # number of overall miss cycles 271610827Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.inst 4020493910 # number of overall miss cycles 271710827Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.data 15552597480 # number of overall miss cycles 271810827Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of overall miss cycles 271910827Sandreas.hansson@arm.comsystem.l2c.overall_miss_latency::total 102110811469 # number of overall miss cycles 272010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.dtb.walker 7374 # number of ReadReq accesses(hits+misses) 272110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.itb.walker 6235 # number of ReadReq accesses(hits+misses) 272210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.inst 515708 # number of ReadReq accesses(hits+misses) 272310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.data 668078 # number of ReadReq accesses(hits+misses) 272410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 481872 # number of ReadReq accesses(hits+misses) 272510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.dtb.walker 7442 # number of ReadReq accesses(hits+misses) 272610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.itb.walker 6122 # number of ReadReq accesses(hits+misses) 272710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.inst 532707 # number of ReadReq accesses(hits+misses) 272810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.data 678736 # number of ReadReq accesses(hits+misses) 272910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 525734 # number of ReadReq accesses(hits+misses) 273010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_accesses::total 3430008 # number of ReadReq accesses(hits+misses) 273110827Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::writebacks 2374848 # number of Writeback accesses(hits+misses) 273210827Sandreas.hansson@arm.comsystem.l2c.Writeback_accesses::total 2374848 # number of Writeback accesses(hits+misses) 273310827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::cpu0.data 555265 # number of WriteInvalidateReq accesses(hits+misses) 273410827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::cpu1.data 258449 # number of WriteInvalidateReq accesses(hits+misses) 273510827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_accesses::total 813714 # number of WriteInvalidateReq accesses(hits+misses) 273610827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu0.data 68512 # number of UpgradeReq accesses(hits+misses) 273710827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::cpu1.data 74920 # number of UpgradeReq accesses(hits+misses) 273810827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_accesses::total 143432 # number of UpgradeReq accesses(hits+misses) 273910827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu0.data 15164 # number of SCUpgradeReq accesses(hits+misses) 274010827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::cpu1.data 17205 # number of SCUpgradeReq accesses(hits+misses) 274110827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_accesses::total 32369 # number of SCUpgradeReq accesses(hits+misses) 274210827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu0.data 133298 # number of ReadExReq accesses(hits+misses) 274310827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::cpu1.data 103629 # number of ReadExReq accesses(hits+misses) 274410827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_accesses::total 236927 # number of ReadExReq accesses(hits+misses) 274510827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.dtb.walker 7374 # number of demand (read+write) accesses 274610827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.itb.walker 6235 # number of demand (read+write) accesses 274710827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.inst 515708 # number of demand (read+write) accesses 274810827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.data 801376 # number of demand (read+write) accesses 274910827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu0.l2cache.prefetcher 481872 # number of demand (read+write) accesses 275010827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.dtb.walker 7442 # number of demand (read+write) accesses 275110827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.itb.walker 6122 # number of demand (read+write) accesses 275210827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.inst 532707 # number of demand (read+write) accesses 275310827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.data 782365 # number of demand (read+write) accesses 275410827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::cpu1.l2cache.prefetcher 525734 # number of demand (read+write) accesses 275510827Sandreas.hansson@arm.comsystem.l2c.demand_accesses::total 3666935 # number of demand (read+write) accesses 275610827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.dtb.walker 7374 # number of overall (read+write) accesses 275710827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.itb.walker 6235 # number of overall (read+write) accesses 275810827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.inst 515708 # number of overall (read+write) accesses 275910827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.data 801376 # number of overall (read+write) accesses 276010827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu0.l2cache.prefetcher 481872 # number of overall (read+write) accesses 276110827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.dtb.walker 7442 # number of overall (read+write) accesses 276210827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.itb.walker 6122 # number of overall (read+write) accesses 276310827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.inst 532707 # number of overall (read+write) accesses 276410827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.data 782365 # number of overall (read+write) accesses 276510827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::cpu1.l2cache.prefetcher 525734 # number of overall (read+write) accesses 276610827Sandreas.hansson@arm.comsystem.l2c.overall_accesses::total 3666935 # number of overall (read+write) accesses 276710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for ReadReq accesses 276810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.309543 # miss rate for ReadReq accesses 276910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.inst 0.098112 # miss rate for ReadReq accesses 277010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.data 0.196525 # miss rate for ReadReq accesses 277110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for ReadReq accesses 277210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for ReadReq accesses 277310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.367037 # miss rate for ReadReq accesses 277410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.inst 0.089424 # miss rate for ReadReq accesses 277510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.data 0.180111 # miss rate for ReadReq accesses 277610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for ReadReq accesses 277710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_miss_rate::total 0.238088 # miss rate for ReadReq accesses 277810827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.777649 # miss rate for WriteInvalidateReq accesses 277910827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.529400 # miss rate for WriteInvalidateReq accesses 278010827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_miss_rate::total 0.698801 # miss rate for WriteInvalidateReq accesses 278110827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu0.data 0.644851 # miss rate for UpgradeReq accesses 278210827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::cpu1.data 0.586052 # miss rate for UpgradeReq accesses 278310827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_miss_rate::total 0.614138 # miss rate for UpgradeReq accesses 278410827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.636112 # miss rate for SCUpgradeReq accesses 278510827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.639465 # miss rate for SCUpgradeReq accesses 278610827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_miss_rate::total 0.637894 # miss rate for SCUpgradeReq accesses 278710827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu0.data 0.590429 # miss rate for ReadExReq accesses 278810827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::cpu1.data 0.520327 # miss rate for ReadExReq accesses 278910827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_miss_rate::total 0.559767 # miss rate for ReadExReq accesses 279010827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for demand accesses 279110827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.itb.walker 0.309543 # miss rate for demand accesses 279210827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.inst 0.098112 # miss rate for demand accesses 279310827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.data 0.262046 # miss rate for demand accesses 279410827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for demand accesses 279510827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for demand accesses 279610827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.itb.walker 0.367037 # miss rate for demand accesses 279710827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.inst 0.089424 # miss rate for demand accesses 279810827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.data 0.225175 # miss rate for demand accesses 279910827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for demand accesses 280010827Sandreas.hansson@arm.comsystem.l2c.demand_miss_rate::total 0.258873 # miss rate for demand accesses 280110827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for overall accesses 280210827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.itb.walker 0.309543 # miss rate for overall accesses 280310827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.inst 0.098112 # miss rate for overall accesses 280410827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.data 0.262046 # miss rate for overall accesses 280510827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for overall accesses 280610827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for overall accesses 280710827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.itb.walker 0.367037 # miss rate for overall accesses 280810827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.inst 0.089424 # miss rate for overall accesses 280910827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.data 0.225175 # miss rate for overall accesses 281010827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for overall accesses 281110827Sandreas.hansson@arm.comsystem.l2c.overall_miss_rate::total 0.258873 # miss rate for overall accesses 281210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average ReadReq miss latency 281310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91538.082902 # average ReadReq miss latency 281410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.inst 85005.570726 # average ReadReq miss latency 281510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.data 90690.615215 # average ReadReq miss latency 281610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average ReadReq miss latency 281710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average ReadReq miss latency 281810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89935.367601 # average ReadReq miss latency 281910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.inst 84398.553855 # average ReadReq miss latency 282010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.data 90471.196846 # average ReadReq miss latency 282110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average ReadReq miss latency 282210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_miss_latency::total 111086.017764 # average ReadReq miss latency 282310827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 120.015595 # average WriteInvalidateReq miss latency 282410827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 301.255542 # average WriteInvalidateReq miss latency 282510827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_miss_latency::total 163.625772 # average WriteInvalidateReq miss latency 282610827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5283.569375 # average UpgradeReq miss latency 282710827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6186.755050 # average UpgradeReq miss latency 282810827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_miss_latency::total 5733.762632 # average UpgradeReq miss latency 282910827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5336.396019 # average SCUpgradeReq miss latency 283010827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5098.456826 # average SCUpgradeReq miss latency 283110827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_miss_latency::total 5209.613425 # average SCUpgradeReq miss latency 283210827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu0.data 87675.131621 # average ReadExReq miss latency 283310827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::cpu1.data 83319.571373 # average ReadExReq miss latency 283410827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_miss_latency::total 85904.289510 # average ReadExReq miss latency 283510827Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average overall miss latency 283610827Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.itb.walker 91538.082902 # average overall miss latency 283710827Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.inst 85005.570726 # average overall miss latency 283810827Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.data 89560.467616 # average overall miss latency 283910827Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average overall miss latency 284010827Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average overall miss latency 284110827Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.itb.walker 89935.367601 # average overall miss latency 284210827Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.inst 84398.553855 # average overall miss latency 284310827Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.data 88282.260103 # average overall miss latency 284410827Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average overall miss latency 284510827Sandreas.hansson@arm.comsystem.l2c.demand_avg_miss_latency::total 107567.835323 # average overall miss latency 284610827Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average overall miss latency 284710827Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.itb.walker 91538.082902 # average overall miss latency 284810827Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.inst 85005.570726 # average overall miss latency 284910827Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.data 89560.467616 # average overall miss latency 285010827Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average overall miss latency 285110827Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average overall miss latency 285210827Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.itb.walker 89935.367601 # average overall miss latency 285310827Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.inst 84398.553855 # average overall miss latency 285410827Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.data 88282.260103 # average overall miss latency 285510827Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average overall miss latency 285610827Sandreas.hansson@arm.comsystem.l2c.overall_avg_miss_latency::total 107567.835323 # average overall miss latency 285710827Sandreas.hansson@arm.comsystem.l2c.blocked_cycles::no_mshrs 328 # number of cycles access was blocked 285810515SN/Asystem.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 285910827Sandreas.hansson@arm.comsystem.l2c.blocked::no_mshrs 14 # number of cycles access was blocked 286010515SN/Asystem.l2c.blocked::no_targets 0 # number of cycles access was blocked 286110827Sandreas.hansson@arm.comsystem.l2c.avg_blocked_cycles::no_mshrs 23.428571 # average number of cycles each access was blocked 286210515SN/Asystem.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 286310515SN/Asystem.l2c.fast_writes 0 # number of fast writes performed 286410515SN/Asystem.l2c.cache_copies 0 # number of cache copies performed 286510827Sandreas.hansson@arm.comsystem.l2c.writebacks::writebacks 1121159 # number of writebacks 286610827Sandreas.hansson@arm.comsystem.l2c.writebacks::total 1121159 # number of writebacks 286710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu0.inst 120 # number of ReadReq MSHR hits 286810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu0.data 25 # number of ReadReq MSHR hits 286910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 287010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu1.inst 120 # number of ReadReq MSHR hits 287110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::cpu1.data 30 # number of ReadReq MSHR hits 287210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_hits::total 296 # number of ReadReq MSHR hits 287310827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.inst 120 # number of demand (read+write) MSHR hits 287410827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits 287510827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 287610827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.inst 120 # number of demand (read+write) MSHR hits 287710827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::cpu1.data 30 # number of demand (read+write) MSHR hits 287810827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits 287910827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.inst 120 # number of overall MSHR hits 288010827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits 288110827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 288210827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.inst 120 # number of overall MSHR hits 288310827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::cpu1.data 30 # number of overall MSHR hits 288410827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_hits::total 296 # number of overall MSHR hits 288510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1889 # number of ReadReq MSHR misses 288610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1930 # number of ReadReq MSHR misses 288710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.inst 50477 # number of ReadReq MSHR misses 288810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.data 131269 # number of ReadReq MSHR misses 288910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of ReadReq MSHR misses 289010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2184 # number of ReadReq MSHR misses 289110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2247 # number of ReadReq MSHR misses 289210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.inst 47517 # number of ReadReq MSHR misses 289310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.data 122218 # number of ReadReq MSHR misses 289410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of ReadReq MSHR misses 289510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_misses::total 816349 # number of ReadReq MSHR misses 289610827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 431801 # number of WriteInvalidateReq MSHR misses 289710827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 136823 # number of WriteInvalidateReq MSHR misses 289810827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_misses::total 568624 # number of WriteInvalidateReq MSHR misses 289910827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu0.data 44180 # number of UpgradeReq MSHR misses 290010827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::cpu1.data 43907 # number of UpgradeReq MSHR misses 290110827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_misses::total 88087 # number of UpgradeReq MSHR misses 290210827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9646 # number of SCUpgradeReq MSHR misses 290310827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11002 # number of SCUpgradeReq MSHR misses 290410827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_misses::total 20648 # number of SCUpgradeReq MSHR misses 290510827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu0.data 78703 # number of ReadExReq MSHR misses 290610827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::cpu1.data 53921 # number of ReadExReq MSHR misses 290710827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_misses::total 132624 # number of ReadExReq MSHR misses 290810827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.dtb.walker 1889 # number of demand (read+write) MSHR misses 290910827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.itb.walker 1930 # number of demand (read+write) MSHR misses 291010827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.inst 50477 # number of demand (read+write) MSHR misses 291110827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.data 209972 # number of demand (read+write) MSHR misses 291210827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of demand (read+write) MSHR misses 291310827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.dtb.walker 2184 # number of demand (read+write) MSHR misses 291410827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.itb.walker 2247 # number of demand (read+write) MSHR misses 291510827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.inst 47517 # number of demand (read+write) MSHR misses 291610827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.data 176139 # number of demand (read+write) MSHR misses 291710827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of demand (read+write) MSHR misses 291810827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_misses::total 948973 # number of demand (read+write) MSHR misses 291910827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.dtb.walker 1889 # number of overall MSHR misses 292010827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.itb.walker 1930 # number of overall MSHR misses 292110827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.inst 50477 # number of overall MSHR misses 292210827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.data 209972 # number of overall MSHR misses 292310827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of overall MSHR misses 292410827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.dtb.walker 2184 # number of overall MSHR misses 292510827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.itb.walker 2247 # number of overall MSHR misses 292610827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.inst 47517 # number of overall MSHR misses 292710827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.data 176139 # number of overall MSHR misses 292810827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of overall MSHR misses 292910827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_misses::total 948973 # number of overall MSHR misses 293010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 293110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable 293210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 293310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::cpu1.data 21723 # number of ReadReq MSHR uncacheable 293410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_uncacheable::total 81542 # number of ReadReq MSHR uncacheable 293510827Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable 293610827Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable 293710827Sandreas.hansson@arm.comsystem.l2c.WriteReq_mshr_uncacheable::total 38146 # number of WriteReq MSHR uncacheable 293810827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 293910827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses 294010827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 294110827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::cpu1.data 41836 # number of overall MSHR uncacheable misses 294210827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_misses::total 119688 # number of overall MSHR uncacheable misses 294310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of ReadReq MSHR miss cycles 294410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 152273500 # number of ReadReq MSHR miss cycles 294510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3658828888 # number of ReadReq MSHR miss cycles 294610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.data 10259837116 # number of ReadReq MSHR miss cycles 294710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of ReadReq MSHR miss cycles 294810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of ReadReq MSHR miss cycles 294910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 173733729 # 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number of overall MSHR uncacheable cycles 299710827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu0.data 4566310000 # number of overall MSHR uncacheable cycles 299810827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7049250 # number of overall MSHR uncacheable cycles 299910827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::cpu1.data 6071250250 # number of overall MSHR uncacheable cycles 300010827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_uncacheable_latency::total 13250369000 # number of overall MSHR uncacheable cycles 300110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for ReadReq accesses 300210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for ReadReq accesses 300310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for ReadReq accesses 300410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.196488 # mshr miss rate for ReadReq accesses 300510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for ReadReq accesses 300610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for ReadReq accesses 300710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for ReadReq accesses 300810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for ReadReq accesses 300910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.180067 # mshr miss rate for ReadReq accesses 301010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for ReadReq accesses 301110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_mshr_miss_rate::total 0.238002 # mshr miss rate for ReadReq accesses 301210827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.777649 # mshr miss rate for WriteInvalidateReq accesses 301310827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.529400 # mshr miss rate for WriteInvalidateReq accesses 301410827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.698801 # mshr miss rate for WriteInvalidateReq accesses 301510827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.644851 # mshr miss rate for UpgradeReq accesses 301610827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.586052 # mshr miss rate for UpgradeReq accesses 301710827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_mshr_miss_rate::total 0.614138 # mshr miss rate for UpgradeReq accesses 301810827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.636112 # mshr miss rate for SCUpgradeReq accesses 301910827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.639465 # mshr miss rate for SCUpgradeReq accesses 302010827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_mshr_miss_rate::total 0.637894 # mshr miss rate for SCUpgradeReq accesses 302110827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.590429 # mshr miss rate for ReadExReq accesses 302210827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.520327 # mshr miss rate for ReadExReq accesses 302310827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_mshr_miss_rate::total 0.559767 # mshr miss rate for ReadExReq accesses 302410827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for demand accesses 302510827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for demand accesses 302610827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for demand accesses 302710827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.data 0.262014 # mshr miss rate for demand accesses 302810827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for demand accesses 302910827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for demand accesses 303010827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for demand accesses 303110827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for demand accesses 303210827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.data 0.225137 # mshr miss rate for demand accesses 303310827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for demand accesses 303410827Sandreas.hansson@arm.comsystem.l2c.demand_mshr_miss_rate::total 0.258792 # mshr miss rate for demand accesses 303510827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for overall accesses 303610827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for overall accesses 303710827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for overall accesses 303810827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.data 0.262014 # mshr miss rate for overall accesses 303910827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for overall accesses 304010827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for overall accesses 304110827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for overall accesses 304210827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for overall accesses 304310827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.data 0.225137 # mshr miss rate for overall accesses 304410827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for overall accesses 304510827Sandreas.hansson@arm.comsystem.l2c.overall_mshr_miss_rate::total 0.258792 # mshr miss rate for overall accesses 304610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average ReadReq mshr miss latency 304710827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average ReadReq mshr miss latency 304810827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average ReadReq mshr miss latency 304910827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78158.873123 # average ReadReq mshr miss latency 305010827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average ReadReq mshr miss latency 305110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average ReadReq mshr miss latency 305210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average ReadReq mshr miss latency 305310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average ReadReq mshr miss latency 305410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77935.546548 # average ReadReq mshr miss latency 305510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average ReadReq mshr miss latency 305610827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_miss_latency::total 98694.338050 # average ReadReq mshr miss latency 305710827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32414.441254 # average WriteInvalidateReq mshr miss latency 305810827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31501.299584 # average WriteInvalidateReq mshr miss latency 305910827Sandreas.hansson@arm.comsystem.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32194.719992 # average WriteInvalidateReq mshr miss latency 306010827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17792.293775 # average UpgradeReq mshr miss latency 306110827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17779.972692 # average UpgradeReq mshr miss latency 306210827Sandreas.hansson@arm.comsystem.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.152327 # average UpgradeReq mshr miss latency 306310827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.024984 # average SCUpgradeReq mshr miss latency 306410827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17834.026632 # average SCUpgradeReq mshr miss latency 306510827Sandreas.hansson@arm.comsystem.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.164665 # average SCUpgradeReq mshr miss latency 306610827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75179.314842 # average ReadExReq mshr miss latency 306710827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70807.215964 # average ReadExReq mshr miss latency 306810827Sandreas.hansson@arm.comsystem.l2c.ReadExReq_avg_mshr_miss_latency::total 73401.748613 # average ReadExReq mshr miss latency 306910827Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average overall mshr miss latency 307010827Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average overall mshr miss latency 307110827Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average overall mshr miss latency 307210827Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.data 77042.056712 # average overall mshr miss latency 307310827Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average overall mshr miss latency 307410827Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average overall mshr miss latency 307510827Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average overall mshr miss latency 307610827Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average overall mshr miss latency 307710827Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.data 75753.368192 # average overall mshr miss latency 307810827Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average overall mshr miss latency 307910827Sandreas.hansson@arm.comsystem.l2c.demand_avg_mshr_miss_latency::total 95159.564794 # average overall mshr miss latency 308010827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average overall mshr miss latency 308110827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average overall mshr miss latency 308210827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average overall mshr miss latency 308310827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.data 77042.056712 # average overall mshr miss latency 308410827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average overall mshr miss latency 308510827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average overall mshr miss latency 308610827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average overall mshr miss latency 308710827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average overall mshr miss latency 308810827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.data 75753.368192 # average overall mshr miss latency 308910827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average overall mshr miss latency 309010827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_miss_latency::total 95159.564794 # average overall mshr miss latency 309110827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696 # average ReadReq mshr uncacheable latency 309210827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 135299.626146 # average ReadReq mshr uncacheable latency 309310827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909 # average ReadReq mshr uncacheable latency 309410827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144049.498228 # average ReadReq mshr uncacheable latency 309510827Sandreas.hansson@arm.comsystem.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97934.867921 # average ReadReq mshr uncacheable latency 309610827Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 128791.715189 # average WriteReq mshr uncacheable latency 309710827Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146276.686720 # average WriteReq mshr uncacheable latency 309810827Sandreas.hansson@arm.comsystem.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138010.905468 # average WriteReq mshr uncacheable latency 309910827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696 # average overall mshr uncacheable latency 310010827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 131909.466447 # average overall mshr uncacheable latency 310110827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909 # average overall mshr uncacheable latency 310210827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145120.237355 # average overall mshr uncacheable latency 310310827Sandreas.hansson@arm.comsystem.l2c.overall_avg_mshr_uncacheable_latency::total 110707.581378 # average overall mshr uncacheable latency 310410515SN/Asystem.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 310510827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadReq 906809 # Transaction distribution 310610827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 906809 # Transaction distribution 310710827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteReq 38146 # Transaction distribution 310810827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteResp 38146 # Transaction distribution 310910827Sandreas.hansson@arm.comsystem.membus.trans_dist::Writeback 1227861 # Transaction distribution 311010827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateReq 672387 # Transaction distribution 311110827Sandreas.hansson@arm.comsystem.membus.trans_dist::WriteInvalidateResp 672387 # Transaction distribution 311210827Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeReq 370275 # Transaction distribution 311310827Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeReq 320224 # Transaction distribution 311410827Sandreas.hansson@arm.comsystem.membus.trans_dist::UpgradeResp 115346 # Transaction distribution 311510827Sandreas.hansson@arm.comsystem.membus.trans_dist::SCUpgradeFailReq 24 # Transaction distribution 311610827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 145002 # Transaction distribution 311710827Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 128981 # Transaction distribution 311810827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122716 # Packet count per connected master and slave (bytes) 311910535SN/Asystem.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 312010827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24970 # Packet count per connected master and slave (bytes) 312110827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5055890 # Packet count per connected master and slave (bytes) 312210827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.l2c.mem_side::total 5203668 # Packet count per connected master and slave (bytes) 312310827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335590 # Packet count per connected master and slave (bytes) 312410827Sandreas.hansson@arm.comsystem.membus.pkt_count_system.iocache.mem_side::total 335590 # Packet count per connected master and slave (bytes) 312510827Sandreas.hansson@arm.comsystem.membus.pkt_count::total 5539258 # Packet count per connected master and slave (bytes) 312610827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155823 # Cumulative packet size per connected master and slave (bytes) 312710535SN/Asystem.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 312810827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49940 # Cumulative packet size per connected master and slave (bytes) 312910827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168605292 # Cumulative packet size per connected master and slave (bytes) 313010827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.l2c.mem_side::total 168811259 # Cumulative packet size per connected master and slave (bytes) 313110827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14076224 # Cumulative packet size per connected master and slave (bytes) 313210827Sandreas.hansson@arm.comsystem.membus.pkt_size_system.iocache.mem_side::total 14076224 # Cumulative packet size per connected master and slave (bytes) 313310827Sandreas.hansson@arm.comsystem.membus.pkt_size::total 182887483 # Cumulative packet size per connected master and slave (bytes) 313410827Sandreas.hansson@arm.comsystem.membus.snoops 594337 # Total snoops (count) 313510827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 3681134 # Request fanout histogram 313610535SN/Asystem.membus.snoop_fanout::mean 1 # Request fanout histogram 313710535SN/Asystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 313810535SN/Asystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 313910535SN/Asystem.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 314010827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 3681134 100.00% 100.00% # Request fanout histogram 314110535SN/Asystem.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 314210535SN/Asystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 314310535SN/Asystem.membus.snoop_fanout::min_value 1 # Request fanout histogram 314410535SN/Asystem.membus.snoop_fanout::max_value 1 # Request fanout histogram 314510827Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 3681134 # Request fanout histogram 314610827Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 100790999 # Layer occupancy (ticks) 314710535SN/Asystem.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 314810726SN/Asystem.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) 314910535SN/Asystem.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 315010827Sandreas.hansson@arm.comsystem.membus.reqLayer2.occupancy 21573500 # Layer occupancy (ticks) 315110535SN/Asystem.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 315210827Sandreas.hansson@arm.comsystem.membus.reqLayer5.occupancy 11112792344 # Layer occupancy (ticks) 315310535SN/Asystem.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 315410827Sandreas.hansson@arm.comsystem.membus.respLayer2.occupancy 5991933811 # Layer occupancy (ticks) 315510535SN/Asystem.membus.respLayer2.utilization 0.0 # Layer utilization (%) 315610827Sandreas.hansson@arm.comsystem.membus.respLayer3.occupancy 151912879 # Layer occupancy (ticks) 315710535SN/Asystem.membus.respLayer3.utilization 0.0 # Layer utilization (%) 315810515SN/Asystem.realview.ethernet.txBytes 966 # Bytes Transmitted 315910515SN/Asystem.realview.ethernet.txPackets 3 # Number of Packets Transmitted 316010515SN/Asystem.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 316110515SN/Asystem.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 316210515SN/Asystem.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 316310515SN/Asystem.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 316410515SN/Asystem.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 316510515SN/Asystem.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 316610515SN/Asystem.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 316710585SN/Asystem.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 316810515SN/Asystem.realview.ethernet.totPackets 3 # Total Packets 316910515SN/Asystem.realview.ethernet.totBytes 966 # Total Bytes 317010515SN/Asystem.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 317110585SN/Asystem.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 317210515SN/Asystem.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 317310515SN/Asystem.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 317410515SN/Asystem.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 317510515SN/Asystem.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 317610515SN/Asystem.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 317710515SN/Asystem.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 317810515SN/Asystem.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 317910515SN/Asystem.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 318010515SN/Asystem.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 318110515SN/Asystem.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 318210515SN/Asystem.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 318310515SN/Asystem.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 318410515SN/Asystem.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 318510515SN/Asystem.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 318610515SN/Asystem.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 318710515SN/Asystem.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 318810515SN/Asystem.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 318910515SN/Asystem.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 319010515SN/Asystem.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 319110515SN/Asystem.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 319210515SN/Asystem.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 319310515SN/Asystem.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 319410515SN/Asystem.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 319510515SN/Asystem.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 319610515SN/Asystem.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 319710515SN/Asystem.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 319810515SN/Asystem.realview.ethernet.postedInterrupts 13 # number of posts to CPU 319910515SN/Asystem.realview.ethernet.droppedPackets 0 # number of packets dropped 320010827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadReq 4327568 # Transaction distribution 320110827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadResp 4320333 # Transaction distribution 320210827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution 320310827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteResp 38146 # Transaction distribution 320410827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::Writeback 2374848 # Transaction distribution 320510827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteInvalidateReq 920665 # Transaction distribution 320610827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::WriteInvalidateResp 813714 # Transaction distribution 320710827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeReq 419012 # Transaction distribution 320810827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeReq 331945 # Transaction distribution 320910827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeResp 750957 # Transaction distribution 321010827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution 321110827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution 321210827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExReq 292509 # Transaction distribution 321310827Sandreas.hansson@arm.comsystem.toL2Bus.trans_dist::ReadExResp 292509 # Transaction distribution 321410827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7096014 # Packet count per connected master and slave (bytes) 321510827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6270717 # Packet count per connected master and slave (bytes) 321610827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_count::total 13366731 # Packet count per connected master and slave (bytes) 321710827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 236480377 # Cumulative packet size per connected master and slave (bytes) 321810827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202778754 # Cumulative packet size per connected master and slave (bytes) 321910827Sandreas.hansson@arm.comsystem.toL2Bus.pkt_size::total 439259131 # Cumulative packet size per connected master and slave (bytes) 322010827Sandreas.hansson@arm.comsystem.toL2Bus.snoops 1555479 # Total snoops (count) 322110827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::samples 8704899 # Request fanout histogram 322210827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::mean 1.013311 # Request fanout histogram 322310827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::stdev 0.114603 # Request fanout histogram 322410515SN/Asystem.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 322510515SN/Asystem.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 322610827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::1 8589027 98.67% 98.67% # Request fanout histogram 322710827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::2 115872 1.33% 100.00% # Request fanout histogram 322810515SN/Asystem.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 322910515SN/Asystem.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 323010515SN/Asystem.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 323110827Sandreas.hansson@arm.comsystem.toL2Bus.snoop_fanout::total 8704899 # Request fanout histogram 323210827Sandreas.hansson@arm.comsystem.toL2Bus.reqLayer0.occupancy 7795939791 # Layer occupancy (ticks) 323310515SN/Asystem.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 323410827Sandreas.hansson@arm.comsystem.toL2Bus.snoopLayer0.occupancy 2526000 # Layer occupancy (ticks) 323510515SN/Asystem.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 323610827Sandreas.hansson@arm.comsystem.toL2Bus.respLayer0.occupancy 3978610795 # Layer occupancy (ticks) 323710515SN/Asystem.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 323810827Sandreas.hansson@arm.comsystem.toL2Bus.respLayer1.occupancy 3846379763 # Layer occupancy (ticks) 323910515SN/Asystem.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 324010515SN/A 324110515SN/A---------- End Simulation Statistics ---------- 3242