1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.401371 # Number of seconds simulated 4sim_ticks 47401370587500 # Number of ticks simulated 5final_tick 47401370587500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1122973 # Simulator instruction rate (inst/s) 8host_op_rate 1337206 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 65940331964 # Simulator tick rate (ticks/s) 10host_mem_usage 757896 # Number of bytes of host memory used 11host_seconds 718.85 # Real time elapsed on the host 12sim_insts 807251718 # Number of instructions simulated 13sim_ops 961253990 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 62784 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 59776 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 2908084 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 11497800 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 12850688 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 108160 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 115584 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 2943416 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 9887760 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 11019584 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 443392 # Number of bytes read from this memory 28system.physmem.bytes_read::total 51897028 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 2908084 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 2943416 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 5851500 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 70859904 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 70880488 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 981 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 934 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 49846 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 179666 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 200792 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 1690 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1806 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 46079 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 154509 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 172181 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6928 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 815412 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1107186 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1109760 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 1325 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 1261 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 61350 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 242563 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 271104 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 2282 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 2438 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 62096 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 208597 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 232474 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9354 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1094842 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 61350 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 62096 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 123446 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1494891 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1495326 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1494891 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 1325 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 1261 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 61350 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 242997 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 271104 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 2282 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 2438 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 62096 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 208597 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 232474 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9354 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 2590168 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 815412 # Number of read requests accepted 85system.physmem.writeReqs 1109760 # Number of write requests accepted 86system.physmem.readBursts 815412 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1109760 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 52162176 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 24192 # Total number of bytes read from write queue 90system.physmem.bytesWritten 70877120 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 51897028 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 70880488 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 378 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2280 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 50443 # Per bank write bursts 97system.physmem.perBankRdBursts::1 58279 # Per bank write bursts 98system.physmem.perBankRdBursts::2 46176 # Per bank write bursts 99system.physmem.perBankRdBursts::3 52637 # Per bank write bursts 100system.physmem.perBankRdBursts::4 47826 # Per bank write bursts 101system.physmem.perBankRdBursts::5 55648 # Per bank write bursts 102system.physmem.perBankRdBursts::6 52176 # Per bank write bursts 103system.physmem.perBankRdBursts::7 51274 # Per bank write bursts 104system.physmem.perBankRdBursts::8 44248 # Per bank write bursts 105system.physmem.perBankRdBursts::9 55412 # Per bank write bursts 106system.physmem.perBankRdBursts::10 43487 # Per bank write bursts 107system.physmem.perBankRdBursts::11 55151 # Per bank write bursts 108system.physmem.perBankRdBursts::12 50800 # Per bank write bursts 109system.physmem.perBankRdBursts::13 57431 # Per bank write bursts 110system.physmem.perBankRdBursts::14 46539 # Per bank write bursts 111system.physmem.perBankRdBursts::15 47507 # Per bank write bursts 112system.physmem.perBankWrBursts::0 68734 # Per bank write bursts 113system.physmem.perBankWrBursts::1 74075 # Per bank write bursts 114system.physmem.perBankWrBursts::2 65910 # Per bank write bursts 115system.physmem.perBankWrBursts::3 69531 # Per bank write bursts 116system.physmem.perBankWrBursts::4 66080 # Per bank write bursts 117system.physmem.perBankWrBursts::5 73115 # Per bank write bursts 118system.physmem.perBankWrBursts::6 69817 # Per bank write bursts 119system.physmem.perBankWrBursts::7 69743 # Per bank write bursts 120system.physmem.perBankWrBursts::8 63555 # Per bank write bursts 121system.physmem.perBankWrBursts::9 71485 # Per bank write bursts 122system.physmem.perBankWrBursts::10 64662 # Per bank write bursts 123system.physmem.perBankWrBursts::11 72406 # Per bank write bursts 124system.physmem.perBankWrBursts::12 68380 # Per bank write bursts 125system.physmem.perBankWrBursts::13 74722 # Per bank write bursts 126system.physmem.perBankWrBursts::14 65945 # Per bank write bursts 127system.physmem.perBankWrBursts::15 69295 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 463 # Number of times write queue was full causing retry 130system.physmem.totGap 47401367297000 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 4795 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 5 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 810587 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1107186 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 559891 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 78604 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 37389 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 30365 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 26588 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 23379 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 20454 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 17072 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 14604 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 2581 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 1059 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 789 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 635 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 471 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 314 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 255 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 217 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 170 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 100 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 88 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 27848 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 35713 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 46446 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 51674 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 57512 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 59733 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 61607 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 63717 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 66102 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 66334 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 69492 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 71245 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 67739 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 66506 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 67172 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 70520 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 64778 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 61855 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 3835 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 1949 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 1570 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 1271 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 993 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 959 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 955 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 864 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 764 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 797 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 853 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 853 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 725 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 779 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 707 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 736 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 651 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 706 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 626 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 643 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 783 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 745 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 761 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 1111 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 881 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 672 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 1107 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 1228 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 1273 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 618 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 1057 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 862223 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 142.699715 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 97.984234 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 187.236614 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 572247 66.37% 66.37% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 178435 20.69% 87.06% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 41649 4.83% 91.89% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 18745 2.17% 94.07% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 13461 1.56% 95.63% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 8413 0.98% 96.60% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 6049 0.70% 97.31% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 5161 0.60% 97.91% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 18063 2.09% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 862223 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 57012 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 14.295727 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 26.624569 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-255 57003 99.98% 99.98% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::256-511 3 0.01% 99.99% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::512-767 3 0.01% 99.99% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::1280-1535 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::1536-1791 1 0.00% 100.00% # Reads before turning the bus around for writes 263system.physmem.rdPerTurnAround::5120-5375 1 0.00% 100.00% # Reads before turning the bus around for writes 264system.physmem.rdPerTurnAround::total 57012 # Reads before turning the bus around for writes 265system.physmem.wrPerTurnAround::samples 57012 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::mean 19.424946 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::gmean 18.563445 # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::stdev 8.850614 # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::16-19 45452 79.72% 79.72% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::20-23 4610 8.09% 87.81% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::24-27 2793 4.90% 92.71% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::28-31 1774 3.11% 95.82% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::32-35 1007 1.77% 97.59% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::36-39 224 0.39% 97.98% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::40-43 148 0.26% 98.24% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::44-47 47 0.08% 98.32% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::48-51 57 0.10% 98.42% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::52-55 22 0.04% 98.46% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::56-59 26 0.05% 98.51% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::60-63 34 0.06% 98.57% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::64-67 476 0.83% 99.40% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::68-71 79 0.14% 99.54% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::72-75 57 0.10% 99.64% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::76-79 65 0.11% 99.75% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::80-83 45 0.08% 99.83% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::84-87 1 0.00% 99.83% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::88-91 2 0.00% 99.84% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::92-95 2 0.00% 99.84% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::96-99 3 0.01% 99.85% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::100-103 2 0.00% 99.85% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::108-111 12 0.02% 99.87% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::112-115 1 0.00% 99.87% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::116-119 1 0.00% 99.87% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::120-123 4 0.01% 99.88% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::124-127 2 0.00% 99.88% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::128-131 16 0.03% 99.91% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::132-135 7 0.01% 99.92% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::136-139 4 0.01% 99.93% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::140-143 5 0.01% 99.94% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::144-147 3 0.01% 99.95% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::152-155 1 0.00% 99.95% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::156-159 3 0.01% 99.95% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::160-163 1 0.00% 99.95% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::168-171 2 0.00% 99.96% # Writes before turning the bus around for reads 305system.physmem.wrPerTurnAround::172-175 3 0.01% 99.96% # Writes before turning the bus around for reads 306system.physmem.wrPerTurnAround::176-179 2 0.00% 99.97% # Writes before turning the bus around for reads 307system.physmem.wrPerTurnAround::180-183 2 0.00% 99.97% # Writes before turning the bus around for reads 308system.physmem.wrPerTurnAround::188-191 9 0.02% 99.99% # Writes before turning the bus around for reads 309system.physmem.wrPerTurnAround::192-195 5 0.01% 99.99% # Writes before turning the bus around for reads 310system.physmem.wrPerTurnAround::196-199 1 0.00% 100.00% # Writes before turning the bus around for reads 311system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads 312system.physmem.wrPerTurnAround::252-255 1 0.00% 100.00% # Writes before turning the bus around for reads 313system.physmem.wrPerTurnAround::total 57012 # Writes before turning the bus around for reads 314system.physmem.totQLat 43191913053 # Total ticks spent queuing 315system.physmem.totMemAccLat 58473800553 # Total ticks spent from burst creation until serviced by the DRAM 316system.physmem.totBusLat 4075170000 # Total ticks spent in databus transfers 317system.physmem.avgQLat 52994.00 # Average queueing delay per DRAM burst 318system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 319system.physmem.avgMemAccLat 71744.00 # Average memory access latency per DRAM burst 320system.physmem.avgRdBW 1.10 # Average DRAM read bandwidth in MiByte/s 321system.physmem.avgWrBW 1.50 # Average achieved write bandwidth in MiByte/s 322system.physmem.avgRdBWSys 1.09 # Average system read bandwidth in MiByte/s 323system.physmem.avgWrBWSys 1.50 # Average system write bandwidth in MiByte/s 324system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 325system.physmem.busUtil 0.02 # Data bus utilization in percentage 326system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 327system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 328system.physmem.avgRdQLen 1.27 # Average read queue length when enqueuing 329system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing 330system.physmem.readRowHits 599171 # Number of row buffer hits during reads 331system.physmem.writeRowHits 461094 # Number of row buffer hits during writes 332system.physmem.readRowHitRate 73.51 # Row buffer hit rate for reads 333system.physmem.writeRowHitRate 41.63 # Row buffer hit rate for writes 334system.physmem.avgGap 24621886.93 # Average gap between requests 335system.physmem.pageHitRate 55.15 # Row buffer hit rate, read and write combined 336system.physmem_0.actEnergy 3125163720 # Energy for activate commands per rank (pJ) 337system.physmem_0.preEnergy 1661060115 # Energy for precharge commands per rank (pJ) 338system.physmem_0.readEnergy 2959237260 # Energy for read commands per rank (pJ) 339system.physmem_0.writeEnergy 2907566100 # Energy for write commands per rank (pJ) 340system.physmem_0.refreshEnergy 39767208000.000008 # Energy for refresh commands per rank (pJ) 341system.physmem_0.actBackEnergy 44841459390 # Energy for active background per rank (pJ) 342system.physmem_0.preBackEnergy 2203203840 # Energy for precharge background per rank (pJ) 343system.physmem_0.actPowerDownEnergy 73351636740 # Energy for active power-down per rank (pJ) 344system.physmem_0.prePowerDownEnergy 56747456160 # Energy for precharge power-down per rank (pJ) 345system.physmem_0.selfRefreshEnergy 11284217805975 # Energy for self refresh per rank (pJ) 346system.physmem_0.totalEnergy 11511799212150 # Total energy per rank (pJ) 347system.physmem_0.averagePower 242.857940 # Core power per rank (mW) 348system.physmem_0.totalIdleTime 47297258186903 # Total Idle time Per DRAM Rank 349system.physmem_0.memoryStateTime::IDLE 3926700752 # Time in different power states 350system.physmem_0.memoryStateTime::REF 16898782000 # Time in different power states 351system.physmem_0.memoryStateTime::SREF 46988619115750 # Time in different power states 352system.physmem_0.memoryStateTime::PRE_PDN 147779602583 # Time in different power states 353system.physmem_0.memoryStateTime::ACT 83286870095 # Time in different power states 354system.physmem_0.memoryStateTime::ACT_PDN 160859516320 # Time in different power states 355system.physmem_1.actEnergy 3031115640 # Energy for activate commands per rank (pJ) 356system.physmem_1.preEnergy 1611076170 # Energy for precharge commands per rank (pJ) 357system.physmem_1.readEnergy 2860105500 # Energy for read commands per rank (pJ) 358system.physmem_1.writeEnergy 2873349000 # Energy for write commands per rank (pJ) 359system.physmem_1.refreshEnergy 40284120240.000008 # Energy for refresh commands per rank (pJ) 360system.physmem_1.actBackEnergy 45341107710 # Energy for active background per rank (pJ) 361system.physmem_1.preBackEnergy 2193321120 # Energy for precharge background per rank (pJ) 362system.physmem_1.actPowerDownEnergy 73446933900 # Energy for active power-down per rank (pJ) 363system.physmem_1.prePowerDownEnergy 57703512480 # Energy for precharge power-down per rank (pJ) 364system.physmem_1.selfRefreshEnergy 11283525763155 # Energy for self refresh per rank (pJ) 365system.physmem_1.totalEnergy 11512888807215 # Total energy per rank (pJ) 366system.physmem_1.averagePower 242.880926 # Core power per rank (mW) 367system.physmem_1.totalIdleTime 47296183842356 # Total Idle time Per DRAM Rank 368system.physmem_1.memoryStateTime::IDLE 3879016799 # Time in different power states 369system.physmem_1.memoryStateTime::REF 17119770000 # Time in different power states 370system.physmem_1.memoryStateTime::SREF 46984848194500 # Time in different power states 371system.physmem_1.memoryStateTime::PRE_PDN 150269925291 # Time in different power states 372system.physmem_1.memoryStateTime::ACT 84186543595 # Time in different power states 373system.physmem_1.memoryStateTime::ACT_PDN 161067137315 # Time in different power states 374system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 375system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 376system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 377system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 378system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 379system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 380system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 381system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 382system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 383system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 384system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 385system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 386system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 387system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 388system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 389system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 390system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 391system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 392system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 393system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 394system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 395system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 396system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 397system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 398system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 399system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 400system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 401system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 402system.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 403system.bridge.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 404system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 405system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 406system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 407system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 408system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 409system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 410system.cpu_clk_domain.clock 500 # Clock period in ticks 411system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 412system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 413system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 414system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 415system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 416system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 417system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 418system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 419system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 420system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 421system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 422system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 423system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 424system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 425system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 426system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 427system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 428system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 429system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 430system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 431system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 432system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 433system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 434system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 435system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 436system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 437system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 438system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 439system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 440system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 441system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 442system.cpu0.dtb.walker.walks 92556 # Table walker walks requested 443system.cpu0.dtb.walker.walksLong 92556 # Table walker walks initiated with long descriptors 444system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 8240 # Level at which table walker walks with long descriptors terminate 445system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 69143 # Level at which table walker walks with long descriptors terminate 446system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting 447system.cpu0.dtb.walker.walkWaitTime::samples 92545 # Table walker wait (enqueue to first request) latency 448system.cpu0.dtb.walker.walkWaitTime::mean 0.280944 # Table walker wait (enqueue to first request) latency 449system.cpu0.dtb.walker.walkWaitTime::stdev 85.466687 # Table walker wait (enqueue to first request) latency 450system.cpu0.dtb.walker.walkWaitTime::0-2047 92544 100.00% 100.00% # Table walker wait (enqueue to first request) latency 451system.cpu0.dtb.walker.walkWaitTime::24576-26623 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 452system.cpu0.dtb.walker.walkWaitTime::total 92545 # Table walker wait (enqueue to first request) latency 453system.cpu0.dtb.walker.walkCompletionTime::samples 77394 # Table walker service (enqueue to completion) latency 454system.cpu0.dtb.walker.walkCompletionTime::mean 23265.414632 # Table walker service (enqueue to completion) latency 455system.cpu0.dtb.walker.walkCompletionTime::gmean 21722.582011 # Table walker service (enqueue to completion) latency 456system.cpu0.dtb.walker.walkCompletionTime::stdev 14143.873172 # Table walker service (enqueue to completion) latency 457system.cpu0.dtb.walker.walkCompletionTime::0-65535 76797 99.23% 99.23% # Table walker service (enqueue to completion) latency 458system.cpu0.dtb.walker.walkCompletionTime::65536-131071 427 0.55% 99.78% # Table walker service (enqueue to completion) latency 459system.cpu0.dtb.walker.walkCompletionTime::131072-196607 102 0.13% 99.91% # Table walker service (enqueue to completion) latency 460system.cpu0.dtb.walker.walkCompletionTime::196608-262143 27 0.03% 99.95% # Table walker service (enqueue to completion) latency 461system.cpu0.dtb.walker.walkCompletionTime::262144-327679 20 0.03% 99.97% # Table walker service (enqueue to completion) latency 462system.cpu0.dtb.walker.walkCompletionTime::327680-393215 12 0.02% 99.99% # Table walker service (enqueue to completion) latency 463system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 464system.cpu0.dtb.walker.walkCompletionTime::589824-655359 6 0.01% 100.00% # Table walker service (enqueue to completion) latency 465system.cpu0.dtb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 466system.cpu0.dtb.walker.walkCompletionTime::total 77394 # Table walker service (enqueue to completion) latency 467system.cpu0.dtb.walker.walksPending::samples 6740631600 # Table walker pending requests distribution 468system.cpu0.dtb.walker.walksPending::mean 0.619851 # Table walker pending requests distribution 469system.cpu0.dtb.walker.walksPending::stdev 0.485423 # Table walker pending requests distribution 470system.cpu0.dtb.walker.walksPending::0 2562444572 38.01% 38.01% # Table walker pending requests distribution 471system.cpu0.dtb.walker.walksPending::1 4178187028 61.99% 100.00% # Table walker pending requests distribution 472system.cpu0.dtb.walker.walksPending::total 6740631600 # Table walker pending requests distribution 473system.cpu0.dtb.walker.walkPageSizes::4K 69143 89.35% 89.35% # Table walker page sizes translated 474system.cpu0.dtb.walker.walkPageSizes::2M 8240 10.65% 100.00% # Table walker page sizes translated 475system.cpu0.dtb.walker.walkPageSizes::total 77383 # Table walker page sizes translated 476system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 92556 # Table walker requests started/completed, data/inst 477system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 478system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 92556 # Table walker requests started/completed, data/inst 479system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 77383 # Table walker requests started/completed, data/inst 480system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 481system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 77383 # Table walker requests started/completed, data/inst 482system.cpu0.dtb.walker.walkRequestOrigin::total 169939 # Table walker requests started/completed, data/inst 483system.cpu0.dtb.inst_hits 0 # ITB inst hits 484system.cpu0.dtb.inst_misses 0 # ITB inst misses 485system.cpu0.dtb.read_hits 77415423 # DTB read hits 486system.cpu0.dtb.read_misses 69730 # DTB read misses 487system.cpu0.dtb.write_hits 70114940 # DTB write hits 488system.cpu0.dtb.write_misses 22826 # DTB write misses 489system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 490system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 491system.cpu0.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID 492system.cpu0.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID 493system.cpu0.dtb.flush_entries 34306 # Number of entries that have been flushed from TLB 494system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 495system.cpu0.dtb.prefetch_faults 3960 # Number of TLB faults due to prefetch 496system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 497system.cpu0.dtb.perms_faults 8638 # Number of TLB faults due to permissions restrictions 498system.cpu0.dtb.read_accesses 77485153 # DTB read accesses 499system.cpu0.dtb.write_accesses 70137766 # DTB write accesses 500system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 501system.cpu0.dtb.hits 147530363 # DTB hits 502system.cpu0.dtb.misses 92556 # DTB misses 503system.cpu0.dtb.accesses 147622919 # DTB accesses 504system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 505system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 506system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 507system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 508system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 509system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 510system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 511system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 512system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 513system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 514system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 515system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 516system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 517system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 518system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 519system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 520system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 521system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 522system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 523system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 524system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 525system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 526system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 527system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 528system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 529system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 530system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 531system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 532system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 533system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 534system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 535system.cpu0.itb.walker.walks 51144 # Table walker walks requested 536system.cpu0.itb.walker.walksLong 51144 # Table walker walks initiated with long descriptors 537system.cpu0.itb.walker.walksLongTerminationLevel::Level2 535 # Level at which table walker walks with long descriptors terminate 538system.cpu0.itb.walker.walksLongTerminationLevel::Level3 45125 # Level at which table walker walks with long descriptors terminate 539system.cpu0.itb.walker.walkWaitTime::samples 51144 # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::0 51144 100.00% 100.00% # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkWaitTime::total 51144 # Table walker wait (enqueue to first request) latency 542system.cpu0.itb.walker.walkCompletionTime::samples 45660 # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::mean 24927.069645 # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::gmean 23080.556454 # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::stdev 20288.256560 # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::0-65535 45087 98.75% 98.75% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::65536-131071 348 0.76% 99.51% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::131072-196607 137 0.30% 99.81% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::196608-262143 34 0.07% 99.88% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::262144-327679 20 0.04% 99.93% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::327680-393215 10 0.02% 99.95% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::393216-458751 2 0.00% 99.95% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::524288-589823 1 0.00% 99.95% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::589824-655359 16 0.04% 99.99% # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::655360-720895 5 0.01% 100.00% # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walkCompletionTime::total 45660 # Table walker service (enqueue to completion) latency 557system.cpu0.itb.walker.walksPending::samples 618561500 # Table walker pending requests distribution 558system.cpu0.itb.walker.walksPending::0 618561500 100.00% 100.00% # Table walker pending requests distribution 559system.cpu0.itb.walker.walksPending::total 618561500 # Table walker pending requests distribution 560system.cpu0.itb.walker.walkPageSizes::4K 45125 98.83% 98.83% # Table walker page sizes translated 561system.cpu0.itb.walker.walkPageSizes::2M 535 1.17% 100.00% # Table walker page sizes translated 562system.cpu0.itb.walker.walkPageSizes::total 45660 # Table walker page sizes translated 563system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 564system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 51144 # Table walker requests started/completed, data/inst 565system.cpu0.itb.walker.walkRequestOrigin_Requested::total 51144 # Table walker requests started/completed, data/inst 566system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 567system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 45660 # Table walker requests started/completed, data/inst 568system.cpu0.itb.walker.walkRequestOrigin_Completed::total 45660 # Table walker requests started/completed, data/inst 569system.cpu0.itb.walker.walkRequestOrigin::total 96804 # Table walker requests started/completed, data/inst 570system.cpu0.itb.inst_hits 385005651 # ITB inst hits 571system.cpu0.itb.inst_misses 51144 # ITB inst misses 572system.cpu0.itb.read_hits 0 # DTB read hits 573system.cpu0.itb.read_misses 0 # DTB read misses 574system.cpu0.itb.write_hits 0 # DTB write hits 575system.cpu0.itb.write_misses 0 # DTB write misses 576system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 577system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 578system.cpu0.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID 579system.cpu0.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID 580system.cpu0.itb.flush_entries 24319 # Number of entries that have been flushed from TLB 581system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 582system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 583system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 584system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 585system.cpu0.itb.read_accesses 0 # DTB read accesses 586system.cpu0.itb.write_accesses 0 # DTB write accesses 587system.cpu0.itb.inst_accesses 385056795 # ITB inst accesses 588system.cpu0.itb.hits 385005651 # DTB hits 589system.cpu0.itb.misses 51144 # DTB misses 590system.cpu0.itb.accesses 385056795 # DTB accesses 591system.cpu0.numPwrStateTransitions 8306 # Number of power state transitions 592system.cpu0.pwrStateClkGateDist::samples 4153 # Distribution of time spent in the clock gated state 593system.cpu0.pwrStateClkGateDist::mean 11295325194.838190 # Distribution of time spent in the clock gated state 594system.cpu0.pwrStateClkGateDist::stdev 176339050181.920959 # Distribution of time spent in the clock gated state 595system.cpu0.pwrStateClkGateDist::underflows 2776 66.84% 66.84% # Distribution of time spent in the clock gated state 596system.cpu0.pwrStateClkGateDist::1000-5e+10 1353 32.58% 99.42% # Distribution of time spent in the clock gated state 597system.cpu0.pwrStateClkGateDist::5e+10-1e+11 6 0.14% 99.57% # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.59% # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.02% 99.61% # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::2.5e+11-3e+11 1 0.02% 99.64% # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.66% # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.69% # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::6e+11-6.5e+11 1 0.02% 99.71% # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::overflows 12 0.29% 100.00% # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::max_value 6953821743500 # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::total 4153 # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateResidencyTicks::ON 491885053337 # Cumulative time (in ticks) in various power states 609system.cpu0.pwrStateResidencyTicks::CLK_GATED 46909485534163 # Cumulative time (in ticks) in various power states 610system.cpu0.numCycles 94802741175 # number of cpu cycles simulated 611system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 612system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 613system.cpu0.kern.inst.arm 0 # number of arm instructions executed 614system.cpu0.kern.inst.quiesce 4153 # number of quiesce instructions executed 615system.cpu0.committedInsts 384730653 # Number of instructions committed 616system.cpu0.committedOps 456411878 # Number of ops (including micro ops) committed 617system.cpu0.num_int_alu_accesses 424236423 # Number of integer alu accesses 618system.cpu0.num_fp_alu_accesses 341428 # Number of float alu accesses 619system.cpu0.num_func_calls 24795410 # number of times a function call or return occured 620system.cpu0.num_conditional_control_insts 55287954 # number of instructions that are conditional controls 621system.cpu0.num_int_insts 424236423 # number of integer instructions 622system.cpu0.num_fp_insts 341428 # number of float instructions 623system.cpu0.num_int_register_reads 565685630 # number of times the integer registers were read 624system.cpu0.num_int_register_writes 332181203 # number of times the integer registers were written 625system.cpu0.num_fp_register_reads 574384 # number of times the floating registers were read 626system.cpu0.num_fp_register_writes 236428 # number of times the floating registers were written 627system.cpu0.num_cc_register_reads 85999446 # number of times the CC registers were read 628system.cpu0.num_cc_register_writes 85681176 # number of times the CC registers were written 629system.cpu0.num_mem_refs 147523428 # number of memory refs 630system.cpu0.num_load_insts 77412307 # Number of load instructions 631system.cpu0.num_store_insts 70111121 # Number of store instructions 632system.cpu0.num_idle_cycles 93818971068.324020 # Number of idle cycles 633system.cpu0.num_busy_cycles 983770106.675979 # Number of busy cycles 634system.cpu0.not_idle_fraction 0.010377 # Percentage of non-idle cycles 635system.cpu0.idle_fraction 0.989623 # Percentage of idle cycles 636system.cpu0.Branches 84896632 # Number of branches fetched 637system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 638system.cpu0.op_class::IntAlu 307975543 67.44% 67.44% # Class of executed instruction 639system.cpu0.op_class::IntMult 1108929 0.24% 67.68% # Class of executed instruction 640system.cpu0.op_class::IntDiv 55110 0.01% 67.69% # Class of executed instruction 641system.cpu0.op_class::FloatAdd 0 0.00% 67.69% # Class of executed instruction 642system.cpu0.op_class::FloatCmp 0 0.00% 67.69% # Class of executed instruction 643system.cpu0.op_class::FloatCvt 0 0.00% 67.69% # Class of executed instruction 644system.cpu0.op_class::FloatMult 0 0.00% 67.69% # Class of executed instruction 645system.cpu0.op_class::FloatMultAcc 0 0.00% 67.69% # Class of executed instruction 646system.cpu0.op_class::FloatDiv 0 0.00% 67.69% # Class of executed instruction 647system.cpu0.op_class::FloatMisc 28590 0.01% 67.70% # Class of executed instruction 648system.cpu0.op_class::FloatSqrt 0 0.00% 67.70% # Class of executed instruction 649system.cpu0.op_class::SimdAdd 0 0.00% 67.70% # Class of executed instruction 650system.cpu0.op_class::SimdAddAcc 0 0.00% 67.70% # Class of executed instruction 651system.cpu0.op_class::SimdAlu 0 0.00% 67.70% # Class of executed instruction 652system.cpu0.op_class::SimdCmp 0 0.00% 67.70% # Class of executed instruction 653system.cpu0.op_class::SimdCvt 0 0.00% 67.70% # Class of executed instruction 654system.cpu0.op_class::SimdMisc 0 0.00% 67.70% # Class of executed instruction 655system.cpu0.op_class::SimdMult 0 0.00% 67.70% # Class of executed instruction 656system.cpu0.op_class::SimdMultAcc 0 0.00% 67.70% # Class of executed instruction 657system.cpu0.op_class::SimdShift 0 0.00% 67.70% # Class of executed instruction 658system.cpu0.op_class::SimdShiftAcc 0 0.00% 67.70% # Class of executed instruction 659system.cpu0.op_class::SimdSqrt 0 0.00% 67.70% # Class of executed instruction 660system.cpu0.op_class::SimdFloatAdd 0 0.00% 67.70% # Class of executed instruction 661system.cpu0.op_class::SimdFloatAlu 0 0.00% 67.70% # Class of executed instruction 662system.cpu0.op_class::SimdFloatCmp 0 0.00% 67.70% # Class of executed instruction 663system.cpu0.op_class::SimdFloatCvt 0 0.00% 67.70% # Class of executed instruction 664system.cpu0.op_class::SimdFloatDiv 0 0.00% 67.70% # Class of executed instruction 665system.cpu0.op_class::SimdFloatMisc 0 0.00% 67.70% # Class of executed instruction 666system.cpu0.op_class::SimdFloatMult 0 0.00% 67.70% # Class of executed instruction 667system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.70% # Class of executed instruction 668system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.70% # Class of executed instruction 669system.cpu0.op_class::MemRead 77373487 16.94% 84.64% # Class of executed instruction 670system.cpu0.op_class::MemWrite 69837103 15.29% 99.93% # Class of executed instruction 671system.cpu0.op_class::FloatMemRead 38820 0.01% 99.94% # Class of executed instruction 672system.cpu0.op_class::FloatMemWrite 274018 0.06% 100.00% # Class of executed instruction 673system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 674system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 675system.cpu0.op_class::total 456691600 # Class of executed instruction 676system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 677system.cpu0.dcache.tags.replacements 5013046 # number of replacements 678system.cpu0.dcache.tags.tagsinuse 470.143979 # Cycle average of tags in use 679system.cpu0.dcache.tags.total_refs 142293396 # Total number of references to valid blocks. 680system.cpu0.dcache.tags.sampled_refs 5013556 # Sample count of references to valid blocks. 681system.cpu0.dcache.tags.avg_refs 28.381731 # Average number of references to valid blocks. 682system.cpu0.dcache.tags.warmup_cycle 637122000 # Cycle when the warmup percentage was hit. 683system.cpu0.dcache.tags.occ_blocks::cpu0.data 470.143979 # Average occupied blocks per requestor 684system.cpu0.dcache.tags.occ_percent::cpu0.data 0.918250 # Average percentage of cache occupancy 685system.cpu0.dcache.tags.occ_percent::total 0.918250 # Average percentage of cache occupancy 686system.cpu0.dcache.tags.occ_task_id_blocks::1024 510 # Occupied blocks per task id 687system.cpu0.dcache.tags.age_task_id_blocks_1024::0 11 # Occupied blocks per task id 688system.cpu0.dcache.tags.age_task_id_blocks_1024::1 199 # Occupied blocks per task id 689system.cpu0.dcache.tags.age_task_id_blocks_1024::2 299 # Occupied blocks per task id 690system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 691system.cpu0.dcache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id 692system.cpu0.dcache.tags.tag_accesses 300094424 # Number of tag accesses 693system.cpu0.dcache.tags.data_accesses 300094424 # Number of data accesses 694system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 695system.cpu0.dcache.ReadReq_hits::cpu0.data 72133805 # number of ReadReq hits 696system.cpu0.dcache.ReadReq_hits::total 72133805 # number of ReadReq hits 697system.cpu0.dcache.WriteReq_hits::cpu0.data 66092358 # number of WriteReq hits 698system.cpu0.dcache.WriteReq_hits::total 66092358 # number of WriteReq hits 699system.cpu0.dcache.SoftPFReq_hits::cpu0.data 186275 # number of SoftPFReq hits 700system.cpu0.dcache.SoftPFReq_hits::total 186275 # number of SoftPFReq hits 701system.cpu0.dcache.WriteLineReq_hits::cpu0.data 227046 # number of WriteLineReq hits 702system.cpu0.dcache.WriteLineReq_hits::total 227046 # number of WriteLineReq hits 703system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1654353 # number of LoadLockedReq hits 704system.cpu0.dcache.LoadLockedReq_hits::total 1654353 # number of LoadLockedReq hits 705system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1603859 # number of StoreCondReq hits 706system.cpu0.dcache.StoreCondReq_hits::total 1603859 # number of StoreCondReq hits 707system.cpu0.dcache.demand_hits::cpu0.data 138453209 # number of demand (read+write) hits 708system.cpu0.dcache.demand_hits::total 138453209 # number of demand (read+write) hits 709system.cpu0.dcache.overall_hits::cpu0.data 138639484 # number of overall hits 710system.cpu0.dcache.overall_hits::total 138639484 # number of overall hits 711system.cpu0.dcache.ReadReq_misses::cpu0.data 2704079 # number of ReadReq misses 712system.cpu0.dcache.ReadReq_misses::total 2704079 # number of ReadReq misses 713system.cpu0.dcache.WriteReq_misses::cpu0.data 1255388 # number of WriteReq misses 714system.cpu0.dcache.WriteReq_misses::total 1255388 # number of WriteReq misses 715system.cpu0.dcache.SoftPFReq_misses::cpu0.data 579222 # number of SoftPFReq misses 716system.cpu0.dcache.SoftPFReq_misses::total 579222 # number of SoftPFReq misses 717system.cpu0.dcache.WriteLineReq_misses::cpu0.data 722220 # number of WriteLineReq misses 718system.cpu0.dcache.WriteLineReq_misses::total 722220 # number of WriteLineReq misses 719system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 141818 # number of LoadLockedReq misses 720system.cpu0.dcache.LoadLockedReq_misses::total 141818 # number of LoadLockedReq misses 721system.cpu0.dcache.StoreCondReq_misses::cpu0.data 191065 # number of StoreCondReq misses 722system.cpu0.dcache.StoreCondReq_misses::total 191065 # number of StoreCondReq misses 723system.cpu0.dcache.demand_misses::cpu0.data 4681687 # number of demand (read+write) misses 724system.cpu0.dcache.demand_misses::total 4681687 # number of demand (read+write) misses 725system.cpu0.dcache.overall_misses::cpu0.data 5260909 # number of overall misses 726system.cpu0.dcache.overall_misses::total 5260909 # number of overall misses 727system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41586194000 # number of ReadReq miss cycles 728system.cpu0.dcache.ReadReq_miss_latency::total 41586194000 # number of ReadReq miss cycles 729system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 27254591500 # number of WriteReq miss cycles 730system.cpu0.dcache.WriteReq_miss_latency::total 27254591500 # number of WriteReq miss cycles 731system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 23833661500 # number of WriteLineReq miss cycles 732system.cpu0.dcache.WriteLineReq_miss_latency::total 23833661500 # number of WriteLineReq miss cycles 733system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2088985000 # number of LoadLockedReq miss cycles 734system.cpu0.dcache.LoadLockedReq_miss_latency::total 2088985000 # number of LoadLockedReq miss cycles 735system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4536311000 # number of StoreCondReq miss cycles 736system.cpu0.dcache.StoreCondReq_miss_latency::total 4536311000 # number of StoreCondReq miss cycles 737system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2828500 # number of StoreCondFailReq miss cycles 738system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2828500 # number of StoreCondFailReq miss cycles 739system.cpu0.dcache.demand_miss_latency::cpu0.data 92674447000 # number of demand (read+write) miss cycles 740system.cpu0.dcache.demand_miss_latency::total 92674447000 # number of demand (read+write) miss cycles 741system.cpu0.dcache.overall_miss_latency::cpu0.data 92674447000 # number of overall miss cycles 742system.cpu0.dcache.overall_miss_latency::total 92674447000 # number of overall miss cycles 743system.cpu0.dcache.ReadReq_accesses::cpu0.data 74837884 # number of ReadReq accesses(hits+misses) 744system.cpu0.dcache.ReadReq_accesses::total 74837884 # number of ReadReq accesses(hits+misses) 745system.cpu0.dcache.WriteReq_accesses::cpu0.data 67347746 # number of WriteReq accesses(hits+misses) 746system.cpu0.dcache.WriteReq_accesses::total 67347746 # number of WriteReq accesses(hits+misses) 747system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 765497 # number of SoftPFReq accesses(hits+misses) 748system.cpu0.dcache.SoftPFReq_accesses::total 765497 # number of SoftPFReq accesses(hits+misses) 749system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 949266 # number of WriteLineReq accesses(hits+misses) 750system.cpu0.dcache.WriteLineReq_accesses::total 949266 # number of WriteLineReq accesses(hits+misses) 751system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1796171 # number of LoadLockedReq accesses(hits+misses) 752system.cpu0.dcache.LoadLockedReq_accesses::total 1796171 # number of LoadLockedReq accesses(hits+misses) 753system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1794924 # number of StoreCondReq accesses(hits+misses) 754system.cpu0.dcache.StoreCondReq_accesses::total 1794924 # number of StoreCondReq accesses(hits+misses) 755system.cpu0.dcache.demand_accesses::cpu0.data 143134896 # number of demand (read+write) accesses 756system.cpu0.dcache.demand_accesses::total 143134896 # number of demand (read+write) accesses 757system.cpu0.dcache.overall_accesses::cpu0.data 143900393 # number of overall (read+write) accesses 758system.cpu0.dcache.overall_accesses::total 143900393 # number of overall (read+write) accesses 759system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036132 # miss rate for ReadReq accesses 760system.cpu0.dcache.ReadReq_miss_rate::total 0.036132 # miss rate for ReadReq accesses 761system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018640 # miss rate for WriteReq accesses 762system.cpu0.dcache.WriteReq_miss_rate::total 0.018640 # miss rate for WriteReq accesses 763system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.756661 # miss rate for SoftPFReq accesses 764system.cpu0.dcache.SoftPFReq_miss_rate::total 0.756661 # miss rate for SoftPFReq accesses 765system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.760819 # miss rate for WriteLineReq accesses 766system.cpu0.dcache.WriteLineReq_miss_rate::total 0.760819 # miss rate for WriteLineReq accesses 767system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.078956 # miss rate for LoadLockedReq accesses 768system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.078956 # miss rate for LoadLockedReq accesses 769system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.106447 # miss rate for StoreCondReq accesses 770system.cpu0.dcache.StoreCondReq_miss_rate::total 0.106447 # miss rate for StoreCondReq accesses 771system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032708 # miss rate for demand accesses 772system.cpu0.dcache.demand_miss_rate::total 0.032708 # miss rate for demand accesses 773system.cpu0.dcache.overall_miss_rate::cpu0.data 0.036559 # miss rate for overall accesses 774system.cpu0.dcache.overall_miss_rate::total 0.036559 # miss rate for overall accesses 775system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15379.060301 # average ReadReq miss latency 776system.cpu0.dcache.ReadReq_avg_miss_latency::total 15379.060301 # average ReadReq miss latency 777system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21710.094011 # average WriteReq miss latency 778system.cpu0.dcache.WriteReq_avg_miss_latency::total 21710.094011 # average WriteReq miss latency 779system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 33000.555925 # average WriteLineReq miss latency 780system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 33000.555925 # average WriteLineReq miss latency 781system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14730.041321 # average LoadLockedReq miss latency 782system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14730.041321 # average LoadLockedReq miss latency 783system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23742.239552 # average StoreCondReq miss latency 784system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23742.239552 # average StoreCondReq miss latency 785system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 786system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 787system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19795.096725 # average overall miss latency 788system.cpu0.dcache.demand_avg_miss_latency::total 19795.096725 # average overall miss latency 789system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 17615.671930 # average overall miss latency 790system.cpu0.dcache.overall_avg_miss_latency::total 17615.671930 # average overall miss latency 791system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 792system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 793system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 794system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 795system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 796system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 797system.cpu0.dcache.writebacks::writebacks 5013046 # number of writebacks 798system.cpu0.dcache.writebacks::total 5013046 # number of writebacks 799system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 26558 # number of ReadReq MSHR hits 800system.cpu0.dcache.ReadReq_mshr_hits::total 26558 # number of ReadReq MSHR hits 801system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21241 # number of WriteReq MSHR hits 802system.cpu0.dcache.WriteReq_mshr_hits::total 21241 # number of WriteReq MSHR hits 803system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 37285 # number of LoadLockedReq MSHR hits 804system.cpu0.dcache.LoadLockedReq_mshr_hits::total 37285 # number of LoadLockedReq MSHR hits 805system.cpu0.dcache.demand_mshr_hits::cpu0.data 47799 # number of demand (read+write) MSHR hits 806system.cpu0.dcache.demand_mshr_hits::total 47799 # number of demand (read+write) MSHR hits 807system.cpu0.dcache.overall_mshr_hits::cpu0.data 47799 # number of overall MSHR hits 808system.cpu0.dcache.overall_mshr_hits::total 47799 # number of overall MSHR hits 809system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2677521 # number of ReadReq MSHR misses 810system.cpu0.dcache.ReadReq_mshr_misses::total 2677521 # number of ReadReq MSHR misses 811system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1234147 # number of WriteReq MSHR misses 812system.cpu0.dcache.WriteReq_mshr_misses::total 1234147 # number of WriteReq MSHR misses 813system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 577585 # number of SoftPFReq MSHR misses 814system.cpu0.dcache.SoftPFReq_mshr_misses::total 577585 # number of SoftPFReq MSHR misses 815system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 722220 # number of WriteLineReq MSHR misses 816system.cpu0.dcache.WriteLineReq_mshr_misses::total 722220 # number of WriteLineReq MSHR misses 817system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104533 # number of LoadLockedReq MSHR misses 818system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104533 # number of LoadLockedReq MSHR misses 819system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 191065 # number of StoreCondReq MSHR misses 820system.cpu0.dcache.StoreCondReq_mshr_misses::total 191065 # number of StoreCondReq MSHR misses 821system.cpu0.dcache.demand_mshr_misses::cpu0.data 4633888 # number of demand (read+write) MSHR misses 822system.cpu0.dcache.demand_mshr_misses::total 4633888 # number of demand (read+write) MSHR misses 823system.cpu0.dcache.overall_mshr_misses::cpu0.data 5211473 # number of overall MSHR misses 824system.cpu0.dcache.overall_mshr_misses::total 5211473 # number of overall MSHR misses 825system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable 826system.cpu0.dcache.ReadReq_mshr_uncacheable::total 15891 # number of ReadReq MSHR uncacheable 827system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable 828system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16800 # number of WriteReq MSHR uncacheable 829system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses 830system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32691 # number of overall MSHR uncacheable misses 831system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 37485691500 # number of ReadReq MSHR miss cycles 832system.cpu0.dcache.ReadReq_mshr_miss_latency::total 37485691500 # number of ReadReq MSHR miss cycles 833system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 25473400500 # number of WriteReq MSHR miss cycles 834system.cpu0.dcache.WriteReq_mshr_miss_latency::total 25473400500 # number of WriteReq MSHR miss cycles 835system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13565827500 # number of SoftPFReq MSHR miss cycles 836system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13565827500 # number of SoftPFReq MSHR miss cycles 837system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 23111441500 # number of WriteLineReq MSHR miss cycles 838system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 23111441500 # number of WriteLineReq MSHR miss cycles 839system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1404174500 # number of LoadLockedReq MSHR miss cycles 840system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1404174500 # number of LoadLockedReq MSHR miss cycles 841system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4345314000 # number of StoreCondReq MSHR miss cycles 842system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4345314000 # number of StoreCondReq MSHR miss cycles 843system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2760500 # number of StoreCondFailReq MSHR miss cycles 844system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2760500 # number of StoreCondFailReq MSHR miss cycles 845system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 86070533500 # number of demand (read+write) MSHR miss cycles 846system.cpu0.dcache.demand_mshr_miss_latency::total 86070533500 # number of demand (read+write) MSHR miss cycles 847system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 99636361000 # number of overall MSHR miss cycles 848system.cpu0.dcache.overall_mshr_miss_latency::total 99636361000 # number of overall MSHR miss cycles 849system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2929733500 # number of ReadReq MSHR uncacheable cycles 850system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2929733500 # number of ReadReq MSHR uncacheable cycles 851system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 2929733500 # number of overall MSHR uncacheable cycles 852system.cpu0.dcache.overall_mshr_uncacheable_latency::total 2929733500 # number of overall MSHR uncacheable cycles 853system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.035778 # mshr miss rate for ReadReq accesses 854system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.035778 # mshr miss rate for ReadReq accesses 855system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018325 # mshr miss rate for WriteReq accesses 856system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018325 # mshr miss rate for WriteReq accesses 857system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.754523 # mshr miss rate for SoftPFReq accesses 858system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.754523 # mshr miss rate for SoftPFReq accesses 859system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.760819 # mshr miss rate for WriteLineReq accesses 860system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.760819 # mshr miss rate for WriteLineReq accesses 861system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.058198 # mshr miss rate for LoadLockedReq accesses 862system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.058198 # mshr miss rate for LoadLockedReq accesses 863system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.106447 # mshr miss rate for StoreCondReq accesses 864system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.106447 # mshr miss rate for StoreCondReq accesses 865system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.032374 # mshr miss rate for demand accesses 866system.cpu0.dcache.demand_mshr_miss_rate::total 0.032374 # mshr miss rate for demand accesses 867system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.036216 # mshr miss rate for overall accesses 868system.cpu0.dcache.overall_mshr_miss_rate::total 0.036216 # mshr miss rate for overall accesses 869system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14000.148458 # average ReadReq mshr miss latency 870system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14000.148458 # average ReadReq mshr miss latency 871system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 20640.491368 # average WriteReq mshr miss latency 872system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 20640.491368 # average WriteReq mshr miss latency 873system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 23487.153406 # average SoftPFReq mshr miss latency 874system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 23487.153406 # average SoftPFReq mshr miss latency 875system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 32000.555925 # average WriteLineReq mshr miss latency 876system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 32000.555925 # average WriteLineReq mshr miss latency 877system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13432.834607 # average LoadLockedReq mshr miss latency 878system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13432.834607 # average LoadLockedReq mshr miss latency 879system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22742.595452 # average StoreCondReq mshr miss latency 880system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22742.595452 # average StoreCondReq mshr miss latency 881system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 882system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 883system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 18574.150584 # average overall mshr miss latency 884system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18574.150584 # average overall mshr miss latency 885system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19118.656280 # average overall mshr miss latency 886system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19118.656280 # average overall mshr miss latency 887system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184364.325719 # average ReadReq mshr uncacheable latency 888system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184364.325719 # average ReadReq mshr uncacheable latency 889system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 89618.962406 # average overall mshr uncacheable latency 890system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 89618.962406 # average overall mshr uncacheable latency 891system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 892system.cpu0.icache.tags.replacements 4327935 # number of replacements 893system.cpu0.icache.tags.tagsinuse 511.943806 # Cycle average of tags in use 894system.cpu0.icache.tags.total_refs 380677204 # Total number of references to valid blocks. 895system.cpu0.icache.tags.sampled_refs 4328447 # Sample count of references to valid blocks. 896system.cpu0.icache.tags.avg_refs 87.947757 # Average number of references to valid blocks. 897system.cpu0.icache.tags.warmup_cycle 27073430000 # Cycle when the warmup percentage was hit. 898system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.943806 # Average occupied blocks per requestor 899system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999890 # Average percentage of cache occupancy 900system.cpu0.icache.tags.occ_percent::total 0.999890 # Average percentage of cache occupancy 901system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 902system.cpu0.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 903system.cpu0.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 904system.cpu0.icache.tags.age_task_id_blocks_1024::2 191 # Occupied blocks per task id 905system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id 906system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 907system.cpu0.icache.tags.tag_accesses 774339749 # Number of tag accesses 908system.cpu0.icache.tags.data_accesses 774339749 # Number of data accesses 909system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 910system.cpu0.icache.ReadReq_hits::cpu0.inst 380677204 # number of ReadReq hits 911system.cpu0.icache.ReadReq_hits::total 380677204 # number of ReadReq hits 912system.cpu0.icache.demand_hits::cpu0.inst 380677204 # number of demand (read+write) hits 913system.cpu0.icache.demand_hits::total 380677204 # number of demand (read+write) hits 914system.cpu0.icache.overall_hits::cpu0.inst 380677204 # number of overall hits 915system.cpu0.icache.overall_hits::total 380677204 # number of overall hits 916system.cpu0.icache.ReadReq_misses::cpu0.inst 4328447 # number of ReadReq misses 917system.cpu0.icache.ReadReq_misses::total 4328447 # number of ReadReq misses 918system.cpu0.icache.demand_misses::cpu0.inst 4328447 # number of demand (read+write) misses 919system.cpu0.icache.demand_misses::total 4328447 # number of demand (read+write) misses 920system.cpu0.icache.overall_misses::cpu0.inst 4328447 # number of overall misses 921system.cpu0.icache.overall_misses::total 4328447 # number of overall misses 922system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 47943054500 # number of ReadReq miss cycles 923system.cpu0.icache.ReadReq_miss_latency::total 47943054500 # number of ReadReq miss cycles 924system.cpu0.icache.demand_miss_latency::cpu0.inst 47943054500 # number of demand (read+write) miss cycles 925system.cpu0.icache.demand_miss_latency::total 47943054500 # number of demand (read+write) miss cycles 926system.cpu0.icache.overall_miss_latency::cpu0.inst 47943054500 # number of overall miss cycles 927system.cpu0.icache.overall_miss_latency::total 47943054500 # number of overall miss cycles 928system.cpu0.icache.ReadReq_accesses::cpu0.inst 385005651 # number of ReadReq accesses(hits+misses) 929system.cpu0.icache.ReadReq_accesses::total 385005651 # number of ReadReq accesses(hits+misses) 930system.cpu0.icache.demand_accesses::cpu0.inst 385005651 # number of demand (read+write) accesses 931system.cpu0.icache.demand_accesses::total 385005651 # number of demand (read+write) accesses 932system.cpu0.icache.overall_accesses::cpu0.inst 385005651 # number of overall (read+write) accesses 933system.cpu0.icache.overall_accesses::total 385005651 # number of overall (read+write) accesses 934system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011243 # miss rate for ReadReq accesses 935system.cpu0.icache.ReadReq_miss_rate::total 0.011243 # miss rate for ReadReq accesses 936system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011243 # miss rate for demand accesses 937system.cpu0.icache.demand_miss_rate::total 0.011243 # miss rate for demand accesses 938system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011243 # miss rate for overall accesses 939system.cpu0.icache.overall_miss_rate::total 0.011243 # miss rate for overall accesses 940system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11076.271582 # average ReadReq miss latency 941system.cpu0.icache.ReadReq_avg_miss_latency::total 11076.271582 # average ReadReq miss latency 942system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency 943system.cpu0.icache.demand_avg_miss_latency::total 11076.271582 # average overall miss latency 944system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11076.271582 # average overall miss latency 945system.cpu0.icache.overall_avg_miss_latency::total 11076.271582 # average overall miss latency 946system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 947system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 948system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 949system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 950system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 951system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 952system.cpu0.icache.writebacks::writebacks 4327935 # number of writebacks 953system.cpu0.icache.writebacks::total 4327935 # number of writebacks 954system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4328447 # number of ReadReq MSHR misses 955system.cpu0.icache.ReadReq_mshr_misses::total 4328447 # number of ReadReq MSHR misses 956system.cpu0.icache.demand_mshr_misses::cpu0.inst 4328447 # number of demand (read+write) MSHR misses 957system.cpu0.icache.demand_mshr_misses::total 4328447 # number of demand (read+write) MSHR misses 958system.cpu0.icache.overall_mshr_misses::cpu0.inst 4328447 # number of overall MSHR misses 959system.cpu0.icache.overall_mshr_misses::total 4328447 # number of overall MSHR misses 960system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable 961system.cpu0.icache.ReadReq_mshr_uncacheable::total 4725 # number of ReadReq MSHR uncacheable 962system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses 963system.cpu0.icache.overall_mshr_uncacheable_misses::total 4725 # number of overall MSHR uncacheable misses 964system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 45778831000 # number of ReadReq MSHR miss cycles 965system.cpu0.icache.ReadReq_mshr_miss_latency::total 45778831000 # number of ReadReq MSHR miss cycles 966system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 45778831000 # number of demand (read+write) MSHR miss cycles 967system.cpu0.icache.demand_mshr_miss_latency::total 45778831000 # number of demand (read+write) MSHR miss cycles 968system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 45778831000 # number of overall MSHR miss cycles 969system.cpu0.icache.overall_mshr_miss_latency::total 45778831000 # number of overall MSHR miss cycles 970system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 463686000 # number of ReadReq MSHR uncacheable cycles 971system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 463686000 # number of ReadReq MSHR uncacheable cycles 972system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 463686000 # number of overall MSHR uncacheable cycles 973system.cpu0.icache.overall_mshr_uncacheable_latency::total 463686000 # number of overall MSHR uncacheable cycles 974system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for ReadReq accesses 975system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011243 # mshr miss rate for ReadReq accesses 976system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for demand accesses 977system.cpu0.icache.demand_mshr_miss_rate::total 0.011243 # mshr miss rate for demand accesses 978system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011243 # mshr miss rate for overall accesses 979system.cpu0.icache.overall_mshr_miss_rate::total 0.011243 # mshr miss rate for overall accesses 980system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average ReadReq mshr miss latency 981system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10576.271582 # average ReadReq mshr miss latency 982system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average overall mshr miss latency 983system.cpu0.icache.demand_avg_mshr_miss_latency::total 10576.271582 # average overall mshr miss latency 984system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10576.271582 # average overall mshr miss latency 985system.cpu0.icache.overall_avg_mshr_miss_latency::total 10576.271582 # average overall mshr miss latency 986system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98134.603175 # average ReadReq mshr uncacheable latency 987system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98134.603175 # average ReadReq mshr uncacheable latency 988system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98134.603175 # average overall mshr uncacheable latency 989system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98134.603175 # average overall mshr uncacheable latency 990system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 991system.cpu0.l2cache.prefetcher.num_hwpf_issued 7077148 # number of hwpf issued 992system.cpu0.l2cache.prefetcher.pfIdentified 7077156 # number of prefetch candidates identified 993system.cpu0.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue 994system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 995system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 996system.cpu0.l2cache.prefetcher.pfSpanPage 919708 # number of prefetches not generated due to page crossing 997system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 998system.cpu0.l2cache.tags.replacements 2034832 # number of replacements 999system.cpu0.l2cache.tags.tagsinuse 15580.971228 # Cycle average of tags in use 1000system.cpu0.l2cache.tags.total_refs 7927218 # Total number of references to valid blocks. 1001system.cpu0.l2cache.tags.sampled_refs 2050121 # Sample count of references to valid blocks. 1002system.cpu0.l2cache.tags.avg_refs 3.866707 # Average number of references to valid blocks. 1003system.cpu0.l2cache.tags.warmup_cycle 1712003500 # Cycle when the warmup percentage was hit. 1004system.cpu0.l2cache.tags.occ_blocks::writebacks 15267.042973 # Average occupied blocks per requestor 1005system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 22.154482 # Average occupied blocks per requestor 1006system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 11.284107 # Average occupied blocks per requestor 1007system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 280.489666 # Average occupied blocks per requestor 1008system.cpu0.l2cache.tags.occ_percent::writebacks 0.931826 # Average percentage of cache occupancy 1009system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001352 # Average percentage of cache occupancy 1010system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000689 # Average percentage of cache occupancy 1011system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.017120 # Average percentage of cache occupancy 1012system.cpu0.l2cache.tags.occ_percent::total 0.950987 # Average percentage of cache occupancy 1013system.cpu0.l2cache.tags.occ_task_id_blocks::1022 305 # Occupied blocks per task id 1014system.cpu0.l2cache.tags.occ_task_id_blocks::1023 72 # Occupied blocks per task id 1015system.cpu0.l2cache.tags.occ_task_id_blocks::1024 14912 # Occupied blocks per task id 1016system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 65 # Occupied blocks per task id 1017system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 109 # Occupied blocks per task id 1018system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 131 # Occupied blocks per task id 1019system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 1020system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id 1021system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 29 # Occupied blocks per task id 1022system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id 1023system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id 1024system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 540 # Occupied blocks per task id 1025system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4190 # Occupied blocks per task id 1026system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7117 # Occupied blocks per task id 1027system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2983 # Occupied blocks per task id 1028system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.018616 # Percentage of cache occupancy per task id 1029system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.004395 # Percentage of cache occupancy per task id 1030system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.910156 # Percentage of cache occupancy per task id 1031system.cpu0.l2cache.tags.tag_accesses 322659786 # Number of tag accesses 1032system.cpu0.l2cache.tags.data_accesses 322659786 # Number of data accesses 1033system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1034system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 205975 # number of ReadReq hits 1035system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 128170 # number of ReadReq hits 1036system.cpu0.l2cache.ReadReq_hits::total 334145 # number of ReadReq hits 1037system.cpu0.l2cache.WritebackDirty_hits::writebacks 3330860 # number of WritebackDirty hits 1038system.cpu0.l2cache.WritebackDirty_hits::total 3330860 # number of WritebackDirty hits 1039system.cpu0.l2cache.WritebackClean_hits::writebacks 6009144 # number of WritebackClean hits 1040system.cpu0.l2cache.WritebackClean_hits::total 6009144 # number of WritebackClean hits 1041system.cpu0.l2cache.ReadExReq_hits::cpu0.data 802570 # number of ReadExReq hits 1042system.cpu0.l2cache.ReadExReq_hits::total 802570 # number of ReadExReq hits 1043system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 3917036 # number of ReadCleanReq hits 1044system.cpu0.l2cache.ReadCleanReq_hits::total 3917036 # number of ReadCleanReq hits 1045system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 2528867 # number of ReadSharedReq hits 1046system.cpu0.l2cache.ReadSharedReq_hits::total 2528867 # number of ReadSharedReq hits 1047system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 164054 # number of InvalidateReq hits 1048system.cpu0.l2cache.InvalidateReq_hits::total 164054 # number of InvalidateReq hits 1049system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 205975 # number of demand (read+write) hits 1050system.cpu0.l2cache.demand_hits::cpu0.itb.walker 128170 # number of demand (read+write) hits 1051system.cpu0.l2cache.demand_hits::cpu0.inst 3917036 # number of demand (read+write) hits 1052system.cpu0.l2cache.demand_hits::cpu0.data 3331437 # number of demand (read+write) hits 1053system.cpu0.l2cache.demand_hits::total 7582618 # number of demand (read+write) hits 1054system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 205975 # number of overall hits 1055system.cpu0.l2cache.overall_hits::cpu0.itb.walker 128170 # number of overall hits 1056system.cpu0.l2cache.overall_hits::cpu0.inst 3917036 # number of overall hits 1057system.cpu0.l2cache.overall_hits::cpu0.data 3331437 # number of overall hits 1058system.cpu0.l2cache.overall_hits::total 7582618 # number of overall hits 1059system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 15216 # number of ReadReq misses 1060system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8071 # number of ReadReq misses 1061system.cpu0.l2cache.ReadReq_misses::total 23287 # number of ReadReq misses 1062system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 218667 # number of UpgradeReq misses 1063system.cpu0.l2cache.UpgradeReq_misses::total 218667 # number of UpgradeReq misses 1064system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 191059 # number of SCUpgradeReq misses 1065system.cpu0.l2cache.SCUpgradeReq_misses::total 191059 # number of SCUpgradeReq misses 1066system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 6 # number of SCUpgradeFailReq misses 1067system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 1068system.cpu0.l2cache.ReadExReq_misses::cpu0.data 228793 # number of ReadExReq misses 1069system.cpu0.l2cache.ReadExReq_misses::total 228793 # number of ReadExReq misses 1070system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 411411 # number of ReadCleanReq misses 1071system.cpu0.l2cache.ReadCleanReq_misses::total 411411 # number of ReadCleanReq misses 1072system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 830772 # number of ReadSharedReq misses 1073system.cpu0.l2cache.ReadSharedReq_misses::total 830772 # number of ReadSharedReq misses 1074system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 558166 # number of InvalidateReq misses 1075system.cpu0.l2cache.InvalidateReq_misses::total 558166 # number of InvalidateReq misses 1076system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 15216 # number of demand (read+write) misses 1077system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8071 # number of demand (read+write) misses 1078system.cpu0.l2cache.demand_misses::cpu0.inst 411411 # number of demand (read+write) misses 1079system.cpu0.l2cache.demand_misses::cpu0.data 1059565 # number of demand (read+write) misses 1080system.cpu0.l2cache.demand_misses::total 1494263 # number of demand (read+write) misses 1081system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 15216 # number of overall misses 1082system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8071 # number of overall misses 1083system.cpu0.l2cache.overall_misses::cpu0.inst 411411 # number of overall misses 1084system.cpu0.l2cache.overall_misses::cpu0.data 1059565 # number of overall misses 1085system.cpu0.l2cache.overall_misses::total 1494263 # number of overall misses 1086system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 436278500 # number of ReadReq miss cycles 1087system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 272723500 # number of ReadReq miss cycles 1088system.cpu0.l2cache.ReadReq_miss_latency::total 709002000 # number of ReadReq miss cycles 1089system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 867672000 # number of UpgradeReq miss cycles 1090system.cpu0.l2cache.UpgradeReq_miss_latency::total 867672000 # number of UpgradeReq miss cycles 1091system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 318347000 # number of SCUpgradeReq miss cycles 1092system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 318347000 # number of SCUpgradeReq miss cycles 1093system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2656998 # number of SCUpgradeFailReq miss cycles 1094system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2656998 # number of SCUpgradeFailReq miss cycles 1095system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12612589500 # number of ReadExReq miss cycles 1096system.cpu0.l2cache.ReadExReq_miss_latency::total 12612589500 # number of ReadExReq miss cycles 1097system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 15771055500 # number of ReadCleanReq miss cycles 1098system.cpu0.l2cache.ReadCleanReq_miss_latency::total 15771055500 # number of ReadCleanReq miss cycles 1099system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 30943358500 # number of ReadSharedReq miss cycles 1100system.cpu0.l2cache.ReadSharedReq_miss_latency::total 30943358500 # number of ReadSharedReq miss cycles 1101system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 436278500 # number of demand (read+write) miss cycles 1102system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 272723500 # number of demand (read+write) miss cycles 1103system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15771055500 # number of demand (read+write) miss cycles 1104system.cpu0.l2cache.demand_miss_latency::cpu0.data 43555948000 # number of demand (read+write) miss cycles 1105system.cpu0.l2cache.demand_miss_latency::total 60036005500 # number of demand (read+write) miss cycles 1106system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 436278500 # number of overall miss cycles 1107system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 272723500 # number of overall miss cycles 1108system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15771055500 # number of overall miss cycles 1109system.cpu0.l2cache.overall_miss_latency::cpu0.data 43555948000 # number of overall miss cycles 1110system.cpu0.l2cache.overall_miss_latency::total 60036005500 # number of overall miss cycles 1111system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 221191 # number of ReadReq accesses(hits+misses) 1112system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 136241 # number of ReadReq accesses(hits+misses) 1113system.cpu0.l2cache.ReadReq_accesses::total 357432 # number of ReadReq accesses(hits+misses) 1114system.cpu0.l2cache.WritebackDirty_accesses::writebacks 3330860 # number of WritebackDirty accesses(hits+misses) 1115system.cpu0.l2cache.WritebackDirty_accesses::total 3330860 # number of WritebackDirty accesses(hits+misses) 1116system.cpu0.l2cache.WritebackClean_accesses::writebacks 6009144 # number of WritebackClean accesses(hits+misses) 1117system.cpu0.l2cache.WritebackClean_accesses::total 6009144 # number of WritebackClean accesses(hits+misses) 1118system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 218667 # number of UpgradeReq accesses(hits+misses) 1119system.cpu0.l2cache.UpgradeReq_accesses::total 218667 # number of UpgradeReq accesses(hits+misses) 1120system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 191059 # number of SCUpgradeReq accesses(hits+misses) 1121system.cpu0.l2cache.SCUpgradeReq_accesses::total 191059 # number of SCUpgradeReq accesses(hits+misses) 1122system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 1123system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 1124system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1031363 # number of ReadExReq accesses(hits+misses) 1125system.cpu0.l2cache.ReadExReq_accesses::total 1031363 # number of ReadExReq accesses(hits+misses) 1126system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 4328447 # number of ReadCleanReq accesses(hits+misses) 1127system.cpu0.l2cache.ReadCleanReq_accesses::total 4328447 # number of ReadCleanReq accesses(hits+misses) 1128system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 3359639 # number of ReadSharedReq accesses(hits+misses) 1129system.cpu0.l2cache.ReadSharedReq_accesses::total 3359639 # number of ReadSharedReq accesses(hits+misses) 1130system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 722220 # number of InvalidateReq accesses(hits+misses) 1131system.cpu0.l2cache.InvalidateReq_accesses::total 722220 # number of InvalidateReq accesses(hits+misses) 1132system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 221191 # number of demand (read+write) accesses 1133system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 136241 # number of demand (read+write) accesses 1134system.cpu0.l2cache.demand_accesses::cpu0.inst 4328447 # number of demand (read+write) accesses 1135system.cpu0.l2cache.demand_accesses::cpu0.data 4391002 # number of demand (read+write) accesses 1136system.cpu0.l2cache.demand_accesses::total 9076881 # number of demand (read+write) accesses 1137system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 221191 # number of overall (read+write) accesses 1138system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 136241 # number of overall (read+write) accesses 1139system.cpu0.l2cache.overall_accesses::cpu0.inst 4328447 # number of overall (read+write) accesses 1140system.cpu0.l2cache.overall_accesses::cpu0.data 4391002 # number of overall (read+write) accesses 1141system.cpu0.l2cache.overall_accesses::total 9076881 # number of overall (read+write) accesses 1142system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for ReadReq accesses 1143system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.059241 # miss rate for ReadReq accesses 1144system.cpu0.l2cache.ReadReq_miss_rate::total 0.065151 # miss rate for ReadReq accesses 1145system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses 1146system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1147system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses 1148system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 1149system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1150system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1151system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.221836 # miss rate for ReadExReq accesses 1152system.cpu0.l2cache.ReadExReq_miss_rate::total 0.221836 # miss rate for ReadExReq accesses 1153system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.095048 # miss rate for ReadCleanReq accesses 1154system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.095048 # miss rate for ReadCleanReq accesses 1155system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.247280 # miss rate for ReadSharedReq accesses 1156system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.247280 # miss rate for ReadSharedReq accesses 1157system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.772848 # miss rate for InvalidateReq accesses 1158system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.772848 # miss rate for InvalidateReq accesses 1159system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for demand accesses 1160system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.059241 # miss rate for demand accesses 1161system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.095048 # miss rate for demand accesses 1162system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.241304 # miss rate for demand accesses 1163system.cpu0.l2cache.demand_miss_rate::total 0.164623 # miss rate for demand accesses 1164system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.068791 # miss rate for overall accesses 1165system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.059241 # miss rate for overall accesses 1166system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.095048 # miss rate for overall accesses 1167system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.241304 # miss rate for overall accesses 1168system.cpu0.l2cache.overall_miss_rate::total 0.164623 # miss rate for overall accesses 1169system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average ReadReq miss latency 1170system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 33790.546401 # average ReadReq miss latency 1171system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30446.257569 # average ReadReq miss latency 1172system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3968.006146 # average UpgradeReq miss latency 1173system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3968.006146 # average UpgradeReq miss latency 1174system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1666.223523 # average SCUpgradeReq miss latency 1175system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1666.223523 # average SCUpgradeReq miss latency 1176system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 442833 # average SCUpgradeFailReq miss latency 1177system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 442833 # average SCUpgradeFailReq miss latency 1178system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 55126.640675 # average ReadExReq miss latency 1179system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 55126.640675 # average ReadExReq miss latency 1180system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 38334.063746 # average ReadCleanReq miss latency 1181system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 38334.063746 # average ReadCleanReq miss latency 1182system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 37246.511076 # average ReadSharedReq miss latency 1183system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 37246.511076 # average ReadSharedReq miss latency 1184system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average overall miss latency 1185system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 33790.546401 # average overall miss latency 1186system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 38334.063746 # average overall miss latency 1187system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 41107.386522 # average overall miss latency 1188system.cpu0.l2cache.demand_avg_miss_latency::total 40177.669861 # average overall miss latency 1189system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 28672.351472 # average overall miss latency 1190system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 33790.546401 # average overall miss latency 1191system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 38334.063746 # average overall miss latency 1192system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 41107.386522 # average overall miss latency 1193system.cpu0.l2cache.overall_avg_miss_latency::total 40177.669861 # average overall miss latency 1194system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1195system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1196system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1197system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1198system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1199system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1200system.cpu0.l2cache.unused_prefetches 34479 # number of HardPF blocks evicted w/o reference 1201system.cpu0.l2cache.writebacks::writebacks 1361012 # number of writebacks 1202system.cpu0.l2cache.writebacks::total 1361012 # number of writebacks 1203system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5370 # number of ReadExReq MSHR hits 1204system.cpu0.l2cache.ReadExReq_mshr_hits::total 5370 # number of ReadExReq MSHR hits 1205system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 489 # number of ReadSharedReq MSHR hits 1206system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 489 # number of ReadSharedReq MSHR hits 1207system.cpu0.l2cache.demand_mshr_hits::cpu0.data 5859 # number of demand (read+write) MSHR hits 1208system.cpu0.l2cache.demand_mshr_hits::total 5859 # number of demand (read+write) MSHR hits 1209system.cpu0.l2cache.overall_mshr_hits::cpu0.data 5859 # number of overall MSHR hits 1210system.cpu0.l2cache.overall_mshr_hits::total 5859 # number of overall MSHR hits 1211system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 15216 # number of ReadReq MSHR misses 1212system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8071 # number of ReadReq MSHR misses 1213system.cpu0.l2cache.ReadReq_mshr_misses::total 23287 # number of ReadReq MSHR misses 1214system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 675054 # number of HardPFReq MSHR misses 1215system.cpu0.l2cache.HardPFReq_mshr_misses::total 675054 # number of HardPFReq MSHR misses 1216system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 218667 # number of UpgradeReq MSHR misses 1217system.cpu0.l2cache.UpgradeReq_mshr_misses::total 218667 # number of UpgradeReq MSHR misses 1218system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 191059 # number of SCUpgradeReq MSHR misses 1219system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 191059 # number of SCUpgradeReq MSHR misses 1220system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 6 # number of SCUpgradeFailReq MSHR misses 1221system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 1222system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 223423 # number of ReadExReq MSHR misses 1223system.cpu0.l2cache.ReadExReq_mshr_misses::total 223423 # number of ReadExReq MSHR misses 1224system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 411411 # number of ReadCleanReq MSHR misses 1225system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 411411 # number of ReadCleanReq MSHR misses 1226system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 830283 # number of ReadSharedReq MSHR misses 1227system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 830283 # number of ReadSharedReq MSHR misses 1228system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 558166 # number of InvalidateReq MSHR misses 1229system.cpu0.l2cache.InvalidateReq_mshr_misses::total 558166 # number of InvalidateReq MSHR misses 1230system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 15216 # number of demand (read+write) MSHR misses 1231system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8071 # number of demand (read+write) MSHR misses 1232system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 411411 # number of demand (read+write) MSHR misses 1233system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1053706 # number of demand (read+write) MSHR misses 1234system.cpu0.l2cache.demand_mshr_misses::total 1488404 # number of demand (read+write) MSHR misses 1235system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 15216 # number of overall MSHR misses 1236system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8071 # number of overall MSHR misses 1237system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 411411 # number of overall MSHR misses 1238system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1053706 # number of overall MSHR misses 1239system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 675054 # number of overall MSHR misses 1240system.cpu0.l2cache.overall_mshr_misses::total 2163458 # number of overall MSHR misses 1241system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable 1242system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable 1243system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20616 # number of ReadReq MSHR uncacheable 1244system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable 1245system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16800 # number of WriteReq MSHR uncacheable 1246system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses 1247system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses 1248system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37416 # number of overall MSHR uncacheable misses 1249system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of ReadReq MSHR miss cycles 1250system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 224297500 # number of ReadReq MSHR miss cycles 1251system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 569280000 # number of ReadReq MSHR miss cycles 1252system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32033056811 # number of HardPFReq MSHR miss cycles 1253system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32033056811 # number of HardPFReq MSHR miss cycles 1254system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4084370000 # number of UpgradeReq MSHR miss cycles 1255system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4084370000 # number of UpgradeReq MSHR miss cycles 1256system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2911469499 # number of SCUpgradeReq MSHR miss cycles 1257system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2911469499 # number of SCUpgradeReq MSHR miss cycles 1258system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2248998 # number of SCUpgradeFailReq MSHR miss cycles 1259system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2248998 # number of SCUpgradeFailReq MSHR miss cycles 1260system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 10644364000 # number of ReadExReq MSHR miss cycles 1261system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 10644364000 # number of ReadExReq MSHR miss cycles 1262system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 13302589500 # number of ReadCleanReq MSHR miss cycles 1263system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 13302589500 # number of ReadCleanReq MSHR miss cycles 1264system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 25893671500 # number of ReadSharedReq MSHR miss cycles 1265system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 25893671500 # number of ReadSharedReq MSHR miss cycles 1266system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 17612762500 # number of InvalidateReq MSHR miss cycles 1267system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 17612762500 # number of InvalidateReq MSHR miss cycles 1268system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of demand (read+write) MSHR miss cycles 1269system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 224297500 # number of demand (read+write) MSHR miss cycles 1270system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 13302589500 # number of demand (read+write) MSHR miss cycles 1271system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 36538035500 # number of demand (read+write) MSHR miss cycles 1272system.cpu0.l2cache.demand_mshr_miss_latency::total 50409905000 # number of demand (read+write) MSHR miss cycles 1273system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 344982500 # number of overall MSHR miss cycles 1274system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 224297500 # number of overall MSHR miss cycles 1275system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 13302589500 # number of overall MSHR miss cycles 1276system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 36538035500 # number of overall MSHR miss cycles 1277system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32033056811 # number of overall MSHR miss cycles 1278system.cpu0.l2cache.overall_mshr_miss_latency::total 82442961811 # number of overall MSHR miss cycles 1279system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 428248500 # number of ReadReq MSHR uncacheable cycles 1280system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2802283500 # number of ReadReq MSHR uncacheable cycles 1281system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3230532000 # number of ReadReq MSHR uncacheable cycles 1282system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 428248500 # number of overall MSHR uncacheable cycles 1283system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2802283500 # number of overall MSHR uncacheable cycles 1284system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 3230532000 # number of overall MSHR uncacheable cycles 1285system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for ReadReq accesses 1286system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for ReadReq accesses 1287system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.065151 # mshr miss rate for ReadReq accesses 1288system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1289system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1290system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses 1291system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1292system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses 1293system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 1294system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1295system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1296system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216629 # mshr miss rate for ReadExReq accesses 1297system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216629 # mshr miss rate for ReadExReq accesses 1298system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for ReadCleanReq accesses 1299system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.095048 # mshr miss rate for ReadCleanReq accesses 1300system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.247135 # mshr miss rate for ReadSharedReq accesses 1301system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.247135 # mshr miss rate for ReadSharedReq accesses 1302system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.772848 # mshr miss rate for InvalidateReq accesses 1303system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.772848 # mshr miss rate for InvalidateReq accesses 1304system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for demand accesses 1305system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for demand accesses 1306system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for demand accesses 1307system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for demand accesses 1308system.cpu0.l2cache.demand_mshr_miss_rate::total 0.163977 # mshr miss rate for demand accesses 1309system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.068791 # mshr miss rate for overall accesses 1310system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.059241 # mshr miss rate for overall accesses 1311system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.095048 # mshr miss rate for overall accesses 1312system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.239969 # mshr miss rate for overall accesses 1313system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1314system.cpu0.l2cache.overall_mshr_miss_rate::total 0.238348 # mshr miss rate for overall accesses 1315system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average ReadReq mshr miss latency 1316system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average ReadReq mshr miss latency 1317system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24446.257569 # average ReadReq mshr miss latency 1318system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average HardPFReq mshr miss latency 1319system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 47452.584254 # average HardPFReq mshr miss latency 1320system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18678.492868 # average UpgradeReq mshr miss latency 1321system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18678.492868 # average UpgradeReq mshr miss latency 1322system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15238.588598 # average SCUpgradeReq mshr miss latency 1323system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15238.588598 # average SCUpgradeReq mshr miss latency 1324system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 374833 # average SCUpgradeFailReq mshr miss latency 1325system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 374833 # average SCUpgradeFailReq mshr miss latency 1326system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 47642.203354 # average ReadExReq mshr miss latency 1327system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 47642.203354 # average ReadExReq mshr miss latency 1328system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average ReadCleanReq mshr miss latency 1329system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32334.063746 # average ReadCleanReq mshr miss latency 1330system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 31186.561088 # average ReadSharedReq mshr miss latency 1331system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31186.561088 # average ReadSharedReq mshr miss latency 1332system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 31554.703260 # average InvalidateReq mshr miss latency 1333system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 31554.703260 # average InvalidateReq mshr miss latency 1334system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency 1335system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency 1336system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency 1337system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency 1338system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 33868.428867 # average overall mshr miss latency 1339system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22672.351472 # average overall mshr miss latency 1340system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 27790.546401 # average overall mshr miss latency 1341system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 32334.063746 # average overall mshr miss latency 1342system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 34675.740197 # average overall mshr miss latency 1343system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 47452.584254 # average overall mshr miss latency 1344system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38107.031341 # average overall mshr miss latency 1345system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average ReadReq mshr uncacheable latency 1346system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176344.062677 # average ReadReq mshr uncacheable latency 1347system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 156700.232829 # average ReadReq mshr uncacheable latency 1348system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90634.603175 # average overall mshr uncacheable latency 1349system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 85720.335872 # average overall mshr uncacheable latency 1350system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 86340.923669 # average overall mshr uncacheable latency 1351system.cpu0.toL2Bus.snoop_filter.tot_requests 19414965 # Total number of requests made to the snoop filter. 1352system.cpu0.toL2Bus.snoop_filter.hit_single_requests 9975279 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1353system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 976 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1354system.cpu0.toL2Bus.snoop_filter.tot_snoops 578988 # Total number of snoops made to the snoop filter. 1355system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 578988 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1356system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1357system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1358system.cpu0.toL2Bus.trans_dist::ReadReq 442233 # Transaction distribution 1359system.cpu0.toL2Bus.trans_dist::ReadResp 8226522 # Transaction distribution 1360system.cpu0.toL2Bus.trans_dist::WriteReq 16801 # Transaction distribution 1361system.cpu0.toL2Bus.trans_dist::WriteResp 16800 # Transaction distribution 1362system.cpu0.toL2Bus.trans_dist::WritebackDirty 4707887 # Transaction distribution 1363system.cpu0.toL2Bus.trans_dist::WritebackClean 6010120 # Transaction distribution 1364system.cpu0.toL2Bus.trans_dist::CleanEvict 978928 # Transaction distribution 1365system.cpu0.toL2Bus.trans_dist::HardPFReq 831060 # Transaction distribution 1366system.cpu0.toL2Bus.trans_dist::UpgradeReq 419258 # Transaction distribution 1367system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 359151 # Transaction distribution 1368system.cpu0.toL2Bus.trans_dist::UpgradeResp 478987 # Transaction distribution 1369system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution 1370system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution 1371system.cpu0.toL2Bus.trans_dist::ReadExReq 1069161 # Transaction distribution 1372system.cpu0.toL2Bus.trans_dist::ReadExResp 1041370 # Transaction distribution 1373system.cpu0.toL2Bus.trans_dist::ReadCleanReq 4328447 # Transaction distribution 1374system.cpu0.toL2Bus.trans_dist::ReadSharedReq 4301809 # Transaction distribution 1375system.cpu0.toL2Bus.trans_dist::InvalidateReq 793195 # Transaction distribution 1376system.cpu0.toL2Bus.trans_dist::InvalidateResp 723551 # Transaction distribution 1377system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 12994279 # Packet count per connected master and slave (bytes) 1378system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 16301256 # Packet count per connected master and slave (bytes) 1379system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 289006 # Packet count per connected master and slave (bytes) 1380system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 490041 # Packet count per connected master and slave (bytes) 1381system.cpu0.toL2Bus.pkt_count::total 30074582 # Packet count per connected master and slave (bytes) 1382system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 554027348 # Cumulative packet size per connected master and slave (bytes) 1383system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 608753046 # Cumulative packet size per connected master and slave (bytes) 1384system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1089928 # Cumulative packet size per connected master and slave (bytes) 1385system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1769528 # Cumulative packet size per connected master and slave (bytes) 1386system.cpu0.toL2Bus.pkt_size::total 1165639850 # Cumulative packet size per connected master and slave (bytes) 1387system.cpu0.toL2Bus.snoops 4847803 # Total snoops (count) 1388system.cpu0.toL2Bus.snoopTraffic 95443532 # Total snoop traffic (bytes) 1389system.cpu0.toL2Bus.snoop_fanout::samples 14917131 # Request fanout histogram 1390system.cpu0.toL2Bus.snoop_fanout::mean 0.053800 # Request fanout histogram 1391system.cpu0.toL2Bus.snoop_fanout::stdev 0.225623 # Request fanout histogram 1392system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1393system.cpu0.toL2Bus.snoop_fanout::0 14114583 94.62% 94.62% # Request fanout histogram 1394system.cpu0.toL2Bus.snoop_fanout::1 802548 5.38% 100.00% # Request fanout histogram 1395system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1396system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1397system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1398system.cpu0.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1399system.cpu0.toL2Bus.snoop_fanout::total 14917131 # Request fanout histogram 1400system.cpu0.toL2Bus.reqLayer0.occupancy 19175088002 # Layer occupancy (ticks) 1401system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1402system.cpu0.toL2Bus.snoopLayer0.occupancy 194853286 # Layer occupancy (ticks) 1403system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1404system.cpu0.toL2Bus.respLayer0.occupancy 6497395500 # Layer occupancy (ticks) 1405system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1406system.cpu0.toL2Bus.respLayer1.occupancy 7177011173 # Layer occupancy (ticks) 1407system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1408system.cpu0.toL2Bus.respLayer2.occupancy 152765499 # Layer occupancy (ticks) 1409system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1410system.cpu0.toL2Bus.respLayer3.occupancy 268850499 # Layer occupancy (ticks) 1411system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1412system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1413system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1414system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1415system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1416system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1417system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1418system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1419system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1420system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1421system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1422system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1423system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1424system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1425system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1426system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1427system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1428system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1429system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1430system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1431system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1432system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1433system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1434system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1435system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1436system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1437system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1438system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1439system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1440system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1441system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1442system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1443system.cpu1.dtb.walker.walks 108097 # Table walker walks requested 1444system.cpu1.dtb.walker.walksLong 108097 # Table walker walks initiated with long descriptors 1445system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 9121 # Level at which table walker walks with long descriptors terminate 1446system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 84193 # Level at which table walker walks with long descriptors terminate 1447system.cpu1.dtb.walker.walksSquashedBefore 17 # Table walks squashed before starting 1448system.cpu1.dtb.walker.walkWaitTime::samples 108080 # Table walker wait (enqueue to first request) latency 1449system.cpu1.dtb.walker.walkWaitTime::mean 0.074019 # Table walker wait (enqueue to first request) latency 1450system.cpu1.dtb.walker.walkWaitTime::stdev 24.334214 # Table walker wait (enqueue to first request) latency 1451system.cpu1.dtb.walker.walkWaitTime::0-511 108079 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1452system.cpu1.dtb.walker.walkWaitTime::7680-8191 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1453system.cpu1.dtb.walker.walkWaitTime::total 108080 # Table walker wait (enqueue to first request) latency 1454system.cpu1.dtb.walker.walkCompletionTime::samples 93331 # Table walker service (enqueue to completion) latency 1455system.cpu1.dtb.walker.walkCompletionTime::mean 24327.977842 # Table walker service (enqueue to completion) latency 1456system.cpu1.dtb.walker.walkCompletionTime::gmean 22238.306429 # Table walker service (enqueue to completion) latency 1457system.cpu1.dtb.walker.walkCompletionTime::stdev 18706.694176 # Table walker service (enqueue to completion) latency 1458system.cpu1.dtb.walker.walkCompletionTime::0-65535 92079 98.66% 98.66% # Table walker service (enqueue to completion) latency 1459system.cpu1.dtb.walker.walkCompletionTime::65536-131071 920 0.99% 99.64% # Table walker service (enqueue to completion) latency 1460system.cpu1.dtb.walker.walkCompletionTime::131072-196607 176 0.19% 99.83% # Table walker service (enqueue to completion) latency 1461system.cpu1.dtb.walker.walkCompletionTime::196608-262143 54 0.06% 99.89% # Table walker service (enqueue to completion) latency 1462system.cpu1.dtb.walker.walkCompletionTime::262144-327679 42 0.05% 99.94% # Table walker service (enqueue to completion) latency 1463system.cpu1.dtb.walker.walkCompletionTime::327680-393215 24 0.03% 99.96% # Table walker service (enqueue to completion) latency 1464system.cpu1.dtb.walker.walkCompletionTime::393216-458751 10 0.01% 99.97% # Table walker service (enqueue to completion) latency 1465system.cpu1.dtb.walker.walkCompletionTime::458752-524287 4 0.00% 99.98% # Table walker service (enqueue to completion) latency 1466system.cpu1.dtb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 1467system.cpu1.dtb.walker.walkCompletionTime::589824-655359 17 0.02% 100.00% # Table walker service (enqueue to completion) latency 1468system.cpu1.dtb.walker.walkCompletionTime::655360-720895 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1469system.cpu1.dtb.walker.walkCompletionTime::total 93331 # Table walker service (enqueue to completion) latency 1470system.cpu1.dtb.walker.walksPending::samples 5379088140 # Table walker pending requests distribution 1471system.cpu1.dtb.walker.walksPending::mean 0.979144 # Table walker pending requests distribution 1472system.cpu1.dtb.walker.walksPending::stdev 0.142902 # Table walker pending requests distribution 1473system.cpu1.dtb.walker.walksPending::0 112185648 2.09% 2.09% # Table walker pending requests distribution 1474system.cpu1.dtb.walker.walksPending::1 5266902492 97.91% 100.00% # Table walker pending requests distribution 1475system.cpu1.dtb.walker.walksPending::total 5379088140 # Table walker pending requests distribution 1476system.cpu1.dtb.walker.walkPageSizes::4K 84194 90.23% 90.23% # Table walker page sizes translated 1477system.cpu1.dtb.walker.walkPageSizes::2M 9121 9.77% 100.00% # Table walker page sizes translated 1478system.cpu1.dtb.walker.walkPageSizes::total 93315 # Table walker page sizes translated 1479system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 108097 # Table walker requests started/completed, data/inst 1480system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1481system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 108097 # Table walker requests started/completed, data/inst 1482system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 93315 # Table walker requests started/completed, data/inst 1483system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1484system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 93315 # Table walker requests started/completed, data/inst 1485system.cpu1.dtb.walker.walkRequestOrigin::total 201412 # Table walker requests started/completed, data/inst 1486system.cpu1.dtb.inst_hits 0 # ITB inst hits 1487system.cpu1.dtb.inst_misses 0 # ITB inst misses 1488system.cpu1.dtb.read_hits 86913541 # DTB read hits 1489system.cpu1.dtb.read_misses 78813 # DTB read misses 1490system.cpu1.dtb.write_hits 79382446 # DTB write hits 1491system.cpu1.dtb.write_misses 29284 # DTB write misses 1492system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1493system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1494system.cpu1.dtb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID 1495system.cpu1.dtb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID 1496system.cpu1.dtb.flush_entries 38404 # Number of entries that have been flushed from TLB 1497system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1498system.cpu1.dtb.prefetch_faults 4493 # Number of TLB faults due to prefetch 1499system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1500system.cpu1.dtb.perms_faults 10593 # Number of TLB faults due to permissions restrictions 1501system.cpu1.dtb.read_accesses 86992354 # DTB read accesses 1502system.cpu1.dtb.write_accesses 79411730 # DTB write accesses 1503system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1504system.cpu1.dtb.hits 166295987 # DTB hits 1505system.cpu1.dtb.misses 108097 # DTB misses 1506system.cpu1.dtb.accesses 166404084 # DTB accesses 1507system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1508system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1509system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1510system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1511system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1512system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1513system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1514system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1515system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1516system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1517system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1518system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1519system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1520system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1521system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1522system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1523system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1524system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1525system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1526system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1527system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1528system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1529system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1530system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1531system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1532system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1533system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1534system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1535system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1536system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1537system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1538system.cpu1.itb.walker.walks 67294 # Table walker walks requested 1539system.cpu1.itb.walker.walksLong 67294 # Table walker walks initiated with long descriptors 1540system.cpu1.itb.walker.walksLongTerminationLevel::Level2 626 # Level at which table walker walks with long descriptors terminate 1541system.cpu1.itb.walker.walksLongTerminationLevel::Level3 61475 # Level at which table walker walks with long descriptors terminate 1542system.cpu1.itb.walker.walkWaitTime::samples 67294 # Table walker wait (enqueue to first request) latency 1543system.cpu1.itb.walker.walkWaitTime::0 67294 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1544system.cpu1.itb.walker.walkWaitTime::total 67294 # Table walker wait (enqueue to first request) latency 1545system.cpu1.itb.walker.walkCompletionTime::samples 62101 # Table walker service (enqueue to completion) latency 1546system.cpu1.itb.walker.walkCompletionTime::mean 26137.727251 # Table walker service (enqueue to completion) latency 1547system.cpu1.itb.walker.walkCompletionTime::gmean 23789.803797 # Table walker service (enqueue to completion) latency 1548system.cpu1.itb.walker.walkCompletionTime::stdev 22700.198457 # Table walker service (enqueue to completion) latency 1549system.cpu1.itb.walker.walkCompletionTime::0-65535 60815 97.93% 97.93% # Table walker service (enqueue to completion) latency 1550system.cpu1.itb.walker.walkCompletionTime::65536-131071 864 1.39% 99.32% # Table walker service (enqueue to completion) latency 1551system.cpu1.itb.walker.walkCompletionTime::131072-196607 247 0.40% 99.72% # Table walker service (enqueue to completion) latency 1552system.cpu1.itb.walker.walkCompletionTime::196608-262143 72 0.12% 99.83% # Table walker service (enqueue to completion) latency 1553system.cpu1.itb.walker.walkCompletionTime::262144-327679 48 0.08% 99.91% # Table walker service (enqueue to completion) latency 1554system.cpu1.itb.walker.walkCompletionTime::327680-393215 18 0.03% 99.94% # Table walker service (enqueue to completion) latency 1555system.cpu1.itb.walker.walkCompletionTime::393216-458751 9 0.01% 99.95% # Table walker service (enqueue to completion) latency 1556system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.96% # Table walker service (enqueue to completion) latency 1557system.cpu1.itb.walker.walkCompletionTime::589824-655359 23 0.04% 100.00% # Table walker service (enqueue to completion) latency 1558system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1559system.cpu1.itb.walker.walkCompletionTime::total 62101 # Table walker service (enqueue to completion) latency 1560system.cpu1.itb.walker.walksPending::samples -17274852 # Table walker pending requests distribution 1561system.cpu1.itb.walker.walksPending::0 -17274852 100.00% 100.00% # Table walker pending requests distribution 1562system.cpu1.itb.walker.walksPending::total -17274852 # Table walker pending requests distribution 1563system.cpu1.itb.walker.walkPageSizes::4K 61475 98.99% 98.99% # Table walker page sizes translated 1564system.cpu1.itb.walker.walkPageSizes::2M 626 1.01% 100.00% # Table walker page sizes translated 1565system.cpu1.itb.walker.walkPageSizes::total 62101 # Table walker page sizes translated 1566system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1567system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 67294 # Table walker requests started/completed, data/inst 1568system.cpu1.itb.walker.walkRequestOrigin_Requested::total 67294 # Table walker requests started/completed, data/inst 1569system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1570system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 62101 # Table walker requests started/completed, data/inst 1571system.cpu1.itb.walker.walkRequestOrigin_Completed::total 62101 # Table walker requests started/completed, data/inst 1572system.cpu1.itb.walker.walkRequestOrigin::total 129395 # Table walker requests started/completed, data/inst 1573system.cpu1.itb.inst_hits 422829218 # ITB inst hits 1574system.cpu1.itb.inst_misses 67294 # ITB inst misses 1575system.cpu1.itb.read_hits 0 # DTB read hits 1576system.cpu1.itb.read_misses 0 # DTB read misses 1577system.cpu1.itb.write_hits 0 # DTB write hits 1578system.cpu1.itb.write_misses 0 # DTB write misses 1579system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1580system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1581system.cpu1.itb.flush_tlb_mva_asid 40011 # Number of times TLB was flushed by MVA & ASID 1582system.cpu1.itb.flush_tlb_asid 1026 # Number of times TLB was flushed by ASID 1583system.cpu1.itb.flush_entries 27014 # Number of entries that have been flushed from TLB 1584system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1585system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1586system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1587system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1588system.cpu1.itb.read_accesses 0 # DTB read accesses 1589system.cpu1.itb.write_accesses 0 # DTB write accesses 1590system.cpu1.itb.inst_accesses 422896512 # ITB inst accesses 1591system.cpu1.itb.hits 422829218 # DTB hits 1592system.cpu1.itb.misses 67294 # DTB misses 1593system.cpu1.itb.accesses 422896512 # DTB accesses 1594system.cpu1.numPwrStateTransitions 29136 # Number of power state transitions 1595system.cpu1.pwrStateClkGateDist::samples 14568 # Distribution of time spent in the clock gated state 1596system.cpu1.pwrStateClkGateDist::mean 3216976278.654242 # Distribution of time spent in the clock gated state 1597system.cpu1.pwrStateClkGateDist::stdev 84611127659.505341 # Distribution of time spent in the clock gated state 1598system.cpu1.pwrStateClkGateDist::underflows 4387 30.11% 30.11% # Distribution of time spent in the clock gated state 1599system.cpu1.pwrStateClkGateDist::1000-5e+10 10152 69.69% 99.80% # Distribution of time spent in the clock gated state 1600system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.03% 99.84% # Distribution of time spent in the clock gated state 1601system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.01% 99.84% # Distribution of time spent in the clock gated state 1602system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state 1603system.cpu1.pwrStateClkGateDist::4e+11-4.5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state 1604system.cpu1.pwrStateClkGateDist::6e+11-6.5e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 1605system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 1606system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 1607system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 1608system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state 1609system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1610system.cpu1.pwrStateClkGateDist::max_value 7390879628476 # Distribution of time spent in the clock gated state 1611system.cpu1.pwrStateClkGateDist::total 14568 # Distribution of time spent in the clock gated state 1612system.cpu1.pwrStateResidencyTicks::ON 536460160065 # Cumulative time (in ticks) in various power states 1613system.cpu1.pwrStateResidencyTicks::CLK_GATED 46864910427435 # Cumulative time (in ticks) in various power states 1614system.cpu1.numCycles 94802741175 # number of cpu cycles simulated 1615system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1616system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1617system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1618system.cpu1.kern.inst.quiesce 14568 # number of quiesce instructions executed 1619system.cpu1.committedInsts 422521065 # Number of instructions committed 1620system.cpu1.committedOps 504842112 # Number of ops (including micro ops) committed 1621system.cpu1.num_int_alu_accesses 470472983 # Number of integer alu accesses 1622system.cpu1.num_fp_alu_accesses 594254 # Number of float alu accesses 1623system.cpu1.num_func_calls 27792823 # number of times a function call or return occured 1624system.cpu1.num_conditional_control_insts 60626161 # number of instructions that are conditional controls 1625system.cpu1.num_int_insts 470472983 # number of integer instructions 1626system.cpu1.num_fp_insts 594254 # number of float instructions 1627system.cpu1.num_int_register_reads 624330931 # number of times the integer registers were read 1628system.cpu1.num_int_register_writes 367229936 # number of times the integer registers were written 1629system.cpu1.num_fp_register_reads 937660 # number of times the floating registers were read 1630system.cpu1.num_fp_register_writes 547764 # number of times the floating registers were written 1631system.cpu1.num_cc_register_reads 91358730 # number of times the CC registers were read 1632system.cpu1.num_cc_register_writes 91073731 # number of times the CC registers were written 1633system.cpu1.num_mem_refs 166284311 # number of memory refs 1634system.cpu1.num_load_insts 86908703 # Number of load instructions 1635system.cpu1.num_store_insts 79375608 # Number of store instructions 1636system.cpu1.num_idle_cycles 93729820854.868027 # Number of idle cycles 1637system.cpu1.num_busy_cycles 1072920320.131977 # Number of busy cycles 1638system.cpu1.not_idle_fraction 0.011317 # Percentage of non-idle cycles 1639system.cpu1.idle_fraction 0.988683 # Percentage of idle cycles 1640system.cpu1.Branches 93458434 # Number of branches fetched 1641system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 1642system.cpu1.op_class::IntAlu 337624684 66.84% 66.84% # Class of executed instruction 1643system.cpu1.op_class::IntMult 1094737 0.22% 67.05% # Class of executed instruction 1644system.cpu1.op_class::IntDiv 62780 0.01% 67.07% # Class of executed instruction 1645system.cpu1.op_class::FloatAdd 8 0.00% 67.07% # Class of executed instruction 1646system.cpu1.op_class::FloatCmp 13 0.00% 67.07% # Class of executed instruction 1647system.cpu1.op_class::FloatCvt 21 0.00% 67.07% # Class of executed instruction 1648system.cpu1.op_class::FloatMult 0 0.00% 67.07% # Class of executed instruction 1649system.cpu1.op_class::FloatMultAcc 0 0.00% 67.07% # Class of executed instruction 1650system.cpu1.op_class::FloatDiv 0 0.00% 67.07% # Class of executed instruction 1651system.cpu1.op_class::FloatMisc 83819 0.02% 67.08% # Class of executed instruction 1652system.cpu1.op_class::FloatSqrt 0 0.00% 67.08% # Class of executed instruction 1653system.cpu1.op_class::SimdAdd 0 0.00% 67.08% # Class of executed instruction 1654system.cpu1.op_class::SimdAddAcc 0 0.00% 67.08% # Class of executed instruction 1655system.cpu1.op_class::SimdAlu 0 0.00% 67.08% # Class of executed instruction 1656system.cpu1.op_class::SimdCmp 0 0.00% 67.08% # Class of executed instruction 1657system.cpu1.op_class::SimdCvt 0 0.00% 67.08% # Class of executed instruction 1658system.cpu1.op_class::SimdMisc 0 0.00% 67.08% # Class of executed instruction 1659system.cpu1.op_class::SimdMult 0 0.00% 67.08% # Class of executed instruction 1660system.cpu1.op_class::SimdMultAcc 0 0.00% 67.08% # Class of executed instruction 1661system.cpu1.op_class::SimdShift 0 0.00% 67.08% # Class of executed instruction 1662system.cpu1.op_class::SimdShiftAcc 0 0.00% 67.08% # Class of executed instruction 1663system.cpu1.op_class::SimdSqrt 0 0.00% 67.08% # Class of executed instruction 1664system.cpu1.op_class::SimdFloatAdd 0 0.00% 67.08% # Class of executed instruction 1665system.cpu1.op_class::SimdFloatAlu 0 0.00% 67.08% # Class of executed instruction 1666system.cpu1.op_class::SimdFloatCmp 0 0.00% 67.08% # Class of executed instruction 1667system.cpu1.op_class::SimdFloatCvt 0 0.00% 67.08% # Class of executed instruction 1668system.cpu1.op_class::SimdFloatDiv 0 0.00% 67.08% # Class of executed instruction 1669system.cpu1.op_class::SimdFloatMisc 0 0.00% 67.08% # Class of executed instruction 1670system.cpu1.op_class::SimdFloatMult 0 0.00% 67.08% # Class of executed instruction 1671system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.08% # Class of executed instruction 1672system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.08% # Class of executed instruction 1673system.cpu1.op_class::MemRead 86829386 17.19% 84.27% # Class of executed instruction 1674system.cpu1.op_class::MemWrite 78944532 15.63% 99.90% # Class of executed instruction 1675system.cpu1.op_class::FloatMemRead 79317 0.02% 99.91% # Class of executed instruction 1676system.cpu1.op_class::FloatMemWrite 431076 0.09% 100.00% # Class of executed instruction 1677system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1678system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1679system.cpu1.op_class::total 505150374 # Class of executed instruction 1680system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1681system.cpu1.dcache.tags.replacements 5478037 # number of replacements 1682system.cpu1.dcache.tags.tagsinuse 455.042894 # Cycle average of tags in use 1683system.cpu1.dcache.tags.total_refs 160612984 # Total number of references to valid blocks. 1684system.cpu1.dcache.tags.sampled_refs 5478549 # Sample count of references to valid blocks. 1685system.cpu1.dcache.tags.avg_refs 29.316701 # Average number of references to valid blocks. 1686system.cpu1.dcache.tags.warmup_cycle 8375929793000 # Cycle when the warmup percentage was hit. 1687system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.042894 # Average occupied blocks per requestor 1688system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888756 # Average percentage of cache occupancy 1689system.cpu1.dcache.tags.occ_percent::total 0.888756 # Average percentage of cache occupancy 1690system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1691system.cpu1.dcache.tags.age_task_id_blocks_1024::0 65 # Occupied blocks per task id 1692system.cpu1.dcache.tags.age_task_id_blocks_1024::1 420 # Occupied blocks per task id 1693system.cpu1.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id 1694system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1695system.cpu1.dcache.tags.tag_accesses 338044480 # Number of tag accesses 1696system.cpu1.dcache.tags.data_accesses 338044480 # Number of data accesses 1697system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1698system.cpu1.dcache.ReadReq_hits::cpu1.data 80989814 # number of ReadReq hits 1699system.cpu1.dcache.ReadReq_hits::total 80989814 # number of ReadReq hits 1700system.cpu1.dcache.WriteReq_hits::cpu1.data 75375313 # number of WriteReq hits 1701system.cpu1.dcache.WriteReq_hits::total 75375313 # number of WriteReq hits 1702system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188638 # number of SoftPFReq hits 1703system.cpu1.dcache.SoftPFReq_hits::total 188638 # number of SoftPFReq hits 1704system.cpu1.dcache.WriteLineReq_hits::cpu1.data 105231 # number of WriteLineReq hits 1705system.cpu1.dcache.WriteLineReq_hits::total 105231 # number of WriteLineReq hits 1706system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1782566 # number of LoadLockedReq hits 1707system.cpu1.dcache.LoadLockedReq_hits::total 1782566 # number of LoadLockedReq hits 1708system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1758380 # number of StoreCondReq hits 1709system.cpu1.dcache.StoreCondReq_hits::total 1758380 # number of StoreCondReq hits 1710system.cpu1.dcache.demand_hits::cpu1.data 156470358 # number of demand (read+write) hits 1711system.cpu1.dcache.demand_hits::total 156470358 # number of demand (read+write) hits 1712system.cpu1.dcache.overall_hits::cpu1.data 156658996 # number of overall hits 1713system.cpu1.dcache.overall_hits::total 156658996 # number of overall hits 1714system.cpu1.dcache.ReadReq_misses::cpu1.data 3115552 # number of ReadReq misses 1715system.cpu1.dcache.ReadReq_misses::total 3115552 # number of ReadReq misses 1716system.cpu1.dcache.WriteReq_misses::cpu1.data 1383415 # number of WriteReq misses 1717system.cpu1.dcache.WriteReq_misses::total 1383415 # number of WriteReq misses 1718system.cpu1.dcache.SoftPFReq_misses::cpu1.data 634948 # number of SoftPFReq misses 1719system.cpu1.dcache.SoftPFReq_misses::total 634948 # number of SoftPFReq misses 1720system.cpu1.dcache.WriteLineReq_misses::cpu1.data 525445 # number of WriteLineReq misses 1721system.cpu1.dcache.WriteLineReq_misses::total 525445 # number of WriteLineReq misses 1722system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 179669 # number of LoadLockedReq misses 1723system.cpu1.dcache.LoadLockedReq_misses::total 179669 # number of LoadLockedReq misses 1724system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202611 # number of StoreCondReq misses 1725system.cpu1.dcache.StoreCondReq_misses::total 202611 # number of StoreCondReq misses 1726system.cpu1.dcache.demand_misses::cpu1.data 5024412 # number of demand (read+write) misses 1727system.cpu1.dcache.demand_misses::total 5024412 # number of demand (read+write) misses 1728system.cpu1.dcache.overall_misses::cpu1.data 5659360 # number of overall misses 1729system.cpu1.dcache.overall_misses::total 5659360 # number of overall misses 1730system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 46416085500 # number of ReadReq miss cycles 1731system.cpu1.dcache.ReadReq_miss_latency::total 46416085500 # number of ReadReq miss cycles 1732system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 26188875500 # number of WriteReq miss cycles 1733system.cpu1.dcache.WriteReq_miss_latency::total 26188875500 # number of WriteReq miss cycles 1734system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 10762345500 # number of WriteLineReq miss cycles 1735system.cpu1.dcache.WriteLineReq_miss_latency::total 10762345500 # number of WriteLineReq miss cycles 1736system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2779147000 # number of LoadLockedReq miss cycles 1737system.cpu1.dcache.LoadLockedReq_miss_latency::total 2779147000 # number of LoadLockedReq miss cycles 1738system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4838630000 # number of StoreCondReq miss cycles 1739system.cpu1.dcache.StoreCondReq_miss_latency::total 4838630000 # number of StoreCondReq miss cycles 1740system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2246000 # number of StoreCondFailReq miss cycles 1741system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2246000 # number of StoreCondFailReq miss cycles 1742system.cpu1.dcache.demand_miss_latency::cpu1.data 83367306500 # number of demand (read+write) miss cycles 1743system.cpu1.dcache.demand_miss_latency::total 83367306500 # number of demand (read+write) miss cycles 1744system.cpu1.dcache.overall_miss_latency::cpu1.data 83367306500 # number of overall miss cycles 1745system.cpu1.dcache.overall_miss_latency::total 83367306500 # number of overall miss cycles 1746system.cpu1.dcache.ReadReq_accesses::cpu1.data 84105366 # number of ReadReq accesses(hits+misses) 1747system.cpu1.dcache.ReadReq_accesses::total 84105366 # number of ReadReq accesses(hits+misses) 1748system.cpu1.dcache.WriteReq_accesses::cpu1.data 76758728 # number of WriteReq accesses(hits+misses) 1749system.cpu1.dcache.WriteReq_accesses::total 76758728 # number of WriteReq accesses(hits+misses) 1750system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 823586 # number of SoftPFReq accesses(hits+misses) 1751system.cpu1.dcache.SoftPFReq_accesses::total 823586 # number of SoftPFReq accesses(hits+misses) 1752system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 630676 # number of WriteLineReq accesses(hits+misses) 1753system.cpu1.dcache.WriteLineReq_accesses::total 630676 # number of WriteLineReq accesses(hits+misses) 1754system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1962235 # number of LoadLockedReq accesses(hits+misses) 1755system.cpu1.dcache.LoadLockedReq_accesses::total 1962235 # number of LoadLockedReq accesses(hits+misses) 1756system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1960991 # number of StoreCondReq accesses(hits+misses) 1757system.cpu1.dcache.StoreCondReq_accesses::total 1960991 # number of StoreCondReq accesses(hits+misses) 1758system.cpu1.dcache.demand_accesses::cpu1.data 161494770 # number of demand (read+write) accesses 1759system.cpu1.dcache.demand_accesses::total 161494770 # number of demand (read+write) accesses 1760system.cpu1.dcache.overall_accesses::cpu1.data 162318356 # number of overall (read+write) accesses 1761system.cpu1.dcache.overall_accesses::total 162318356 # number of overall (read+write) accesses 1762system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037043 # miss rate for ReadReq accesses 1763system.cpu1.dcache.ReadReq_miss_rate::total 0.037043 # miss rate for ReadReq accesses 1764system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018023 # miss rate for WriteReq accesses 1765system.cpu1.dcache.WriteReq_miss_rate::total 0.018023 # miss rate for WriteReq accesses 1766system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.770955 # miss rate for SoftPFReq accesses 1767system.cpu1.dcache.SoftPFReq_miss_rate::total 0.770955 # miss rate for SoftPFReq accesses 1768system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.833146 # miss rate for WriteLineReq accesses 1769system.cpu1.dcache.WriteLineReq_miss_rate::total 0.833146 # miss rate for WriteLineReq accesses 1770system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091563 # miss rate for LoadLockedReq accesses 1771system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091563 # miss rate for LoadLockedReq accesses 1772system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103321 # miss rate for StoreCondReq accesses 1773system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103321 # miss rate for StoreCondReq accesses 1774system.cpu1.dcache.demand_miss_rate::cpu1.data 0.031112 # miss rate for demand accesses 1775system.cpu1.dcache.demand_miss_rate::total 0.031112 # miss rate for demand accesses 1776system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034866 # miss rate for overall accesses 1777system.cpu1.dcache.overall_miss_rate::total 0.034866 # miss rate for overall accesses 1778system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14898.189952 # average ReadReq miss latency 1779system.cpu1.dcache.ReadReq_avg_miss_latency::total 14898.189952 # average ReadReq miss latency 1780system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18930.599639 # average WriteReq miss latency 1781system.cpu1.dcache.WriteReq_avg_miss_latency::total 18930.599639 # average WriteReq miss latency 1782system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 20482.344489 # average WriteLineReq miss latency 1783system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 20482.344489 # average WriteLineReq miss latency 1784system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15468.149764 # average LoadLockedReq miss latency 1785system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15468.149764 # average LoadLockedReq miss latency 1786system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23881.378602 # average StoreCondReq miss latency 1787system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23881.378602 # average StoreCondReq miss latency 1788system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1789system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1790system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16592.450321 # average overall miss latency 1791system.cpu1.dcache.demand_avg_miss_latency::total 16592.450321 # average overall miss latency 1792system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 14730.871777 # average overall miss latency 1793system.cpu1.dcache.overall_avg_miss_latency::total 14730.871777 # average overall miss latency 1794system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1795system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1796system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1797system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1798system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1799system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1800system.cpu1.dcache.writebacks::writebacks 5478037 # number of writebacks 1801system.cpu1.dcache.writebacks::total 5478037 # number of writebacks 1802system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 17265 # number of ReadReq MSHR hits 1803system.cpu1.dcache.ReadReq_mshr_hits::total 17265 # number of ReadReq MSHR hits 1804system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 318 # number of WriteReq MSHR hits 1805system.cpu1.dcache.WriteReq_mshr_hits::total 318 # number of WriteReq MSHR hits 1806system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 49763 # number of LoadLockedReq MSHR hits 1807system.cpu1.dcache.LoadLockedReq_mshr_hits::total 49763 # number of LoadLockedReq MSHR hits 1808system.cpu1.dcache.demand_mshr_hits::cpu1.data 17583 # number of demand (read+write) MSHR hits 1809system.cpu1.dcache.demand_mshr_hits::total 17583 # number of demand (read+write) MSHR hits 1810system.cpu1.dcache.overall_mshr_hits::cpu1.data 17583 # number of overall MSHR hits 1811system.cpu1.dcache.overall_mshr_hits::total 17583 # number of overall MSHR hits 1812system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3098287 # number of ReadReq MSHR misses 1813system.cpu1.dcache.ReadReq_mshr_misses::total 3098287 # number of ReadReq MSHR misses 1814system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1383097 # number of WriteReq MSHR misses 1815system.cpu1.dcache.WriteReq_mshr_misses::total 1383097 # number of WriteReq MSHR misses 1816system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 634948 # number of SoftPFReq MSHR misses 1817system.cpu1.dcache.SoftPFReq_mshr_misses::total 634948 # number of SoftPFReq MSHR misses 1818system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 525445 # number of WriteLineReq MSHR misses 1819system.cpu1.dcache.WriteLineReq_mshr_misses::total 525445 # number of WriteLineReq MSHR misses 1820system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 129906 # number of LoadLockedReq MSHR misses 1821system.cpu1.dcache.LoadLockedReq_mshr_misses::total 129906 # number of LoadLockedReq MSHR misses 1822system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202611 # number of StoreCondReq MSHR misses 1823system.cpu1.dcache.StoreCondReq_mshr_misses::total 202611 # number of StoreCondReq MSHR misses 1824system.cpu1.dcache.demand_mshr_misses::cpu1.data 5006829 # number of demand (read+write) MSHR misses 1825system.cpu1.dcache.demand_mshr_misses::total 5006829 # number of demand (read+write) MSHR misses 1826system.cpu1.dcache.overall_mshr_misses::cpu1.data 5641777 # number of overall MSHR misses 1827system.cpu1.dcache.overall_mshr_misses::total 5641777 # number of overall MSHR misses 1828system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 22372 # number of ReadReq MSHR uncacheable 1829system.cpu1.dcache.ReadReq_mshr_uncacheable::total 22372 # number of ReadReq MSHR uncacheable 1830system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable 1831system.cpu1.dcache.WriteReq_mshr_uncacheable::total 21343 # number of WriteReq MSHR uncacheable 1832system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 43715 # number of overall MSHR uncacheable misses 1833system.cpu1.dcache.overall_mshr_uncacheable_misses::total 43715 # number of overall MSHR uncacheable misses 1834system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42239304500 # number of ReadReq MSHR miss cycles 1835system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42239304500 # number of ReadReq MSHR miss cycles 1836system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 24787763000 # number of WriteReq MSHR miss cycles 1837system.cpu1.dcache.WriteReq_mshr_miss_latency::total 24787763000 # number of WriteReq MSHR miss cycles 1838system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13852353000 # number of SoftPFReq MSHR miss cycles 1839system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13852353000 # number of SoftPFReq MSHR miss cycles 1840system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 10236900500 # number of WriteLineReq MSHR miss cycles 1841system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 10236900500 # number of WriteLineReq MSHR miss cycles 1842system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1787997500 # number of LoadLockedReq MSHR miss cycles 1843system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1787997500 # number of LoadLockedReq MSHR miss cycles 1844system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4636074000 # number of StoreCondReq MSHR miss cycles 1845system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4636074000 # number of StoreCondReq MSHR miss cycles 1846system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2191000 # number of StoreCondFailReq MSHR miss cycles 1847system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2191000 # number of StoreCondFailReq MSHR miss cycles 1848system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 77263968000 # number of demand (read+write) MSHR miss cycles 1849system.cpu1.dcache.demand_mshr_miss_latency::total 77263968000 # number of demand (read+write) MSHR miss cycles 1850system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 91116321000 # number of overall MSHR miss cycles 1851system.cpu1.dcache.overall_mshr_miss_latency::total 91116321000 # number of overall MSHR miss cycles 1852system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3993280500 # number of ReadReq MSHR uncacheable cycles 1853system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3993280500 # number of ReadReq MSHR uncacheable cycles 1854system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3993280500 # number of overall MSHR uncacheable cycles 1855system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3993280500 # number of overall MSHR uncacheable cycles 1856system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036838 # mshr miss rate for ReadReq accesses 1857system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036838 # mshr miss rate for ReadReq accesses 1858system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018019 # mshr miss rate for WriteReq accesses 1859system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018019 # mshr miss rate for WriteReq accesses 1860system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.770955 # mshr miss rate for SoftPFReq accesses 1861system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.770955 # mshr miss rate for SoftPFReq accesses 1862system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.833146 # mshr miss rate for WriteLineReq accesses 1863system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.833146 # mshr miss rate for WriteLineReq accesses 1864system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.066203 # mshr miss rate for LoadLockedReq accesses 1865system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.066203 # mshr miss rate for LoadLockedReq accesses 1866system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103321 # mshr miss rate for StoreCondReq accesses 1867system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103321 # mshr miss rate for StoreCondReq accesses 1868system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031003 # mshr miss rate for demand accesses 1869system.cpu1.dcache.demand_mshr_miss_rate::total 0.031003 # mshr miss rate for demand accesses 1870system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034757 # mshr miss rate for overall accesses 1871system.cpu1.dcache.overall_mshr_miss_rate::total 0.034757 # mshr miss rate for overall accesses 1872system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13633.115493 # average ReadReq mshr miss latency 1873system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13633.115493 # average ReadReq mshr miss latency 1874system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 17921.926662 # average WriteReq mshr miss latency 1875system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 17921.926662 # average WriteReq mshr miss latency 1876system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21816.515683 # average SoftPFReq mshr miss latency 1877system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21816.515683 # average SoftPFReq mshr miss latency 1878system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 19482.344489 # average WriteLineReq mshr miss latency 1879system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 19482.344489 # average WriteLineReq mshr miss latency 1880system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13763.779194 # average LoadLockedReq mshr miss latency 1881system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13763.779194 # average LoadLockedReq mshr miss latency 1882system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22881.650058 # average StoreCondReq mshr miss latency 1883system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22881.650058 # average StoreCondReq mshr miss latency 1884system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1885system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1886system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15431.716961 # average overall mshr miss latency 1887system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15431.716961 # average overall mshr miss latency 1888system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16150.287578 # average overall mshr miss latency 1889system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16150.287578 # average overall mshr miss latency 1890system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178494.569104 # average ReadReq mshr uncacheable latency 1891system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178494.569104 # average ReadReq mshr uncacheable latency 1892system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 91348.061306 # average overall mshr uncacheable latency 1893system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 91348.061306 # average overall mshr uncacheable latency 1894system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1895system.cpu1.icache.tags.replacements 5778503 # number of replacements 1896system.cpu1.icache.tags.tagsinuse 496.250731 # Cycle average of tags in use 1897system.cpu1.icache.tags.total_refs 417050198 # Total number of references to valid blocks. 1898system.cpu1.icache.tags.sampled_refs 5779015 # Sample count of references to valid blocks. 1899system.cpu1.icache.tags.avg_refs 72.166312 # Average number of references to valid blocks. 1900system.cpu1.icache.tags.warmup_cycle 8375901500000 # Cycle when the warmup percentage was hit. 1901system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.250731 # Average occupied blocks per requestor 1902system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969240 # Average percentage of cache occupancy 1903system.cpu1.icache.tags.occ_percent::total 0.969240 # Average percentage of cache occupancy 1904system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1905system.cpu1.icache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id 1906system.cpu1.icache.tags.age_task_id_blocks_1024::1 323 # Occupied blocks per task id 1907system.cpu1.icache.tags.age_task_id_blocks_1024::2 129 # Occupied blocks per task id 1908system.cpu1.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1909system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1910system.cpu1.icache.tags.tag_accesses 851437456 # Number of tag accesses 1911system.cpu1.icache.tags.data_accesses 851437456 # Number of data accesses 1912system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1913system.cpu1.icache.ReadReq_hits::cpu1.inst 417050198 # number of ReadReq hits 1914system.cpu1.icache.ReadReq_hits::total 417050198 # number of ReadReq hits 1915system.cpu1.icache.demand_hits::cpu1.inst 417050198 # number of demand (read+write) hits 1916system.cpu1.icache.demand_hits::total 417050198 # number of demand (read+write) hits 1917system.cpu1.icache.overall_hits::cpu1.inst 417050198 # number of overall hits 1918system.cpu1.icache.overall_hits::total 417050198 # number of overall hits 1919system.cpu1.icache.ReadReq_misses::cpu1.inst 5779020 # number of ReadReq misses 1920system.cpu1.icache.ReadReq_misses::total 5779020 # number of ReadReq misses 1921system.cpu1.icache.demand_misses::cpu1.inst 5779020 # number of demand (read+write) misses 1922system.cpu1.icache.demand_misses::total 5779020 # number of demand (read+write) misses 1923system.cpu1.icache.overall_misses::cpu1.inst 5779020 # number of overall misses 1924system.cpu1.icache.overall_misses::total 5779020 # number of overall misses 1925system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 61138169500 # number of ReadReq miss cycles 1926system.cpu1.icache.ReadReq_miss_latency::total 61138169500 # number of ReadReq miss cycles 1927system.cpu1.icache.demand_miss_latency::cpu1.inst 61138169500 # number of demand (read+write) miss cycles 1928system.cpu1.icache.demand_miss_latency::total 61138169500 # number of demand (read+write) miss cycles 1929system.cpu1.icache.overall_miss_latency::cpu1.inst 61138169500 # number of overall miss cycles 1930system.cpu1.icache.overall_miss_latency::total 61138169500 # number of overall miss cycles 1931system.cpu1.icache.ReadReq_accesses::cpu1.inst 422829218 # number of ReadReq accesses(hits+misses) 1932system.cpu1.icache.ReadReq_accesses::total 422829218 # number of ReadReq accesses(hits+misses) 1933system.cpu1.icache.demand_accesses::cpu1.inst 422829218 # number of demand (read+write) accesses 1934system.cpu1.icache.demand_accesses::total 422829218 # number of demand (read+write) accesses 1935system.cpu1.icache.overall_accesses::cpu1.inst 422829218 # number of overall (read+write) accesses 1936system.cpu1.icache.overall_accesses::total 422829218 # number of overall (read+write) accesses 1937system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013668 # miss rate for ReadReq accesses 1938system.cpu1.icache.ReadReq_miss_rate::total 0.013668 # miss rate for ReadReq accesses 1939system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013668 # miss rate for demand accesses 1940system.cpu1.icache.demand_miss_rate::total 0.013668 # miss rate for demand accesses 1941system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013668 # miss rate for overall accesses 1942system.cpu1.icache.overall_miss_rate::total 0.013668 # miss rate for overall accesses 1943system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10579.331703 # average ReadReq miss latency 1944system.cpu1.icache.ReadReq_avg_miss_latency::total 10579.331703 # average ReadReq miss latency 1945system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency 1946system.cpu1.icache.demand_avg_miss_latency::total 10579.331703 # average overall miss latency 1947system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10579.331703 # average overall miss latency 1948system.cpu1.icache.overall_avg_miss_latency::total 10579.331703 # average overall miss latency 1949system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1950system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1951system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1952system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1953system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1954system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1955system.cpu1.icache.writebacks::writebacks 5778503 # number of writebacks 1956system.cpu1.icache.writebacks::total 5778503 # number of writebacks 1957system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5779020 # number of ReadReq MSHR misses 1958system.cpu1.icache.ReadReq_mshr_misses::total 5779020 # number of ReadReq MSHR misses 1959system.cpu1.icache.demand_mshr_misses::cpu1.inst 5779020 # number of demand (read+write) MSHR misses 1960system.cpu1.icache.demand_mshr_misses::total 5779020 # number of demand (read+write) MSHR misses 1961system.cpu1.icache.overall_mshr_misses::cpu1.inst 5779020 # number of overall MSHR misses 1962system.cpu1.icache.overall_mshr_misses::total 5779020 # number of overall MSHR misses 1963system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1964system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1965system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1966system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 1967system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 58248659500 # number of ReadReq MSHR miss cycles 1968system.cpu1.icache.ReadReq_mshr_miss_latency::total 58248659500 # number of ReadReq MSHR miss cycles 1969system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 58248659500 # number of demand (read+write) MSHR miss cycles 1970system.cpu1.icache.demand_mshr_miss_latency::total 58248659500 # number of demand (read+write) MSHR miss cycles 1971system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 58248659500 # number of overall MSHR miss cycles 1972system.cpu1.icache.overall_mshr_miss_latency::total 58248659500 # number of overall MSHR miss cycles 1973system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10594500 # number of ReadReq MSHR uncacheable cycles 1974system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10594500 # number of ReadReq MSHR uncacheable cycles 1975system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10594500 # number of overall MSHR uncacheable cycles 1976system.cpu1.icache.overall_mshr_uncacheable_latency::total 10594500 # number of overall MSHR uncacheable cycles 1977system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for ReadReq accesses 1978system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013668 # mshr miss rate for ReadReq accesses 1979system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for demand accesses 1980system.cpu1.icache.demand_mshr_miss_rate::total 0.013668 # mshr miss rate for demand accesses 1981system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013668 # mshr miss rate for overall accesses 1982system.cpu1.icache.overall_mshr_miss_rate::total 0.013668 # mshr miss rate for overall accesses 1983system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average ReadReq mshr miss latency 1984system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10079.331703 # average ReadReq mshr miss latency 1985system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency 1986system.cpu1.icache.demand_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency 1987system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10079.331703 # average overall mshr miss latency 1988system.cpu1.icache.overall_avg_mshr_miss_latency::total 10079.331703 # average overall mshr miss latency 1989system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average ReadReq mshr uncacheable latency 1990system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 96313.636364 # average ReadReq mshr uncacheable latency 1991system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 96313.636364 # average overall mshr uncacheable latency 1992system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 96313.636364 # average overall mshr uncacheable latency 1993system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 1994system.cpu1.l2cache.prefetcher.num_hwpf_issued 7190671 # number of hwpf issued 1995system.cpu1.l2cache.prefetcher.pfIdentified 7190679 # number of prefetch candidates identified 1996system.cpu1.l2cache.prefetcher.pfBufferHit 7 # number of redundant prefetches already in prefetch queue 1997system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1998system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1999system.cpu1.l2cache.prefetcher.pfSpanPage 898577 # number of prefetches not generated due to page crossing 2000system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 2001system.cpu1.l2cache.tags.replacements 1924030 # number of replacements 2002system.cpu1.l2cache.tags.tagsinuse 12969.443296 # Cycle average of tags in use 2003system.cpu1.l2cache.tags.total_refs 10103718 # Total number of references to valid blocks. 2004system.cpu1.l2cache.tags.sampled_refs 1939825 # Sample count of references to valid blocks. 2005system.cpu1.l2cache.tags.avg_refs 5.208572 # Average number of references to valid blocks. 2006system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2007system.cpu1.l2cache.tags.occ_blocks::writebacks 12701.469256 # Average occupied blocks per requestor 2008system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 37.295961 # Average occupied blocks per requestor 2009system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 26.822764 # Average occupied blocks per requestor 2010system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 203.855315 # Average occupied blocks per requestor 2011system.cpu1.l2cache.tags.occ_percent::writebacks 0.775236 # Average percentage of cache occupancy 2012system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002276 # Average percentage of cache occupancy 2013system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001637 # Average percentage of cache occupancy 2014system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.012442 # Average percentage of cache occupancy 2015system.cpu1.l2cache.tags.occ_percent::total 0.791592 # Average percentage of cache occupancy 2016system.cpu1.l2cache.tags.occ_task_id_blocks::1022 331 # Occupied blocks per task id 2017system.cpu1.l2cache.tags.occ_task_id_blocks::1023 61 # Occupied blocks per task id 2018system.cpu1.l2cache.tags.occ_task_id_blocks::1024 15403 # Occupied blocks per task id 2019system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id 2020system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 142 # Occupied blocks per task id 2021system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 95 # Occupied blocks per task id 2022system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 88 # Occupied blocks per task id 2023system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id 2024system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 32 # Occupied blocks per task id 2025system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id 2026system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 15 # Occupied blocks per task id 2027system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id 2028system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1498 # Occupied blocks per task id 2029system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5779 # Occupied blocks per task id 2030system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5762 # Occupied blocks per task id 2031system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2244 # Occupied blocks per task id 2032system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.020203 # Percentage of cache occupancy per task id 2033system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003723 # Percentage of cache occupancy per task id 2034system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.940125 # Percentage of cache occupancy per task id 2035system.cpu1.l2cache.tags.tag_accesses 387081443 # Number of tag accesses 2036system.cpu1.l2cache.tags.data_accesses 387081443 # Number of data accesses 2037system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 2038system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 243745 # number of ReadReq hits 2039system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 174457 # number of ReadReq hits 2040system.cpu1.l2cache.ReadReq_hits::total 418202 # number of ReadReq hits 2041system.cpu1.l2cache.WritebackDirty_hits::writebacks 3475258 # number of WritebackDirty hits 2042system.cpu1.l2cache.WritebackDirty_hits::total 3475258 # number of WritebackDirty hits 2043system.cpu1.l2cache.WritebackClean_hits::writebacks 7780467 # number of WritebackClean hits 2044system.cpu1.l2cache.WritebackClean_hits::total 7780467 # number of WritebackClean hits 2045system.cpu1.l2cache.ReadExReq_hits::cpu1.data 920068 # number of ReadExReq hits 2046system.cpu1.l2cache.ReadExReq_hits::total 920068 # number of ReadExReq hits 2047system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5308980 # number of ReadCleanReq hits 2048system.cpu1.l2cache.ReadCleanReq_hits::total 5308980 # number of ReadCleanReq hits 2049system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2962504 # number of ReadSharedReq hits 2050system.cpu1.l2cache.ReadSharedReq_hits::total 2962504 # number of ReadSharedReq hits 2051system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 264311 # number of InvalidateReq hits 2052system.cpu1.l2cache.InvalidateReq_hits::total 264311 # number of InvalidateReq hits 2053system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 243745 # number of demand (read+write) hits 2054system.cpu1.l2cache.demand_hits::cpu1.itb.walker 174457 # number of demand (read+write) hits 2055system.cpu1.l2cache.demand_hits::cpu1.inst 5308980 # number of demand (read+write) hits 2056system.cpu1.l2cache.demand_hits::cpu1.data 3882572 # number of demand (read+write) hits 2057system.cpu1.l2cache.demand_hits::total 9609754 # number of demand (read+write) hits 2058system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 243745 # number of overall hits 2059system.cpu1.l2cache.overall_hits::cpu1.itb.walker 174457 # number of overall hits 2060system.cpu1.l2cache.overall_hits::cpu1.inst 5308980 # number of overall hits 2061system.cpu1.l2cache.overall_hits::cpu1.data 3882572 # number of overall hits 2062system.cpu1.l2cache.overall_hits::total 9609754 # number of overall hits 2063system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 18156 # number of ReadReq misses 2064system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9553 # number of ReadReq misses 2065system.cpu1.l2cache.ReadReq_misses::total 27709 # number of ReadReq misses 2066system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 208398 # number of UpgradeReq misses 2067system.cpu1.l2cache.UpgradeReq_misses::total 208398 # number of UpgradeReq misses 2068system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 202605 # number of SCUpgradeReq misses 2069system.cpu1.l2cache.SCUpgradeReq_misses::total 202605 # number of SCUpgradeReq misses 2070system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 6 # number of SCUpgradeFailReq misses 2071system.cpu1.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses 2072system.cpu1.l2cache.ReadExReq_misses::cpu1.data 254808 # number of ReadExReq misses 2073system.cpu1.l2cache.ReadExReq_misses::total 254808 # number of ReadExReq misses 2074system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 470040 # number of ReadCleanReq misses 2075system.cpu1.l2cache.ReadCleanReq_misses::total 470040 # number of ReadCleanReq misses 2076system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 900637 # number of ReadSharedReq misses 2077system.cpu1.l2cache.ReadSharedReq_misses::total 900637 # number of ReadSharedReq misses 2078system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 261134 # number of InvalidateReq misses 2079system.cpu1.l2cache.InvalidateReq_misses::total 261134 # number of InvalidateReq misses 2080system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 18156 # number of demand (read+write) misses 2081system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9553 # number of demand (read+write) misses 2082system.cpu1.l2cache.demand_misses::cpu1.inst 470040 # number of demand (read+write) misses 2083system.cpu1.l2cache.demand_misses::cpu1.data 1155445 # number of demand (read+write) misses 2084system.cpu1.l2cache.demand_misses::total 1653194 # number of demand (read+write) misses 2085system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 18156 # number of overall misses 2086system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9553 # number of overall misses 2087system.cpu1.l2cache.overall_misses::cpu1.inst 470040 # number of overall misses 2088system.cpu1.l2cache.overall_misses::cpu1.data 1155445 # number of overall misses 2089system.cpu1.l2cache.overall_misses::total 1653194 # number of overall misses 2090system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 581758000 # number of ReadReq miss cycles 2091system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 383665000 # number of ReadReq miss cycles 2092system.cpu1.l2cache.ReadReq_miss_latency::total 965423000 # number of ReadReq miss cycles 2093system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 884282500 # number of UpgradeReq miss cycles 2094system.cpu1.l2cache.UpgradeReq_miss_latency::total 884282500 # number of UpgradeReq miss cycles 2095system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 360962500 # number of SCUpgradeReq miss cycles 2096system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 360962500 # number of SCUpgradeReq miss cycles 2097system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2107498 # number of SCUpgradeFailReq miss cycles 2098system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2107498 # number of SCUpgradeFailReq miss cycles 2099system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 11534187000 # number of ReadExReq miss cycles 2100system.cpu1.l2cache.ReadExReq_miss_latency::total 11534187000 # number of ReadExReq miss cycles 2101system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 17654070500 # number of ReadCleanReq miss cycles 2102system.cpu1.l2cache.ReadCleanReq_miss_latency::total 17654070500 # number of ReadCleanReq miss cycles 2103system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 32780970500 # number of ReadSharedReq miss cycles 2104system.cpu1.l2cache.ReadSharedReq_miss_latency::total 32780970500 # number of ReadSharedReq miss cycles 2105system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 198500 # number of InvalidateReq miss cycles 2106system.cpu1.l2cache.InvalidateReq_miss_latency::total 198500 # number of InvalidateReq miss cycles 2107system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 581758000 # number of demand (read+write) miss cycles 2108system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 383665000 # number of demand (read+write) miss cycles 2109system.cpu1.l2cache.demand_miss_latency::cpu1.inst 17654070500 # number of demand (read+write) miss cycles 2110system.cpu1.l2cache.demand_miss_latency::cpu1.data 44315157500 # number of demand (read+write) miss cycles 2111system.cpu1.l2cache.demand_miss_latency::total 62934651000 # number of demand (read+write) miss cycles 2112system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 581758000 # number of overall miss cycles 2113system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 383665000 # number of overall miss cycles 2114system.cpu1.l2cache.overall_miss_latency::cpu1.inst 17654070500 # number of overall miss cycles 2115system.cpu1.l2cache.overall_miss_latency::cpu1.data 44315157500 # number of overall miss cycles 2116system.cpu1.l2cache.overall_miss_latency::total 62934651000 # number of overall miss cycles 2117system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 261901 # number of ReadReq accesses(hits+misses) 2118system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 184010 # number of ReadReq accesses(hits+misses) 2119system.cpu1.l2cache.ReadReq_accesses::total 445911 # number of ReadReq accesses(hits+misses) 2120system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3475258 # number of WritebackDirty accesses(hits+misses) 2121system.cpu1.l2cache.WritebackDirty_accesses::total 3475258 # number of WritebackDirty accesses(hits+misses) 2122system.cpu1.l2cache.WritebackClean_accesses::writebacks 7780467 # number of WritebackClean accesses(hits+misses) 2123system.cpu1.l2cache.WritebackClean_accesses::total 7780467 # number of WritebackClean accesses(hits+misses) 2124system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 208398 # number of UpgradeReq accesses(hits+misses) 2125system.cpu1.l2cache.UpgradeReq_accesses::total 208398 # number of UpgradeReq accesses(hits+misses) 2126system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202605 # number of SCUpgradeReq accesses(hits+misses) 2127system.cpu1.l2cache.SCUpgradeReq_accesses::total 202605 # number of SCUpgradeReq accesses(hits+misses) 2128system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 6 # number of SCUpgradeFailReq accesses(hits+misses) 2129system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) 2130system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1174876 # number of ReadExReq accesses(hits+misses) 2131system.cpu1.l2cache.ReadExReq_accesses::total 1174876 # number of ReadExReq accesses(hits+misses) 2132system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5779020 # number of ReadCleanReq accesses(hits+misses) 2133system.cpu1.l2cache.ReadCleanReq_accesses::total 5779020 # number of ReadCleanReq accesses(hits+misses) 2134system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3863141 # number of ReadSharedReq accesses(hits+misses) 2135system.cpu1.l2cache.ReadSharedReq_accesses::total 3863141 # number of ReadSharedReq accesses(hits+misses) 2136system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 525445 # number of InvalidateReq accesses(hits+misses) 2137system.cpu1.l2cache.InvalidateReq_accesses::total 525445 # number of InvalidateReq accesses(hits+misses) 2138system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 261901 # number of demand (read+write) accesses 2139system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 184010 # number of demand (read+write) accesses 2140system.cpu1.l2cache.demand_accesses::cpu1.inst 5779020 # number of demand (read+write) accesses 2141system.cpu1.l2cache.demand_accesses::cpu1.data 5038017 # number of demand (read+write) accesses 2142system.cpu1.l2cache.demand_accesses::total 11262948 # number of demand (read+write) accesses 2143system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 261901 # number of overall (read+write) accesses 2144system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 184010 # number of overall (read+write) accesses 2145system.cpu1.l2cache.overall_accesses::cpu1.inst 5779020 # number of overall (read+write) accesses 2146system.cpu1.l2cache.overall_accesses::cpu1.data 5038017 # number of overall (read+write) accesses 2147system.cpu1.l2cache.overall_accesses::total 11262948 # number of overall (read+write) accesses 2148system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for ReadReq accesses 2149system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.051916 # miss rate for ReadReq accesses 2150system.cpu1.l2cache.ReadReq_miss_rate::total 0.062140 # miss rate for ReadReq accesses 2151system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses 2152system.cpu1.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 2153system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses 2154system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses 2155system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2156system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2157system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.216881 # miss rate for ReadExReq accesses 2158system.cpu1.l2cache.ReadExReq_miss_rate::total 0.216881 # miss rate for ReadExReq accesses 2159system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.081336 # miss rate for ReadCleanReq accesses 2160system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.081336 # miss rate for ReadCleanReq accesses 2161system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.233136 # miss rate for ReadSharedReq accesses 2162system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.233136 # miss rate for ReadSharedReq accesses 2163system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.496977 # miss rate for InvalidateReq accesses 2164system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.496977 # miss rate for InvalidateReq accesses 2165system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for demand accesses 2166system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.051916 # miss rate for demand accesses 2167system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.081336 # miss rate for demand accesses 2168system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.229345 # miss rate for demand accesses 2169system.cpu1.l2cache.demand_miss_rate::total 0.146782 # miss rate for demand accesses 2170system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.069324 # miss rate for overall accesses 2171system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.051916 # miss rate for overall accesses 2172system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.081336 # miss rate for overall accesses 2173system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.229345 # miss rate for overall accesses 2174system.cpu1.l2cache.overall_miss_rate::total 0.146782 # miss rate for overall accesses 2175system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average ReadReq miss latency 2176system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 40161.729300 # average ReadReq miss latency 2177system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34841.495543 # average ReadReq miss latency 2178system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4243.238899 # average UpgradeReq miss latency 2179system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4243.238899 # average UpgradeReq miss latency 2180system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1781.607068 # average SCUpgradeReq miss latency 2181system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1781.607068 # average SCUpgradeReq miss latency 2182system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 351249.666667 # average SCUpgradeFailReq miss latency 2183system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 351249.666667 # average SCUpgradeFailReq miss latency 2184system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 45266.188660 # average ReadExReq miss latency 2185system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 45266.188660 # average ReadExReq miss latency 2186system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 37558.655646 # average ReadCleanReq miss latency 2187system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 37558.655646 # average ReadCleanReq miss latency 2188system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 36397.539186 # average ReadSharedReq miss latency 2189system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 36397.539186 # average ReadSharedReq miss latency 2190system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 0.760146 # average InvalidateReq miss latency 2191system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 0.760146 # average InvalidateReq miss latency 2192system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average overall miss latency 2193system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 40161.729300 # average overall miss latency 2194system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 37558.655646 # average overall miss latency 2195system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 38353.324909 # average overall miss latency 2196system.cpu1.l2cache.demand_avg_miss_latency::total 38068.521299 # average overall miss latency 2197system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32042.189910 # average overall miss latency 2198system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 40161.729300 # average overall miss latency 2199system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 37558.655646 # average overall miss latency 2200system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 38353.324909 # average overall miss latency 2201system.cpu1.l2cache.overall_avg_miss_latency::total 38068.521299 # average overall miss latency 2202system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2203system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2204system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2205system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2206system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2207system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2208system.cpu1.l2cache.unused_prefetches 40493 # number of HardPF blocks evicted w/o reference 2209system.cpu1.l2cache.writebacks::writebacks 1134178 # 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number of ReadReq MSHR misses 2222system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9553 # number of ReadReq MSHR misses 2223system.cpu1.l2cache.ReadReq_mshr_misses::total 27709 # number of ReadReq MSHR misses 2224system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 685885 # number of HardPFReq MSHR misses 2225system.cpu1.l2cache.HardPFReq_mshr_misses::total 685885 # number of HardPFReq MSHR misses 2226system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 208398 # number of UpgradeReq MSHR misses 2227system.cpu1.l2cache.UpgradeReq_mshr_misses::total 208398 # number of UpgradeReq MSHR misses 2228system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 202605 # number of SCUpgradeReq MSHR misses 2229system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 202605 # number of SCUpgradeReq MSHR misses 2230system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 6 # number of SCUpgradeFailReq MSHR misses 2231system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 6 # number of SCUpgradeFailReq MSHR misses 2232system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 250166 # number of ReadExReq MSHR misses 2233system.cpu1.l2cache.ReadExReq_mshr_misses::total 250166 # number of ReadExReq MSHR misses 2234system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 470040 # number of ReadCleanReq MSHR misses 2235system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 470040 # number of ReadCleanReq MSHR misses 2236system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 900222 # number of ReadSharedReq MSHR misses 2237system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 900222 # number of ReadSharedReq MSHR misses 2238system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 261133 # number of InvalidateReq MSHR misses 2239system.cpu1.l2cache.InvalidateReq_mshr_misses::total 261133 # number of InvalidateReq MSHR misses 2240system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 18156 # number of demand (read+write) MSHR misses 2241system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9553 # number of demand (read+write) MSHR misses 2242system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 470040 # number of demand (read+write) MSHR misses 2243system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1150388 # number of demand (read+write) MSHR misses 2244system.cpu1.l2cache.demand_mshr_misses::total 1648137 # number of demand (read+write) MSHR misses 2245system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 18156 # number of overall MSHR misses 2246system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9553 # number of overall MSHR misses 2247system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 470040 # number of overall MSHR misses 2248system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1150388 # number of overall MSHR misses 2249system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 685885 # number of overall MSHR misses 2250system.cpu1.l2cache.overall_mshr_misses::total 2334022 # number of overall MSHR misses 2251system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2252system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 22372 # number of ReadReq MSHR uncacheable 2253system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 22482 # number of ReadReq MSHR uncacheable 2254system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable 2255system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 21343 # number of WriteReq MSHR uncacheable 2256system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2257system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 43715 # number of overall MSHR uncacheable misses 2258system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 43825 # number of overall MSHR uncacheable misses 2259system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of ReadReq MSHR miss cycles 2260system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 326347000 # number of ReadReq MSHR miss cycles 2261system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 799169000 # number of ReadReq MSHR miss cycles 2262system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 28141665535 # number of HardPFReq MSHR miss cycles 2263system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 28141665535 # number of HardPFReq MSHR miss cycles 2264system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 3910093000 # number of UpgradeReq MSHR miss cycles 2265system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 3910093000 # number of UpgradeReq MSHR miss cycles 2266system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 3115291500 # number of SCUpgradeReq MSHR miss cycles 2267system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 3115291500 # number of SCUpgradeReq MSHR miss cycles 2268system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1777498 # number of SCUpgradeFailReq MSHR miss cycles 2269system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1777498 # number of SCUpgradeFailReq MSHR miss cycles 2270system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 9489009000 # number of ReadExReq MSHR miss cycles 2271system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 9489009000 # number of ReadExReq MSHR miss cycles 2272system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 14833830500 # number of ReadCleanReq MSHR miss cycles 2273system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 14833830500 # number of ReadCleanReq MSHR miss cycles 2274system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 27315818000 # number of ReadSharedReq MSHR miss cycles 2275system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 27315818000 # number of ReadSharedReq MSHR miss cycles 2276system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6163710000 # number of InvalidateReq MSHR miss cycles 2277system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6163710000 # number of InvalidateReq MSHR miss cycles 2278system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of demand (read+write) MSHR miss cycles 2279system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 326347000 # number of demand (read+write) MSHR miss cycles 2280system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 14833830500 # number of demand (read+write) MSHR miss cycles 2281system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 36804827000 # number of demand (read+write) MSHR miss cycles 2282system.cpu1.l2cache.demand_mshr_miss_latency::total 52437826500 # number of demand (read+write) MSHR miss cycles 2283system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 472822000 # number of overall MSHR miss cycles 2284system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 326347000 # number of overall MSHR miss cycles 2285system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 14833830500 # number of overall MSHR miss cycles 2286system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 36804827000 # number of overall MSHR miss cycles 2287system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 28141665535 # number of overall MSHR miss cycles 2288system.cpu1.l2cache.overall_mshr_miss_latency::total 80579492035 # number of overall MSHR miss cycles 2289system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9769500 # number of ReadReq MSHR uncacheable cycles 2290system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3813749500 # number of ReadReq MSHR uncacheable cycles 2291system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3823519000 # number of ReadReq MSHR uncacheable cycles 2292system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9769500 # number of overall MSHR uncacheable cycles 2293system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3813749500 # number of overall MSHR uncacheable cycles 2294system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3823519000 # number of overall MSHR uncacheable cycles 2295system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for ReadReq accesses 2296system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for ReadReq accesses 2297system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.062140 # mshr miss rate for ReadReq accesses 2298system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2299system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2300system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses 2301system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 2302system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses 2303system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses 2304system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2305system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2306system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.212930 # mshr miss rate for ReadExReq accesses 2307system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.212930 # mshr miss rate for ReadExReq accesses 2308system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for ReadCleanReq accesses 2309system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.081336 # mshr miss rate for ReadCleanReq accesses 2310system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.233029 # mshr miss rate for ReadSharedReq accesses 2311system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.233029 # mshr miss rate for ReadSharedReq accesses 2312system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.496975 # mshr miss rate for InvalidateReq accesses 2313system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.496975 # mshr miss rate for InvalidateReq accesses 2314system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for demand accesses 2315system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for demand accesses 2316system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for demand accesses 2317system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.228341 # mshr miss rate for demand accesses 2318system.cpu1.l2cache.demand_mshr_miss_rate::total 0.146333 # mshr miss rate for demand accesses 2319system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.069324 # mshr miss rate for overall accesses 2320system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.051916 # mshr miss rate for overall accesses 2321system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.081336 # mshr miss rate for overall accesses 2322system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.228341 # mshr miss rate for overall accesses 2323system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2324system.cpu1.l2cache.overall_mshr_miss_rate::total 0.207230 # mshr miss rate for overall accesses 2325system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average ReadReq mshr miss latency 2326system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average ReadReq mshr miss latency 2327system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28841.495543 # average ReadReq mshr miss latency 2328system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average HardPFReq mshr miss latency 2329system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41029.714216 # average HardPFReq mshr miss latency 2330system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18762.622482 # average UpgradeReq mshr miss latency 2331system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18762.622482 # average UpgradeReq mshr miss latency 2332system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15376.182720 # average SCUpgradeReq mshr miss latency 2333system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15376.182720 # average SCUpgradeReq mshr miss latency 2334system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 296249.666667 # average SCUpgradeFailReq mshr miss latency 2335system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 296249.666667 # average SCUpgradeFailReq mshr miss latency 2336system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37930.849916 # average ReadExReq mshr miss latency 2337system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37930.849916 # average ReadExReq mshr miss latency 2338system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average ReadCleanReq mshr miss latency 2339system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31558.655646 # average ReadCleanReq mshr miss latency 2340system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 30343.424178 # average ReadSharedReq mshr miss latency 2341system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 30343.424178 # average ReadSharedReq mshr miss latency 2342system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 23603.719178 # average InvalidateReq mshr miss latency 2343system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 23603.719178 # average InvalidateReq mshr miss latency 2344system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency 2345system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency 2346system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency 2347system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency 2348system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31816.424545 # average overall mshr miss latency 2349system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26042.189910 # average overall mshr miss latency 2350system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 34161.729300 # average overall mshr miss latency 2351system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31558.655646 # average overall mshr miss latency 2352system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 31993.403095 # average overall mshr miss latency 2353system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41029.714216 # average overall mshr miss latency 2354system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 34523.878539 # average overall mshr miss latency 2355system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average ReadReq mshr uncacheable latency 2356system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170469.761309 # average ReadReq mshr uncacheable latency 2357system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170070.233965 # average ReadReq mshr uncacheable latency 2358system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 88813.636364 # average overall mshr uncacheable latency 2359system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 87241.210111 # average overall mshr uncacheable latency 2360system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 87245.156874 # average overall mshr uncacheable latency 2361system.cpu1.toL2Bus.snoop_filter.tot_requests 23256823 # Total number of requests made to the snoop filter. 2362system.cpu1.toL2Bus.snoop_filter.hit_single_requests 11916693 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2363system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 817 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2364system.cpu1.toL2Bus.snoop_filter.tot_snoops 568685 # Total number of snoops made to the snoop filter. 2365system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 568681 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2366system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2367system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 2368system.cpu1.toL2Bus.trans_dist::ReadReq 538115 # Transaction distribution 2369system.cpu1.toL2Bus.trans_dist::ReadResp 10263353 # Transaction distribution 2370system.cpu1.toL2Bus.trans_dist::WriteReq 21343 # Transaction distribution 2371system.cpu1.toL2Bus.trans_dist::WriteResp 21343 # Transaction distribution 2372system.cpu1.toL2Bus.trans_dist::WritebackDirty 4626226 # Transaction distribution 2373system.cpu1.toL2Bus.trans_dist::WritebackClean 7781279 # Transaction distribution 2374system.cpu1.toL2Bus.trans_dist::CleanEvict 1111211 # Transaction distribution 2375system.cpu1.toL2Bus.trans_dist::HardPFReq 833315 # Transaction distribution 2376system.cpu1.toL2Bus.trans_dist::UpgradeReq 380175 # Transaction distribution 2377system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 364314 # Transaction distribution 2378system.cpu1.toL2Bus.trans_dist::UpgradeResp 469217 # Transaction distribution 2379system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution 2380system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution 2381system.cpu1.toL2Bus.trans_dist::ReadExReq 1205096 # Transaction distribution 2382system.cpu1.toL2Bus.trans_dist::ReadExResp 1180975 # Transaction distribution 2383system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5779020 # Transaction distribution 2384system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4693276 # Transaction distribution 2385system.cpu1.toL2Bus.trans_dist::InvalidateReq 584455 # Transaction distribution 2386system.cpu1.toL2Bus.trans_dist::InvalidateResp 526474 # Transaction distribution 2387system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17336763 # Packet count per connected master and slave (bytes) 2388system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17662942 # Packet count per connected master and slave (bytes) 2389system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 385121 # Packet count per connected master and slave (bytes) 2390system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 576423 # Packet count per connected master and slave (bytes) 2391system.cpu1.toL2Bus.pkt_count::total 35961249 # Packet count per connected master and slave (bytes) 2392system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 739681912 # Cumulative packet size per connected master and slave (bytes) 2393system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 678880625 # Cumulative packet size per connected master and slave (bytes) 2394system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1472080 # Cumulative packet size per connected master and slave (bytes) 2395system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2095208 # Cumulative packet size per connected master and slave (bytes) 2396system.cpu1.toL2Bus.pkt_size::total 1422129825 # Cumulative packet size per connected master and slave (bytes) 2397system.cpu1.toL2Bus.snoops 4566671 # Total snoops (count) 2398system.cpu1.toL2Bus.snoopTraffic 79930832 # Total snoop traffic (bytes) 2399system.cpu1.toL2Bus.snoop_fanout::samples 16661362 # Request fanout histogram 2400system.cpu1.toL2Bus.snoop_fanout::mean 0.048994 # Request fanout histogram 2401system.cpu1.toL2Bus.snoop_fanout::stdev 0.215856 # Request fanout histogram 2402system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2403system.cpu1.toL2Bus.snoop_fanout::0 15845064 95.10% 95.10% # Request fanout histogram 2404system.cpu1.toL2Bus.snoop_fanout::1 816294 4.90% 100.00% # Request fanout histogram 2405system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram 2406system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2407system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2408system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2409system.cpu1.toL2Bus.snoop_fanout::total 16661362 # Request fanout histogram 2410system.cpu1.toL2Bus.reqLayer0.occupancy 23051952997 # Layer occupancy (ticks) 2411system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2412system.cpu1.toL2Bus.snoopLayer0.occupancy 163764383 # Layer occupancy (ticks) 2413system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2414system.cpu1.toL2Bus.respLayer0.occupancy 8668640000 # Layer occupancy (ticks) 2415system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2416system.cpu1.toL2Bus.respLayer1.occupancy 8058549119 # Layer occupancy (ticks) 2417system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2418system.cpu1.toL2Bus.respLayer2.occupancy 201111499 # Layer occupancy (ticks) 2419system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2420system.cpu1.toL2Bus.respLayer3.occupancy 314522000 # Layer occupancy (ticks) 2421system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2422system.iobus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 2423system.iobus.trans_dist::ReadReq 40263 # Transaction distribution 2424system.iobus.trans_dist::ReadResp 40263 # Transaction distribution 2425system.iobus.trans_dist::WriteReq 136535 # Transaction distribution 2426system.iobus.trans_dist::WriteResp 136535 # Transaction distribution 2427system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47338 # Packet count per connected master and slave (bytes) 2428system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2429system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2430system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2431system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2432system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2433system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2434system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2435system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2436system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2437system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2438system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 2439system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2440system.iobus.pkt_count_system.bridge.master::total 122272 # Packet count per connected master and slave (bytes) 2441system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231244 # Packet count per connected master and slave (bytes) 2442system.iobus.pkt_count_system.realview.ide.dma::total 231244 # Packet count per connected master and slave (bytes) 2443system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2444system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2445system.iobus.pkt_count::total 353596 # Packet count per connected master and slave (bytes) 2446system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47358 # Cumulative packet size per connected master and slave (bytes) 2447system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2448system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 2449system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2450system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2451system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2452system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2453system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2454system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2455system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2456system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2457system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 2458system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2459system.iobus.pkt_size_system.bridge.master::total 155379 # Cumulative packet size per connected master and slave (bytes) 2460system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338992 # Cumulative packet size per connected master and slave (bytes) 2461system.iobus.pkt_size_system.realview.ide.dma::total 7338992 # Cumulative packet size per connected master and slave (bytes) 2462system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2463system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2464system.iobus.pkt_size::total 7496457 # Cumulative packet size per connected master and slave (bytes) 2465system.iobus.reqLayer0.occupancy 36598000 # Layer occupancy (ticks) 2466system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2467system.iobus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) 2468system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2469system.iobus.reqLayer2.occupancy 319500 # Layer occupancy (ticks) 2470system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2471system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2472system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2473system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) 2474system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 2475system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2476system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2477system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2478system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2479system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks) 2480system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2481system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) 2482system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2483system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 2484system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2485system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2486system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2487system.iobus.reqLayer23.occupancy 25735000 # Layer occupancy (ticks) 2488system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2489system.iobus.reqLayer24.occupancy 37421000 # Layer occupancy (ticks) 2490system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2491system.iobus.reqLayer25.occupancy 570201068 # Layer occupancy (ticks) 2492system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2493system.iobus.respLayer0.occupancy 92468000 # Layer occupancy (ticks) 2494system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2495system.iobus.respLayer3.occupancy 147940000 # Layer occupancy (ticks) 2496system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2497system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 2498system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2499system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 2500system.iocache.tags.replacements 115618 # number of replacements 2501system.iocache.tags.tagsinuse 11.260426 # Cycle average of tags in use 2502system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2503system.iocache.tags.sampled_refs 115634 # Sample count of references to valid blocks. 2504system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2505system.iocache.tags.warmup_cycle 9133276021000 # Cycle when the warmup percentage was hit. 2506system.iocache.tags.occ_blocks::realview.ethernet 7.412431 # Average occupied blocks per requestor 2507system.iocache.tags.occ_blocks::realview.ide 3.847995 # Average occupied blocks per requestor 2508system.iocache.tags.occ_percent::realview.ethernet 0.463277 # Average percentage of cache occupancy 2509system.iocache.tags.occ_percent::realview.ide 0.240500 # Average percentage of cache occupancy 2510system.iocache.tags.occ_percent::total 0.703777 # Average percentage of cache occupancy 2511system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2512system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2513system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2514system.iocache.tags.tag_accesses 1040955 # Number of tag accesses 2515system.iocache.tags.data_accesses 1040955 # Number of data accesses 2516system.iocache.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 2517system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2518system.iocache.ReadReq_misses::realview.ide 8894 # number of ReadReq misses 2519system.iocache.ReadReq_misses::total 8931 # number of ReadReq misses 2520system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2521system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2522system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 2523system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 2524system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2525system.iocache.demand_misses::realview.ide 115622 # number of demand (read+write) misses 2526system.iocache.demand_misses::total 115662 # number of demand (read+write) misses 2527system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2528system.iocache.overall_misses::realview.ide 115622 # number of overall misses 2529system.iocache.overall_misses::total 115662 # number of overall misses 2530system.iocache.ReadReq_miss_latency::realview.ethernet 5195000 # number of ReadReq miss cycles 2531system.iocache.ReadReq_miss_latency::realview.ide 2022255480 # number of ReadReq miss cycles 2532system.iocache.ReadReq_miss_latency::total 2027450480 # number of ReadReq miss cycles 2533system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2534system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2535system.iocache.WriteLineReq_miss_latency::realview.ide 13353085588 # number of WriteLineReq miss cycles 2536system.iocache.WriteLineReq_miss_latency::total 13353085588 # number of WriteLineReq miss cycles 2537system.iocache.demand_miss_latency::realview.ethernet 5564000 # number of demand (read+write) miss cycles 2538system.iocache.demand_miss_latency::realview.ide 15375341068 # number of demand (read+write) miss cycles 2539system.iocache.demand_miss_latency::total 15380905068 # number of demand (read+write) miss cycles 2540system.iocache.overall_miss_latency::realview.ethernet 5564000 # number of overall miss cycles 2541system.iocache.overall_miss_latency::realview.ide 15375341068 # number of overall miss cycles 2542system.iocache.overall_miss_latency::total 15380905068 # number of overall miss cycles 2543system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2544system.iocache.ReadReq_accesses::realview.ide 8894 # number of ReadReq accesses(hits+misses) 2545system.iocache.ReadReq_accesses::total 8931 # number of ReadReq accesses(hits+misses) 2546system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2547system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2548system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 2549system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 2550system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2551system.iocache.demand_accesses::realview.ide 115622 # number of demand (read+write) accesses 2552system.iocache.demand_accesses::total 115662 # number of demand (read+write) accesses 2553system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2554system.iocache.overall_accesses::realview.ide 115622 # number of overall (read+write) accesses 2555system.iocache.overall_accesses::total 115662 # number of overall (read+write) accesses 2556system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2557system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2558system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2559system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2560system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2561system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 2562system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 2563system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2564system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2565system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2566system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2567system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2568system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2569system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140405.405405 # average ReadReq miss latency 2570system.iocache.ReadReq_avg_miss_latency::realview.ide 227373.002024 # average ReadReq miss latency 2571system.iocache.ReadReq_avg_miss_latency::total 227012.706304 # average ReadReq miss latency 2572system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2573system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2574system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125113.237276 # average WriteLineReq miss latency 2575system.iocache.WriteLineReq_avg_miss_latency::total 125113.237276 # average WriteLineReq miss latency 2576system.iocache.demand_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2577system.iocache.demand_avg_miss_latency::realview.ide 132979.373026 # average overall miss latency 2578system.iocache.demand_avg_miss_latency::total 132981.489755 # average overall miss latency 2579system.iocache.overall_avg_miss_latency::realview.ethernet 139100 # average overall miss latency 2580system.iocache.overall_avg_miss_latency::realview.ide 132979.373026 # average overall miss latency 2581system.iocache.overall_avg_miss_latency::total 132981.489755 # average overall miss latency 2582system.iocache.blocked_cycles::no_mshrs 51037 # number of cycles access was blocked 2583system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2584system.iocache.blocked::no_mshrs 3535 # number of cycles access was blocked 2585system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2586system.iocache.avg_blocked_cycles::no_mshrs 14.437624 # average number of cycles each access was blocked 2587system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2588system.iocache.writebacks::writebacks 106694 # number of writebacks 2589system.iocache.writebacks::total 106694 # number of writebacks 2590system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2591system.iocache.ReadReq_mshr_misses::realview.ide 8894 # number of ReadReq MSHR misses 2592system.iocache.ReadReq_mshr_misses::total 8931 # number of ReadReq MSHR misses 2593system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2594system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2595system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 2596system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 2597system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2598system.iocache.demand_mshr_misses::realview.ide 115622 # number of demand (read+write) MSHR misses 2599system.iocache.demand_mshr_misses::total 115662 # number of demand (read+write) MSHR misses 2600system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2601system.iocache.overall_mshr_misses::realview.ide 115622 # number of overall MSHR misses 2602system.iocache.overall_mshr_misses::total 115662 # number of overall MSHR misses 2603system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3345000 # number of ReadReq MSHR miss cycles 2604system.iocache.ReadReq_mshr_miss_latency::realview.ide 1577555480 # number of ReadReq MSHR miss cycles 2605system.iocache.ReadReq_mshr_miss_latency::total 1580900480 # number of ReadReq MSHR miss cycles 2606system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 2607system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 2608system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 8010840420 # number of WriteLineReq MSHR miss cycles 2609system.iocache.WriteLineReq_mshr_miss_latency::total 8010840420 # number of WriteLineReq MSHR miss cycles 2610system.iocache.demand_mshr_miss_latency::realview.ethernet 3564000 # number of demand (read+write) MSHR miss cycles 2611system.iocache.demand_mshr_miss_latency::realview.ide 9588395900 # number of demand (read+write) MSHR miss cycles 2612system.iocache.demand_mshr_miss_latency::total 9591959900 # number of demand (read+write) MSHR miss cycles 2613system.iocache.overall_mshr_miss_latency::realview.ethernet 3564000 # number of overall MSHR miss cycles 2614system.iocache.overall_mshr_miss_latency::realview.ide 9588395900 # number of overall MSHR miss cycles 2615system.iocache.overall_mshr_miss_latency::total 9591959900 # number of overall MSHR miss cycles 2616system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2617system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2618system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2619system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2620system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2621system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 2622system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 2623system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2624system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2625system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2626system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2627system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2628system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2629system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90405.405405 # average ReadReq mshr miss latency 2630system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 177373.002024 # average ReadReq mshr miss latency 2631system.iocache.ReadReq_avg_mshr_miss_latency::total 177012.706304 # average ReadReq mshr miss latency 2632system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 2633system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 2634system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75058.470317 # average WriteLineReq mshr miss latency 2635system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75058.470317 # average WriteLineReq mshr miss latency 2636system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2637system.iocache.demand_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency 2638system.iocache.demand_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency 2639system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89100 # average overall mshr miss latency 2640system.iocache.overall_avg_mshr_miss_latency::realview.ide 82928.818910 # average overall mshr miss latency 2641system.iocache.overall_avg_mshr_miss_latency::total 82930.953122 # average overall mshr miss latency 2642system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 2643system.l2c.tags.replacements 1289685 # number of replacements 2644system.l2c.tags.tagsinuse 65148.785380 # Cycle average of tags in use 2645system.l2c.tags.total_refs 5723107 # Total number of references to valid blocks. 2646system.l2c.tags.sampled_refs 1350729 # Sample count of references to valid blocks. 2647system.l2c.tags.avg_refs 4.237051 # Average number of references to valid blocks. 2648system.l2c.tags.warmup_cycle 6059472500 # Cycle when the warmup percentage was hit. 2649system.l2c.tags.occ_blocks::writebacks 12155.679811 # Average occupied blocks per requestor 2650system.l2c.tags.occ_blocks::cpu0.dtb.walker 124.426191 # Average occupied blocks per requestor 2651system.l2c.tags.occ_blocks::cpu0.itb.walker 138.926128 # Average occupied blocks per requestor 2652system.l2c.tags.occ_blocks::cpu0.inst 3396.773965 # Average occupied blocks per requestor 2653system.l2c.tags.occ_blocks::cpu0.data 12605.328956 # Average occupied blocks per requestor 2654system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 8503.765275 # Average occupied blocks per requestor 2655system.l2c.tags.occ_blocks::cpu1.dtb.walker 300.348884 # Average occupied blocks per requestor 2656system.l2c.tags.occ_blocks::cpu1.itb.walker 348.970492 # Average occupied blocks per requestor 2657system.l2c.tags.occ_blocks::cpu1.inst 3831.795073 # Average occupied blocks per requestor 2658system.l2c.tags.occ_blocks::cpu1.data 12139.257493 # Average occupied blocks per requestor 2659system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11603.513111 # Average occupied blocks per requestor 2660system.l2c.tags.occ_percent::writebacks 0.185481 # Average percentage of cache occupancy 2661system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001899 # Average percentage of cache occupancy 2662system.l2c.tags.occ_percent::cpu0.itb.walker 0.002120 # Average percentage of cache occupancy 2663system.l2c.tags.occ_percent::cpu0.inst 0.051831 # Average percentage of cache occupancy 2664system.l2c.tags.occ_percent::cpu0.data 0.192342 # Average percentage of cache occupancy 2665system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.129757 # Average percentage of cache occupancy 2666system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004583 # Average percentage of cache occupancy 2667system.l2c.tags.occ_percent::cpu1.itb.walker 0.005325 # Average percentage of cache occupancy 2668system.l2c.tags.occ_percent::cpu1.inst 0.058469 # Average percentage of cache occupancy 2669system.l2c.tags.occ_percent::cpu1.data 0.185230 # Average percentage of cache occupancy 2670system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.177056 # Average percentage of cache occupancy 2671system.l2c.tags.occ_percent::total 0.994092 # Average percentage of cache occupancy 2672system.l2c.tags.occ_task_id_blocks::1022 12163 # Occupied blocks per task id 2673system.l2c.tags.occ_task_id_blocks::1023 299 # Occupied blocks per task id 2674system.l2c.tags.occ_task_id_blocks::1024 48582 # Occupied blocks per task id 2675system.l2c.tags.age_task_id_blocks_1022::2 174 # Occupied blocks per task id 2676system.l2c.tags.age_task_id_blocks_1022::3 318 # Occupied blocks per task id 2677system.l2c.tags.age_task_id_blocks_1022::4 11671 # Occupied blocks per task id 2678system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id 2679system.l2c.tags.age_task_id_blocks_1023::4 297 # Occupied blocks per task id 2680system.l2c.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 2681system.l2c.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 2682system.l2c.tags.age_task_id_blocks_1024::2 1173 # Occupied blocks per task id 2683system.l2c.tags.age_task_id_blocks_1024::3 4557 # Occupied blocks per task id 2684system.l2c.tags.age_task_id_blocks_1024::4 42755 # Occupied blocks per task id 2685system.l2c.tags.occ_task_id_percent::1022 0.185593 # Percentage of cache occupancy per task id 2686system.l2c.tags.occ_task_id_percent::1023 0.004562 # Percentage of cache occupancy per task id 2687system.l2c.tags.occ_task_id_percent::1024 0.741302 # Percentage of cache occupancy per task id 2688system.l2c.tags.tag_accesses 65194650 # Number of tag accesses 2689system.l2c.tags.data_accesses 65194650 # Number of data accesses 2690system.l2c.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 2691system.l2c.WritebackDirty_hits::writebacks 2495189 # number of WritebackDirty hits 2692system.l2c.WritebackDirty_hits::total 2495189 # number of WritebackDirty hits 2693system.l2c.UpgradeReq_hits::cpu0.data 165997 # number of UpgradeReq hits 2694system.l2c.UpgradeReq_hits::cpu1.data 157094 # number of UpgradeReq hits 2695system.l2c.UpgradeReq_hits::total 323091 # number of UpgradeReq hits 2696system.l2c.SCUpgradeReq_hits::cpu0.data 44921 # number of SCUpgradeReq hits 2697system.l2c.SCUpgradeReq_hits::cpu1.data 51888 # number of SCUpgradeReq hits 2698system.l2c.SCUpgradeReq_hits::total 96809 # number of SCUpgradeReq hits 2699system.l2c.ReadExReq_hits::cpu0.data 41742 # number of ReadExReq hits 2700system.l2c.ReadExReq_hits::cpu1.data 58696 # number of ReadExReq hits 2701system.l2c.ReadExReq_hits::total 100438 # number of ReadExReq hits 2702system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 7485 # number of ReadSharedReq hits 2703system.l2c.ReadSharedReq_hits::cpu0.itb.walker 3707 # number of ReadSharedReq hits 2704system.l2c.ReadSharedReq_hits::cpu0.inst 366128 # number of ReadSharedReq hits 2705system.l2c.ReadSharedReq_hits::cpu0.data 471159 # number of ReadSharedReq hits 2706system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 250331 # number of ReadSharedReq hits 2707system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 11134 # number of ReadSharedReq hits 2708system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5196 # number of ReadSharedReq hits 2709system.l2c.ReadSharedReq_hits::cpu1.inst 423879 # number of ReadSharedReq hits 2710system.l2c.ReadSharedReq_hits::cpu1.data 535784 # number of ReadSharedReq hits 2711system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 283571 # number of ReadSharedReq hits 2712system.l2c.ReadSharedReq_hits::total 2358374 # number of ReadSharedReq hits 2713system.l2c.InvalidateReq_hits::cpu0.data 108961 # number of InvalidateReq hits 2714system.l2c.InvalidateReq_hits::cpu1.data 126093 # number of InvalidateReq hits 2715system.l2c.InvalidateReq_hits::total 235054 # number of InvalidateReq hits 2716system.l2c.demand_hits::cpu0.dtb.walker 7485 # number of demand (read+write) hits 2717system.l2c.demand_hits::cpu0.itb.walker 3707 # number of demand (read+write) hits 2718system.l2c.demand_hits::cpu0.inst 366128 # number of demand (read+write) hits 2719system.l2c.demand_hits::cpu0.data 512901 # number of demand (read+write) hits 2720system.l2c.demand_hits::cpu0.l2cache.prefetcher 250331 # number of demand (read+write) hits 2721system.l2c.demand_hits::cpu1.dtb.walker 11134 # number of demand (read+write) hits 2722system.l2c.demand_hits::cpu1.itb.walker 5196 # number of demand (read+write) hits 2723system.l2c.demand_hits::cpu1.inst 423879 # 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number of overall hits 2737system.l2c.overall_hits::total 2458812 # number of overall hits 2738system.l2c.UpgradeReq_misses::cpu0.data 21704 # number of UpgradeReq misses 2739system.l2c.UpgradeReq_misses::cpu1.data 22525 # number of UpgradeReq misses 2740system.l2c.UpgradeReq_misses::total 44229 # number of UpgradeReq misses 2741system.l2c.SCUpgradeReq_misses::cpu0.data 639 # number of SCUpgradeReq misses 2742system.l2c.SCUpgradeReq_misses::cpu1.data 868 # number of SCUpgradeReq misses 2743system.l2c.SCUpgradeReq_misses::total 1507 # number of SCUpgradeReq misses 2744system.l2c.ReadExReq_misses::cpu0.data 68872 # number of ReadExReq misses 2745system.l2c.ReadExReq_misses::cpu1.data 49716 # number of ReadExReq misses 2746system.l2c.ReadExReq_misses::total 118588 # number of ReadExReq misses 2747system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 981 # number of ReadSharedReq misses 2748system.l2c.ReadSharedReq_misses::cpu0.itb.walker 934 # number of ReadSharedReq misses 2749system.l2c.ReadSharedReq_misses::cpu0.inst 45283 # number of ReadSharedReq misses 2750system.l2c.ReadSharedReq_misses::cpu0.data 111817 # number of ReadSharedReq misses 2751system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 200821 # number of ReadSharedReq misses 2752system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 1691 # number of ReadSharedReq misses 2753system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1806 # number of ReadSharedReq misses 2754system.l2c.ReadSharedReq_misses::cpu1.inst 46161 # number of ReadSharedReq misses 2755system.l2c.ReadSharedReq_misses::cpu1.data 105560 # number of ReadSharedReq misses 2756system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 172390 # number of ReadSharedReq misses 2757system.l2c.ReadSharedReq_misses::total 687444 # number of ReadSharedReq misses 2758system.l2c.InvalidateReq_misses::cpu0.data 412236 # number of InvalidateReq misses 2759system.l2c.InvalidateReq_misses::cpu1.data 90358 # number of InvalidateReq misses 2760system.l2c.InvalidateReq_misses::total 502594 # number of InvalidateReq misses 2761system.l2c.demand_misses::cpu0.dtb.walker 981 # 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number of overall misses 2774system.l2c.overall_misses::cpu0.inst 45283 # number of overall misses 2775system.l2c.overall_misses::cpu0.data 180689 # number of overall misses 2776system.l2c.overall_misses::cpu0.l2cache.prefetcher 200821 # number of overall misses 2777system.l2c.overall_misses::cpu1.dtb.walker 1691 # number of overall misses 2778system.l2c.overall_misses::cpu1.itb.walker 1806 # number of overall misses 2779system.l2c.overall_misses::cpu1.inst 46161 # number of overall misses 2780system.l2c.overall_misses::cpu1.data 155276 # number of overall misses 2781system.l2c.overall_misses::cpu1.l2cache.prefetcher 172390 # number of overall misses 2782system.l2c.overall_misses::total 806032 # number of overall misses 2783system.l2c.UpgradeReq_miss_latency::cpu0.data 123357500 # number of UpgradeReq miss cycles 2784system.l2c.UpgradeReq_miss_latency::cpu1.data 137680500 # number of UpgradeReq miss cycles 2785system.l2c.UpgradeReq_miss_latency::total 261038000 # number of UpgradeReq miss cycles 2786system.l2c.SCUpgradeReq_miss_latency::cpu0.data 7905500 # number of SCUpgradeReq miss cycles 2787system.l2c.SCUpgradeReq_miss_latency::cpu1.data 10002000 # number of SCUpgradeReq miss cycles 2788system.l2c.SCUpgradeReq_miss_latency::total 17907500 # number of SCUpgradeReq miss cycles 2789system.l2c.ReadExReq_miss_latency::cpu0.data 7461780500 # number of ReadExReq miss cycles 2790system.l2c.ReadExReq_miss_latency::cpu1.data 5660273500 # number of ReadExReq miss cycles 2791system.l2c.ReadExReq_miss_latency::total 13122054000 # number of ReadExReq miss cycles 2792system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 100552000 # number of ReadSharedReq miss cycles 2793system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 104158000 # number of ReadSharedReq miss cycles 2794system.l2c.ReadSharedReq_miss_latency::cpu0.inst 5195669500 # number of ReadSharedReq miss cycles 2795system.l2c.ReadSharedReq_miss_latency::cpu0.data 12454113000 # number of ReadSharedReq miss cycles 2796system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of ReadSharedReq miss cycles 2797system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 176942500 # number of ReadSharedReq miss cycles 2798system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 186194000 # number of ReadSharedReq miss cycles 2799system.l2c.ReadSharedReq_miss_latency::cpu1.inst 5476488000 # number of ReadSharedReq miss cycles 2800system.l2c.ReadSharedReq_miss_latency::cpu1.data 12376112000 # number of ReadSharedReq miss cycles 2801system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of ReadSharedReq miss cycles 2802system.l2c.ReadSharedReq_miss_latency::total 86331961414 # number of ReadSharedReq miss cycles 2803system.l2c.demand_miss_latency::cpu0.dtb.walker 100552000 # number of demand (read+write) miss cycles 2804system.l2c.demand_miss_latency::cpu0.itb.walker 104158000 # number of demand (read+write) miss cycles 2805system.l2c.demand_miss_latency::cpu0.inst 5195669500 # number of demand (read+write) miss cycles 2806system.l2c.demand_miss_latency::cpu0.data 19915893500 # number of demand (read+write) miss cycles 2807system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of demand (read+write) miss cycles 2808system.l2c.demand_miss_latency::cpu1.dtb.walker 176942500 # number of demand (read+write) miss cycles 2809system.l2c.demand_miss_latency::cpu1.itb.walker 186194000 # number of demand (read+write) miss cycles 2810system.l2c.demand_miss_latency::cpu1.inst 5476488000 # number of demand (read+write) miss cycles 2811system.l2c.demand_miss_latency::cpu1.data 18036385500 # number of demand (read+write) miss cycles 2812system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of demand (read+write) miss cycles 2813system.l2c.demand_miss_latency::total 99454015414 # number of demand (read+write) miss cycles 2814system.l2c.overall_miss_latency::cpu0.dtb.walker 100552000 # number of overall miss cycles 2815system.l2c.overall_miss_latency::cpu0.itb.walker 104158000 # number of overall miss cycles 2816system.l2c.overall_miss_latency::cpu0.inst 5195669500 # number of overall miss cycles 2817system.l2c.overall_miss_latency::cpu0.data 19915893500 # number of overall miss cycles 2818system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27350729041 # number of overall miss cycles 2819system.l2c.overall_miss_latency::cpu1.dtb.walker 176942500 # number of overall miss cycles 2820system.l2c.overall_miss_latency::cpu1.itb.walker 186194000 # number of overall miss cycles 2821system.l2c.overall_miss_latency::cpu1.inst 5476488000 # number of overall miss cycles 2822system.l2c.overall_miss_latency::cpu1.data 18036385500 # number of overall miss cycles 2823system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 22911003373 # number of overall miss cycles 2824system.l2c.overall_miss_latency::total 99454015414 # number of overall miss cycles 2825system.l2c.WritebackDirty_accesses::writebacks 2495189 # number of WritebackDirty accesses(hits+misses) 2826system.l2c.WritebackDirty_accesses::total 2495189 # number of WritebackDirty accesses(hits+misses) 2827system.l2c.UpgradeReq_accesses::cpu0.data 187701 # number of UpgradeReq accesses(hits+misses) 2828system.l2c.UpgradeReq_accesses::cpu1.data 179619 # number of UpgradeReq accesses(hits+misses) 2829system.l2c.UpgradeReq_accesses::total 367320 # number of UpgradeReq accesses(hits+misses) 2830system.l2c.SCUpgradeReq_accesses::cpu0.data 45560 # number of SCUpgradeReq accesses(hits+misses) 2831system.l2c.SCUpgradeReq_accesses::cpu1.data 52756 # number of SCUpgradeReq accesses(hits+misses) 2832system.l2c.SCUpgradeReq_accesses::total 98316 # number of SCUpgradeReq accesses(hits+misses) 2833system.l2c.ReadExReq_accesses::cpu0.data 110614 # number of ReadExReq accesses(hits+misses) 2834system.l2c.ReadExReq_accesses::cpu1.data 108412 # number of ReadExReq accesses(hits+misses) 2835system.l2c.ReadExReq_accesses::total 219026 # number of ReadExReq accesses(hits+misses) 2836system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 8466 # number of ReadSharedReq accesses(hits+misses) 2837system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 4641 # number of ReadSharedReq accesses(hits+misses) 2838system.l2c.ReadSharedReq_accesses::cpu0.inst 411411 # number of ReadSharedReq accesses(hits+misses) 2839system.l2c.ReadSharedReq_accesses::cpu0.data 582976 # number of ReadSharedReq accesses(hits+misses) 2840system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 451152 # number of ReadSharedReq accesses(hits+misses) 2841system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 12825 # number of ReadSharedReq accesses(hits+misses) 2842system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 7002 # number of ReadSharedReq accesses(hits+misses) 2843system.l2c.ReadSharedReq_accesses::cpu1.inst 470040 # number of ReadSharedReq accesses(hits+misses) 2844system.l2c.ReadSharedReq_accesses::cpu1.data 641344 # number of ReadSharedReq accesses(hits+misses) 2845system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 455961 # number of ReadSharedReq accesses(hits+misses) 2846system.l2c.ReadSharedReq_accesses::total 3045818 # number of ReadSharedReq accesses(hits+misses) 2847system.l2c.InvalidateReq_accesses::cpu0.data 521197 # number of InvalidateReq accesses(hits+misses) 2848system.l2c.InvalidateReq_accesses::cpu1.data 216451 # number of InvalidateReq accesses(hits+misses) 2849system.l2c.InvalidateReq_accesses::total 737648 # number of InvalidateReq accesses(hits+misses) 2850system.l2c.demand_accesses::cpu0.dtb.walker 8466 # number of demand (read+write) accesses 2851system.l2c.demand_accesses::cpu0.itb.walker 4641 # number of demand (read+write) accesses 2852system.l2c.demand_accesses::cpu0.inst 411411 # number of demand (read+write) accesses 2853system.l2c.demand_accesses::cpu0.data 693590 # number of demand (read+write) accesses 2854system.l2c.demand_accesses::cpu0.l2cache.prefetcher 451152 # number of demand (read+write) accesses 2855system.l2c.demand_accesses::cpu1.dtb.walker 12825 # number of demand (read+write) accesses 2856system.l2c.demand_accesses::cpu1.itb.walker 7002 # number of demand (read+write) accesses 2857system.l2c.demand_accesses::cpu1.inst 470040 # number of demand (read+write) accesses 2858system.l2c.demand_accesses::cpu1.data 749756 # number of demand (read+write) accesses 2859system.l2c.demand_accesses::cpu1.l2cache.prefetcher 455961 # number of demand (read+write) accesses 2860system.l2c.demand_accesses::total 3264844 # number of demand (read+write) accesses 2861system.l2c.overall_accesses::cpu0.dtb.walker 8466 # number of overall (read+write) accesses 2862system.l2c.overall_accesses::cpu0.itb.walker 4641 # number of overall (read+write) accesses 2863system.l2c.overall_accesses::cpu0.inst 411411 # number of overall (read+write) accesses 2864system.l2c.overall_accesses::cpu0.data 693590 # number of overall (read+write) accesses 2865system.l2c.overall_accesses::cpu0.l2cache.prefetcher 451152 # number of overall (read+write) accesses 2866system.l2c.overall_accesses::cpu1.dtb.walker 12825 # number of overall (read+write) accesses 2867system.l2c.overall_accesses::cpu1.itb.walker 7002 # number of overall (read+write) accesses 2868system.l2c.overall_accesses::cpu1.inst 470040 # number of overall (read+write) accesses 2869system.l2c.overall_accesses::cpu1.data 749756 # number of overall (read+write) accesses 2870system.l2c.overall_accesses::cpu1.l2cache.prefetcher 455961 # number of overall (read+write) accesses 2871system.l2c.overall_accesses::total 3264844 # number of overall (read+write) accesses 2872system.l2c.UpgradeReq_miss_rate::cpu0.data 0.115631 # miss rate for UpgradeReq accesses 2873system.l2c.UpgradeReq_miss_rate::cpu1.data 0.125404 # miss rate for UpgradeReq accesses 2874system.l2c.UpgradeReq_miss_rate::total 0.120410 # miss rate for UpgradeReq accesses 2875system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.014025 # miss rate for SCUpgradeReq accesses 2876system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016453 # miss rate for SCUpgradeReq accesses 2877system.l2c.SCUpgradeReq_miss_rate::total 0.015328 # miss rate for SCUpgradeReq accesses 2878system.l2c.ReadExReq_miss_rate::cpu0.data 0.622634 # miss rate for ReadExReq accesses 2879system.l2c.ReadExReq_miss_rate::cpu1.data 0.458584 # miss rate for ReadExReq accesses 2880system.l2c.ReadExReq_miss_rate::total 0.541433 # miss rate for ReadExReq accesses 2881system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for ReadSharedReq accesses 2882system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.201250 # miss rate for ReadSharedReq accesses 2883system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.110068 # miss rate for ReadSharedReq accesses 2884system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.191804 # miss rate for ReadSharedReq accesses 2885system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for ReadSharedReq accesses 2886system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for ReadSharedReq accesses 2887system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.257926 # miss rate for ReadSharedReq accesses 2888system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.098207 # miss rate for ReadSharedReq accesses 2889system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.164592 # miss rate for ReadSharedReq accesses 2890system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for ReadSharedReq accesses 2891system.l2c.ReadSharedReq_miss_rate::total 0.225701 # miss rate for ReadSharedReq accesses 2892system.l2c.InvalidateReq_miss_rate::cpu0.data 0.790941 # miss rate for InvalidateReq accesses 2893system.l2c.InvalidateReq_miss_rate::cpu1.data 0.417452 # miss rate for InvalidateReq accesses 2894system.l2c.InvalidateReq_miss_rate::total 0.681347 # miss rate for InvalidateReq accesses 2895system.l2c.demand_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for demand accesses 2896system.l2c.demand_miss_rate::cpu0.itb.walker 0.201250 # miss rate for demand accesses 2897system.l2c.demand_miss_rate::cpu0.inst 0.110068 # miss rate for demand accesses 2898system.l2c.demand_miss_rate::cpu0.data 0.260513 # miss rate for demand accesses 2899system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for demand accesses 2900system.l2c.demand_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for demand accesses 2901system.l2c.demand_miss_rate::cpu1.itb.walker 0.257926 # miss rate for demand accesses 2902system.l2c.demand_miss_rate::cpu1.inst 0.098207 # miss rate for demand accesses 2903system.l2c.demand_miss_rate::cpu1.data 0.207102 # miss rate for demand accesses 2904system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for demand accesses 2905system.l2c.demand_miss_rate::total 0.246882 # miss rate for demand accesses 2906system.l2c.overall_miss_rate::cpu0.dtb.walker 0.115875 # miss rate for overall accesses 2907system.l2c.overall_miss_rate::cpu0.itb.walker 0.201250 # miss rate for overall accesses 2908system.l2c.overall_miss_rate::cpu0.inst 0.110068 # miss rate for overall accesses 2909system.l2c.overall_miss_rate::cpu0.data 0.260513 # miss rate for overall accesses 2910system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.445129 # miss rate for overall accesses 2911system.l2c.overall_miss_rate::cpu1.dtb.walker 0.131852 # miss rate for overall accesses 2912system.l2c.overall_miss_rate::cpu1.itb.walker 0.257926 # miss rate for overall accesses 2913system.l2c.overall_miss_rate::cpu1.inst 0.098207 # miss rate for overall accesses 2914system.l2c.overall_miss_rate::cpu1.data 0.207102 # miss rate for overall accesses 2915system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.378081 # miss rate for overall accesses 2916system.l2c.overall_miss_rate::total 0.246882 # miss rate for overall accesses 2917system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5683.629746 # average UpgradeReq miss latency 2918system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6112.341842 # average UpgradeReq miss latency 2919system.l2c.UpgradeReq_avg_miss_latency::total 5901.964774 # average UpgradeReq miss latency 2920system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 12371.674491 # average SCUpgradeReq miss latency 2921system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11523.041475 # average SCUpgradeReq miss latency 2922system.l2c.SCUpgradeReq_avg_miss_latency::total 11882.879894 # average SCUpgradeReq miss latency 2923system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108342.729992 # average ReadExReq miss latency 2924system.l2c.ReadExReq_avg_miss_latency::cpu1.data 113852.150213 # average ReadExReq miss latency 2925system.l2c.ReadExReq_avg_miss_latency::total 110652.460620 # average ReadExReq miss latency 2926system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 102499.490316 # average ReadSharedReq miss latency 2927system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 111518.201285 # average ReadSharedReq miss latency 2928system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 114737.749266 # average ReadSharedReq miss latency 2929system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111379.423522 # average ReadSharedReq miss latency 2930system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 136194.566509 # average ReadSharedReq miss latency 2931system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 104637.788291 # average ReadSharedReq miss latency 2932system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103097.452935 # average ReadSharedReq miss latency 2933system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 118638.850978 # average ReadSharedReq miss latency 2934system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 117242.440318 # average ReadSharedReq miss latency 2935system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average ReadSharedReq miss latency 2936system.l2c.ReadSharedReq_avg_miss_latency::total 125583.991444 # average ReadSharedReq miss latency 2937system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 102499.490316 # average overall miss latency 2938system.l2c.demand_avg_miss_latency::cpu0.itb.walker 111518.201285 # average overall miss latency 2939system.l2c.demand_avg_miss_latency::cpu0.inst 114737.749266 # average overall miss latency 2940system.l2c.demand_avg_miss_latency::cpu0.data 110221.947656 # average overall miss latency 2941system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 136194.566509 # average overall miss latency 2942system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 104637.788291 # average overall miss latency 2943system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103097.452935 # average overall miss latency 2944system.l2c.demand_avg_miss_latency::cpu1.inst 118638.850978 # average overall miss latency 2945system.l2c.demand_avg_miss_latency::cpu1.data 116156.943121 # average overall miss latency 2946system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average overall miss latency 2947system.l2c.demand_avg_miss_latency::total 123387.179931 # average overall miss latency 2948system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 102499.490316 # average overall miss latency 2949system.l2c.overall_avg_miss_latency::cpu0.itb.walker 111518.201285 # average overall miss latency 2950system.l2c.overall_avg_miss_latency::cpu0.inst 114737.749266 # average overall miss latency 2951system.l2c.overall_avg_miss_latency::cpu0.data 110221.947656 # average overall miss latency 2952system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 136194.566509 # average overall miss latency 2953system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 104637.788291 # average overall miss latency 2954system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103097.452935 # average overall miss latency 2955system.l2c.overall_avg_miss_latency::cpu1.inst 118638.850978 # average overall miss latency 2956system.l2c.overall_avg_miss_latency::cpu1.data 116156.943121 # average overall miss latency 2957system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132902.160061 # average overall miss latency 2958system.l2c.overall_avg_miss_latency::total 123387.179931 # average overall miss latency 2959system.l2c.blocked_cycles::no_mshrs 70 # number of cycles access was blocked 2960system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2961system.l2c.blocked::no_mshrs 3 # number of cycles access was blocked 2962system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2963system.l2c.avg_blocked_cycles::no_mshrs 23.333333 # average number of cycles each access was blocked 2964system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2965system.l2c.writebacks::writebacks 1000492 # number of writebacks 2966system.l2c.writebacks::total 1000492 # number of writebacks 2967system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 125 # number of ReadSharedReq MSHR hits 2968system.l2c.ReadSharedReq_mshr_hits::cpu0.data 495 # number of ReadSharedReq MSHR hits 2969system.l2c.ReadSharedReq_mshr_hits::cpu0.l2cache.prefetcher 3 # number of ReadSharedReq MSHR hits 2970system.l2c.ReadSharedReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadSharedReq MSHR hits 2971system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 176 # number of ReadSharedReq MSHR hits 2972system.l2c.ReadSharedReq_mshr_hits::cpu1.data 174 # number of ReadSharedReq MSHR hits 2973system.l2c.ReadSharedReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadSharedReq MSHR hits 2974system.l2c.ReadSharedReq_mshr_hits::total 975 # number of ReadSharedReq MSHR hits 2975system.l2c.demand_mshr_hits::cpu0.inst 125 # number of demand (read+write) MSHR hits 2976system.l2c.demand_mshr_hits::cpu0.data 495 # number of demand (read+write) MSHR hits 2977system.l2c.demand_mshr_hits::cpu0.l2cache.prefetcher 3 # number of demand (read+write) MSHR hits 2978system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2979system.l2c.demand_mshr_hits::cpu1.inst 176 # number of demand (read+write) MSHR hits 2980system.l2c.demand_mshr_hits::cpu1.data 174 # number of demand (read+write) MSHR hits 2981system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits 2982system.l2c.demand_mshr_hits::total 975 # number of demand (read+write) MSHR hits 2983system.l2c.overall_mshr_hits::cpu0.inst 125 # number of overall MSHR hits 2984system.l2c.overall_mshr_hits::cpu0.data 495 # number of overall MSHR hits 2985system.l2c.overall_mshr_hits::cpu0.l2cache.prefetcher 3 # number of overall MSHR hits 2986system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2987system.l2c.overall_mshr_hits::cpu1.inst 176 # number of overall MSHR hits 2988system.l2c.overall_mshr_hits::cpu1.data 174 # number of overall MSHR hits 2989system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits 2990system.l2c.overall_mshr_hits::total 975 # number of overall MSHR hits 2991system.l2c.CleanEvict_mshr_misses::writebacks 48951 # number of CleanEvict MSHR misses 2992system.l2c.CleanEvict_mshr_misses::total 48951 # number of CleanEvict MSHR misses 2993system.l2c.UpgradeReq_mshr_misses::cpu0.data 21704 # number of UpgradeReq MSHR misses 2994system.l2c.UpgradeReq_mshr_misses::cpu1.data 22525 # number of UpgradeReq MSHR misses 2995system.l2c.UpgradeReq_mshr_misses::total 44229 # number of UpgradeReq MSHR misses 2996system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 639 # number of SCUpgradeReq MSHR misses 2997system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 868 # number of SCUpgradeReq MSHR misses 2998system.l2c.SCUpgradeReq_mshr_misses::total 1507 # number of SCUpgradeReq MSHR misses 2999system.l2c.ReadExReq_mshr_misses::cpu0.data 68872 # number of ReadExReq MSHR misses 3000system.l2c.ReadExReq_mshr_misses::cpu1.data 49716 # number of ReadExReq MSHR misses 3001system.l2c.ReadExReq_mshr_misses::total 118588 # number of ReadExReq MSHR misses 3002system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 981 # number of ReadSharedReq MSHR misses 3003system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 934 # number of ReadSharedReq MSHR misses 3004system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 45158 # number of ReadSharedReq MSHR misses 3005system.l2c.ReadSharedReq_mshr_misses::cpu0.data 111322 # number of ReadSharedReq MSHR misses 3006system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of ReadSharedReq MSHR misses 3007system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 1690 # number of ReadSharedReq MSHR misses 3008system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1806 # number of ReadSharedReq MSHR misses 3009system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 45985 # number of ReadSharedReq MSHR misses 3010system.l2c.ReadSharedReq_mshr_misses::cpu1.data 105386 # number of ReadSharedReq MSHR misses 3011system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of ReadSharedReq MSHR misses 3012system.l2c.ReadSharedReq_mshr_misses::total 686469 # number of ReadSharedReq MSHR misses 3013system.l2c.InvalidateReq_mshr_misses::cpu0.data 412236 # number of InvalidateReq MSHR misses 3014system.l2c.InvalidateReq_mshr_misses::cpu1.data 90358 # number of InvalidateReq MSHR misses 3015system.l2c.InvalidateReq_mshr_misses::total 502594 # number of InvalidateReq MSHR misses 3016system.l2c.demand_mshr_misses::cpu0.dtb.walker 981 # number of demand (read+write) MSHR misses 3017system.l2c.demand_mshr_misses::cpu0.itb.walker 934 # number of demand (read+write) MSHR misses 3018system.l2c.demand_mshr_misses::cpu0.inst 45158 # number of demand (read+write) MSHR misses 3019system.l2c.demand_mshr_misses::cpu0.data 180194 # number of demand (read+write) MSHR misses 3020system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of demand (read+write) MSHR misses 3021system.l2c.demand_mshr_misses::cpu1.dtb.walker 1690 # number of demand (read+write) MSHR misses 3022system.l2c.demand_mshr_misses::cpu1.itb.walker 1806 # number of demand (read+write) MSHR misses 3023system.l2c.demand_mshr_misses::cpu1.inst 45985 # number of demand (read+write) MSHR misses 3024system.l2c.demand_mshr_misses::cpu1.data 155102 # number of demand (read+write) MSHR misses 3025system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of demand (read+write) MSHR misses 3026system.l2c.demand_mshr_misses::total 805057 # number of demand (read+write) MSHR misses 3027system.l2c.overall_mshr_misses::cpu0.dtb.walker 981 # number of overall MSHR misses 3028system.l2c.overall_mshr_misses::cpu0.itb.walker 934 # number of overall MSHR misses 3029system.l2c.overall_mshr_misses::cpu0.inst 45158 # number of overall MSHR misses 3030system.l2c.overall_mshr_misses::cpu0.data 180194 # number of overall MSHR misses 3031system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 200818 # number of overall MSHR misses 3032system.l2c.overall_mshr_misses::cpu1.dtb.walker 1690 # number of overall MSHR misses 3033system.l2c.overall_mshr_misses::cpu1.itb.walker 1806 # number of overall MSHR misses 3034system.l2c.overall_mshr_misses::cpu1.inst 45985 # number of overall MSHR misses 3035system.l2c.overall_mshr_misses::cpu1.data 155102 # number of overall MSHR misses 3036system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 172389 # number of overall MSHR misses 3037system.l2c.overall_mshr_misses::total 805057 # number of overall MSHR misses 3038system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 4725 # number of ReadReq MSHR uncacheable 3039system.l2c.ReadReq_mshr_uncacheable::cpu0.data 15891 # number of ReadReq MSHR uncacheable 3040system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 3041system.l2c.ReadReq_mshr_uncacheable::cpu1.data 22370 # number of ReadReq MSHR uncacheable 3042system.l2c.ReadReq_mshr_uncacheable::total 43096 # number of ReadReq MSHR uncacheable 3043system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16800 # number of WriteReq MSHR uncacheable 3044system.l2c.WriteReq_mshr_uncacheable::cpu1.data 21343 # number of WriteReq MSHR uncacheable 3045system.l2c.WriteReq_mshr_uncacheable::total 38143 # number of WriteReq MSHR uncacheable 3046system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 4725 # number of overall MSHR uncacheable misses 3047system.l2c.overall_mshr_uncacheable_misses::cpu0.data 32691 # number of overall MSHR uncacheable misses 3048system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 3049system.l2c.overall_mshr_uncacheable_misses::cpu1.data 43713 # number of overall MSHR uncacheable misses 3050system.l2c.overall_mshr_uncacheable_misses::total 81239 # number of overall MSHR uncacheable misses 3051system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 437084000 # number of UpgradeReq MSHR miss cycles 3052system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 466716500 # number of UpgradeReq MSHR miss cycles 3053system.l2c.UpgradeReq_mshr_miss_latency::total 903800500 # number of UpgradeReq MSHR miss cycles 3054system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15328000 # number of SCUpgradeReq MSHR miss cycles 3055system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 21488000 # number of SCUpgradeReq MSHR miss cycles 3056system.l2c.SCUpgradeReq_mshr_miss_latency::total 36816000 # number of SCUpgradeReq MSHR miss cycles 3057system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6773036549 # number of ReadExReq MSHR miss cycles 3058system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 5163079069 # number of ReadExReq MSHR miss cycles 3059system.l2c.ReadExReq_mshr_miss_latency::total 11936115618 # number of ReadExReq MSHR miss cycles 3060system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 90742000 # number of ReadSharedReq MSHR miss cycles 3061system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 94817501 # number of ReadSharedReq MSHR miss cycles 3062system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 4733313024 # number of ReadSharedReq MSHR miss cycles 3063system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 11297480109 # number of ReadSharedReq MSHR miss cycles 3064system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25342213838 # number of ReadSharedReq MSHR miss cycles 3065system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 159957502 # number of ReadSharedReq MSHR miss cycles 3066system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 168133501 # number of ReadSharedReq MSHR miss cycles 3067system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5000535031 # number of ReadSharedReq MSHR miss cycles 3068system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 11306213655 # number of ReadSharedReq MSHR miss cycles 3069system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 21186861799 # number of ReadSharedReq MSHR miss cycles 3070system.l2c.ReadSharedReq_mshr_miss_latency::total 79380267960 # number of ReadSharedReq MSHR miss cycles 3071system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 8132910000 # number of InvalidateReq MSHR miss cycles 3072system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1724009500 # number of InvalidateReq MSHR miss cycles 3073system.l2c.InvalidateReq_mshr_miss_latency::total 9856919500 # number of InvalidateReq MSHR miss cycles 3074system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 90742000 # number of demand (read+write) MSHR miss cycles 3075system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 94817501 # number of demand (read+write) MSHR miss cycles 3076system.l2c.demand_mshr_miss_latency::cpu0.inst 4733313024 # number of demand (read+write) MSHR miss cycles 3077system.l2c.demand_mshr_miss_latency::cpu0.data 18070516658 # number of demand (read+write) MSHR miss cycles 3078system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 25342213838 # number of demand (read+write) MSHR miss cycles 3079system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 159957502 # number of demand (read+write) MSHR miss cycles 3080system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 168133501 # number of demand (read+write) MSHR miss cycles 3081system.l2c.demand_mshr_miss_latency::cpu1.inst 5000535031 # number of demand (read+write) MSHR miss cycles 3082system.l2c.demand_mshr_miss_latency::cpu1.data 16469292724 # number of demand (read+write) MSHR miss cycles 3083system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 21186861799 # number of demand (read+write) MSHR miss cycles 3084system.l2c.demand_mshr_miss_latency::total 91316383578 # number of demand (read+write) MSHR miss cycles 3085system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 90742000 # number of overall MSHR miss cycles 3086system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 94817501 # number of overall MSHR miss cycles 3087system.l2c.overall_mshr_miss_latency::cpu0.inst 4733313024 # number of overall MSHR miss cycles 3088system.l2c.overall_mshr_miss_latency::cpu0.data 18070516658 # number of overall MSHR miss cycles 3089system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25342213838 # number of overall MSHR miss cycles 3090system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 159957502 # number of overall MSHR miss cycles 3091system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 168133501 # number of overall MSHR miss cycles 3092system.l2c.overall_mshr_miss_latency::cpu1.inst 5000535031 # number of overall MSHR miss cycles 3093system.l2c.overall_mshr_miss_latency::cpu1.data 16469292724 # number of overall MSHR miss cycles 3094system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 21186861799 # number of overall MSHR miss cycles 3095system.l2c.overall_mshr_miss_latency::total 91316383578 # number of overall MSHR miss cycles 3096system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 343198000 # number of ReadReq MSHR uncacheable cycles 3097system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2516105003 # number of ReadReq MSHR uncacheable cycles 3098system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7788000 # number of ReadReq MSHR uncacheable cycles 3099system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3411021500 # number of ReadReq MSHR uncacheable cycles 3100system.l2c.ReadReq_mshr_uncacheable_latency::total 6278112503 # number of ReadReq MSHR uncacheable cycles 3101system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 343198000 # number of overall MSHR uncacheable cycles 3102system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2516105003 # number of overall MSHR uncacheable cycles 3103system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7788000 # number of overall MSHR uncacheable cycles 3104system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3411021500 # number of overall MSHR uncacheable cycles 3105system.l2c.overall_mshr_uncacheable_latency::total 6278112503 # number of overall MSHR uncacheable cycles 3106system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3107system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3108system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.115631 # mshr miss rate for UpgradeReq accesses 3109system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.125404 # mshr miss rate for UpgradeReq accesses 3110system.l2c.UpgradeReq_mshr_miss_rate::total 0.120410 # mshr miss rate for UpgradeReq accesses 3111system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.014025 # mshr miss rate for SCUpgradeReq accesses 3112system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016453 # mshr miss rate for SCUpgradeReq accesses 3113system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.015328 # mshr miss rate for SCUpgradeReq accesses 3114system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.622634 # mshr miss rate for ReadExReq accesses 3115system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.458584 # mshr miss rate for ReadExReq accesses 3116system.l2c.ReadExReq_mshr_miss_rate::total 0.541433 # mshr miss rate for ReadExReq accesses 3117system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for ReadSharedReq accesses 3118system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for ReadSharedReq accesses 3119system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for ReadSharedReq accesses 3120system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.190955 # mshr miss rate for ReadSharedReq accesses 3121system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for ReadSharedReq accesses 3122system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for ReadSharedReq accesses 3123system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for ReadSharedReq accesses 3124system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for ReadSharedReq accesses 3125system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.164321 # mshr miss rate for ReadSharedReq accesses 3126system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for ReadSharedReq accesses 3127system.l2c.ReadSharedReq_mshr_miss_rate::total 0.225381 # mshr miss rate for ReadSharedReq accesses 3128system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.790941 # mshr miss rate for InvalidateReq accesses 3129system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.417452 # mshr miss rate for InvalidateReq accesses 3130system.l2c.InvalidateReq_mshr_miss_rate::total 0.681347 # mshr miss rate for InvalidateReq accesses 3131system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for demand accesses 3132system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for demand accesses 3133system.l2c.demand_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for demand accesses 3134system.l2c.demand_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for demand accesses 3135system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for demand accesses 3136system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for demand accesses 3137system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for demand accesses 3138system.l2c.demand_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for demand accesses 3139system.l2c.demand_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for demand accesses 3140system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for demand accesses 3141system.l2c.demand_mshr_miss_rate::total 0.246584 # mshr miss rate for demand accesses 3142system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115875 # mshr miss rate for overall accesses 3143system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.201250 # mshr miss rate for overall accesses 3144system.l2c.overall_mshr_miss_rate::cpu0.inst 0.109764 # mshr miss rate for overall accesses 3145system.l2c.overall_mshr_miss_rate::cpu0.data 0.259799 # mshr miss rate for overall accesses 3146system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.445123 # mshr miss rate for overall accesses 3147system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.131774 # mshr miss rate for overall accesses 3148system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.257926 # mshr miss rate for overall accesses 3149system.l2c.overall_mshr_miss_rate::cpu1.inst 0.097832 # mshr miss rate for overall accesses 3150system.l2c.overall_mshr_miss_rate::cpu1.data 0.206870 # mshr miss rate for overall accesses 3151system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.378078 # mshr miss rate for overall accesses 3152system.l2c.overall_mshr_miss_rate::total 0.246584 # mshr miss rate for overall accesses 3153system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20138.407667 # average UpgradeReq mshr miss latency 3154system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20719.933407 # average UpgradeReq mshr miss latency 3155system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20434.567817 # average UpgradeReq mshr miss latency 3156system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 23987.480438 # average SCUpgradeReq mshr miss latency 3157system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24755.760369 # average SCUpgradeReq mshr miss latency 3158system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24429.993364 # average SCUpgradeReq mshr miss latency 3159system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98342.382231 # average ReadExReq mshr miss latency 3160system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 103851.457660 # average ReadExReq mshr miss latency 3161system.l2c.ReadExReq_avg_mshr_miss_latency::total 100651.968310 # average ReadExReq mshr miss latency 3162system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average ReadSharedReq mshr miss latency 3163system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average ReadSharedReq mshr miss latency 3164system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average ReadSharedReq mshr miss latency 3165system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101484.703015 # average ReadSharedReq mshr miss latency 3166system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average ReadSharedReq mshr miss latency 3167system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average ReadSharedReq mshr miss latency 3168system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average ReadSharedReq mshr miss latency 3169system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average ReadSharedReq mshr miss latency 3170system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 107283.829493 # average ReadSharedReq mshr miss latency 3171system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average ReadSharedReq mshr miss latency 3172system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 115635.619321 # average ReadSharedReq mshr miss latency 3173system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 19728.771869 # average InvalidateReq mshr miss latency 3174system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 19079.766042 # average InvalidateReq mshr miss latency 3175system.l2c.InvalidateReq_avg_mshr_miss_latency::total 19612.091469 # average InvalidateReq mshr miss latency 3176system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency 3177system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency 3178system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency 3179system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency 3180system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average overall mshr miss latency 3181system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average overall mshr miss latency 3182system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency 3183system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency 3184system.l2c.demand_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency 3185system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency 3186system.l2c.demand_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency 3187system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 92499.490316 # average overall mshr miss latency 3188system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 101517.667024 # average overall mshr miss latency 3189system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 104816.710749 # average overall mshr miss latency 3190system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100283.675694 # average overall mshr miss latency 3191system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 126194.931918 # average overall mshr miss latency 3192system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 94649.409467 # average overall mshr miss latency 3193system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93097.176633 # average overall mshr miss latency 3194system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 108742.742873 # average overall mshr miss latency 3195system.l2c.overall_avg_mshr_miss_latency::cpu1.data 106183.625769 # average overall mshr miss latency 3196system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 122901.471666 # average overall mshr miss latency 3197system.l2c.overall_avg_mshr_miss_latency::total 113428.469758 # average overall mshr miss latency 3198system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average ReadReq mshr uncacheable latency 3199system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158335.221383 # average ReadReq mshr uncacheable latency 3200system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average ReadReq mshr uncacheable latency 3201system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152481.962450 # average ReadReq mshr uncacheable latency 3202system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 145677.383121 # average ReadReq mshr uncacheable latency 3203system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 72634.497354 # average overall mshr uncacheable latency 3204system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 76966.290508 # average overall mshr uncacheable latency 3205system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 70800 # average overall mshr uncacheable latency 3206system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 78032.198659 # average overall mshr uncacheable latency 3207system.l2c.overall_avg_mshr_uncacheable_latency::total 77279.539421 # average overall mshr uncacheable latency 3208system.membus.snoop_filter.tot_requests 3361893 # Total number of requests made to the snoop filter. 3209system.membus.snoop_filter.hit_single_requests 1995718 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3210system.membus.snoop_filter.hit_multi_requests 3092 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3211system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3212system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3213system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3214system.membus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3215system.membus.trans_dist::ReadReq 43096 # Transaction distribution 3216system.membus.trans_dist::ReadResp 738496 # Transaction distribution 3217system.membus.trans_dist::WriteReq 38143 # Transaction distribution 3218system.membus.trans_dist::WriteResp 38143 # Transaction distribution 3219system.membus.trans_dist::WritebackDirty 1107186 # Transaction distribution 3220system.membus.trans_dist::CleanEvict 202416 # Transaction distribution 3221system.membus.trans_dist::UpgradeReq 304555 # Transaction distribution 3222system.membus.trans_dist::SCUpgradeReq 296744 # Transaction distribution 3223system.membus.trans_dist::UpgradeResp 23 # Transaction distribution 3224system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution 3225system.membus.trans_dist::ReadExReq 135023 # Transaction distribution 3226system.membus.trans_dist::ReadExResp 117908 # Transaction distribution 3227system.membus.trans_dist::ReadSharedReq 695400 # Transaction distribution 3228system.membus.trans_dist::InvalidateReq 620101 # Transaction distribution 3229system.membus.trans_dist::InvalidateResp 29545 # Transaction distribution 3230system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122272 # Packet count per connected master and slave (bytes) 3231system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 3232system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25316 # Packet count per connected master and slave (bytes) 3233system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3948606 # Packet count per connected master and slave (bytes) 3234system.membus.pkt_count_system.l2c.mem_side::total 4096286 # Packet count per connected master and slave (bytes) 3235system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238208 # Packet count per connected master and slave (bytes) 3236system.membus.pkt_count_system.iocache.mem_side::total 238208 # Packet count per connected master and slave (bytes) 3237system.membus.pkt_count::total 4334494 # Packet count per connected master and slave (bytes) 3238system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155379 # Cumulative packet size per connected master and slave (bytes) 3239system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 3240system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50632 # Cumulative packet size per connected master and slave (bytes) 3241system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 115505708 # Cumulative packet size per connected master and slave (bytes) 3242system.membus.pkt_size_system.l2c.mem_side::total 115711923 # Cumulative packet size per connected master and slave (bytes) 3243system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7271808 # Cumulative packet size per connected master and slave (bytes) 3244system.membus.pkt_size_system.iocache.mem_side::total 7271808 # Cumulative packet size per connected master and slave (bytes) 3245system.membus.pkt_size::total 122983731 # Cumulative packet size per connected master and slave (bytes) 3246system.membus.snoops 615067 # Total snoops (count) 3247system.membus.snoopTraffic 174144 # Total snoop traffic (bytes) 3248system.membus.snoop_fanout::samples 2133066 # Request fanout histogram 3249system.membus.snoop_fanout::mean 0.015313 # Request fanout histogram 3250system.membus.snoop_fanout::stdev 0.122793 # Request fanout histogram 3251system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3252system.membus.snoop_fanout::0 2100403 98.47% 98.47% # Request fanout histogram 3253system.membus.snoop_fanout::1 32663 1.53% 100.00% # Request fanout histogram 3254system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3255system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3256system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3257system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3258system.membus.snoop_fanout::total 2133066 # Request fanout histogram 3259system.membus.reqLayer0.occupancy 100156000 # Layer occupancy (ticks) 3260system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3261system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) 3262system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3263system.membus.reqLayer2.occupancy 21088500 # Layer occupancy (ticks) 3264system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3265system.membus.reqLayer5.occupancy 7525887071 # Layer occupancy (ticks) 3266system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3267system.membus.respLayer2.occupancy 4366874131 # Layer occupancy (ticks) 3268system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3269system.membus.respLayer3.occupancy 80052408 # Layer occupancy (ticks) 3270system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3271system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3272system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3273system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3274system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3275system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3276system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3277system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3278system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3279system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3280system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3281system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3282system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3283system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3284system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3285system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3286system.realview.ethernet.txBytes 966 # Bytes Transmitted 3287system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3288system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3289system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3290system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3291system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3292system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3293system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3294system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3295system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3296system.realview.ethernet.totPackets 3 # Total Packets 3297system.realview.ethernet.totBytes 966 # Total Bytes 3298system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3299system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3300system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3301system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3302system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3303system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3304system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3305system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3306system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3307system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3308system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3309system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3310system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3311system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3312system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3313system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3314system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3315system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3316system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3317system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3318system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3319system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3320system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3321system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3322system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3323system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3324system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3325system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3326system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3327system.realview.ethernet.droppedPackets 0 # number of packets dropped 3328system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3329system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3330system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3331system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3332system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3333system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3334system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3335system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3336system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3337system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3338system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3339system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3340system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3341system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3342system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3343system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3344system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3345system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3346system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3347system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3348system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3349system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3350system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3351system.toL2Bus.snoop_filter.tot_requests 10343091 # Total number of requests made to the snoop filter. 3352system.toL2Bus.snoop_filter.hit_single_requests 5462203 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3353system.toL2Bus.snoop_filter.hit_multi_requests 1986792 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3354system.toL2Bus.snoop_filter.tot_snoops 195863 # Total number of snoops made to the snoop filter. 3355system.toL2Bus.snoop_filter.hit_single_snoops 175744 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3356system.toL2Bus.snoop_filter.hit_multi_snoops 20119 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3357system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47401370587500 # Cumulative time (in ticks) in various power states 3358system.toL2Bus.trans_dist::ReadReq 43098 # Transaction distribution 3359system.toL2Bus.trans_dist::ReadResp 3851068 # Transaction distribution 3360system.toL2Bus.trans_dist::WriteReq 38143 # Transaction distribution 3361system.toL2Bus.trans_dist::WriteResp 38143 # Transaction distribution 3362system.toL2Bus.trans_dist::WritebackDirty 3495681 # Transaction distribution 3363system.toL2Bus.trans_dist::CleanEvict 2217175 # Transaction distribution 3364system.toL2Bus.trans_dist::UpgradeReq 626966 # Transaction distribution 3365system.toL2Bus.trans_dist::SCUpgradeReq 393553 # Transaction distribution 3366system.toL2Bus.trans_dist::UpgradeResp 1020519 # Transaction distribution 3367system.toL2Bus.trans_dist::SCUpgradeFailReq 123 # Transaction distribution 3368system.toL2Bus.trans_dist::UpgradeFailResp 123 # Transaction distribution 3369system.toL2Bus.trans_dist::ReadExReq 273712 # Transaction distribution 3370system.toL2Bus.trans_dist::ReadExResp 273712 # Transaction distribution 3371system.toL2Bus.trans_dist::ReadSharedReq 3808446 # Transaction distribution 3372system.toL2Bus.trans_dist::InvalidateReq 849023 # Transaction distribution 3373system.toL2Bus.trans_dist::InvalidateResp 832010 # Transaction distribution 3374system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7676666 # Packet count per connected master and slave (bytes) 3375system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7311446 # Packet count per connected master and slave (bytes) 3376system.toL2Bus.pkt_count::total 14988112 # Packet count per connected master and slave (bytes) 3377system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 187677530 # Cumulative packet size per connected master and slave (bytes) 3378system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 181320537 # Cumulative packet size per connected master and slave (bytes) 3379system.toL2Bus.pkt_size::total 368998067 # Cumulative packet size per connected master and slave (bytes) 3380system.toL2Bus.snoops 2787811 # Total snoops (count) 3381system.toL2Bus.snoopTraffic 116317008 # Total snoop traffic (bytes) 3382system.toL2Bus.snoop_fanout::samples 7322753 # Request fanout histogram 3383system.toL2Bus.snoop_fanout::mean 0.391714 # Request fanout histogram 3384system.toL2Bus.snoop_fanout::stdev 0.493730 # Request fanout histogram 3385system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3386system.toL2Bus.snoop_fanout::0 4474450 61.10% 61.10% # Request fanout histogram 3387system.toL2Bus.snoop_fanout::1 2828184 38.62% 99.73% # Request fanout histogram 3388system.toL2Bus.snoop_fanout::2 20119 0.27% 100.00% # Request fanout histogram 3389system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3390system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3391system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3392system.toL2Bus.snoop_fanout::total 7322753 # Request fanout histogram 3393system.toL2Bus.reqLayer0.occupancy 8114772770 # Layer occupancy (ticks) 3394system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3395system.toL2Bus.snoopLayer0.occupancy 9310827 # Layer occupancy (ticks) 3396system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3397system.toL2Bus.respLayer0.occupancy 3511032286 # Layer occupancy (ticks) 3398system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3399system.toL2Bus.respLayer1.occupancy 3606444627 # Layer occupancy (ticks) 3400system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3401 3402---------- End Simulation Statistics ---------- 3403