stats.txt revision 10827
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.526955 # Number of seconds simulated 4sim_ticks 47526954967000 # Number of ticks simulated 5final_tick 47526954967000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 679404 # Simulator instruction rate (inst/s) 8host_op_rate 799114 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 36258651928 # Simulator tick rate (ticks/s) 10host_mem_usage 756696 # Number of bytes of host memory used 11host_seconds 1310.78 # Real time elapsed on the host 12sim_insts 890546366 # Number of instructions simulated 13sim_ops 1047459319 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu0.dtb.walker 120896 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu0.itb.walker 123520 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.inst 3402100 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.data 13323656 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.l2cache.prefetcher 13846976 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu1.dtb.walker 139776 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.itb.walker 143808 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.inst 3041464 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.data 11124432 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.l2cache.prefetcher 15361728 # Number of bytes read from this memory 26system.physmem.bytes_read::realview.ide 416704 # Number of bytes read from this memory 27system.physmem.bytes_read::total 61045060 # Number of bytes read from this memory 28system.physmem.bytes_inst_read::cpu0.inst 3402100 # Number of instructions bytes read from this memory 29system.physmem.bytes_inst_read::cpu1.inst 3041464 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::total 6443564 # Number of instructions bytes read from this memory 31system.physmem.bytes_written::writebacks 78583104 # Number of bytes written to this memory 32system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 34system.physmem.bytes_written::total 78603688 # Number of bytes written to this memory 35system.physmem.num_reads::cpu0.dtb.walker 1889 # Number of read requests responded to by this memory 36system.physmem.num_reads::cpu0.itb.walker 1930 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.inst 93565 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.data 208195 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.l2cache.prefetcher 216359 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu1.dtb.walker 2184 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.itb.walker 2247 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.inst 47611 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.data 173832 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.l2cache.prefetcher 240027 # Number of read requests responded to by this memory 45system.physmem.num_reads::realview.ide 6511 # Number of read requests responded to by this memory 46system.physmem.num_reads::total 994350 # Number of read requests responded to by this memory 47system.physmem.num_writes::writebacks 1227861 # Number of write requests responded to by this memory 48system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 50system.physmem.num_writes::total 1230435 # Number of write requests responded to by this memory 51system.physmem.bw_read::cpu0.dtb.walker 2544 # Total read bandwidth from this memory (bytes/s) 52system.physmem.bw_read::cpu0.itb.walker 2599 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.inst 71583 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.data 280339 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.l2cache.prefetcher 291350 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu1.dtb.walker 2941 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.itb.walker 3026 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.inst 63995 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.data 234066 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.l2cache.prefetcher 323221 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::realview.ide 8768 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::total 1284430 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_inst_read::cpu0.inst 71583 # Instruction read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu1.inst 63995 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::total 135577 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_write::writebacks 1653443 # Write bandwidth from this memory (bytes/s) 67system.physmem.bw_write::cpu0.data 433 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::total 1653876 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_total::writebacks 1653443 # Total bandwidth to/from this memory (bytes/s) 71system.physmem.bw_total::cpu0.dtb.walker 2544 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.itb.walker 2599 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.inst 71583 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.data 280772 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.l2cache.prefetcher 291350 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu1.dtb.walker 2941 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.itb.walker 3026 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.inst 63995 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.data 234066 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.l2cache.prefetcher 323221 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::realview.ide 8768 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::total 2938306 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.readReqs 994350 # Number of read requests accepted 84system.physmem.writeReqs 1902822 # Number of write requests accepted 85system.physmem.readBursts 994350 # Number of DRAM read bursts, including those serviced by the write queue 86system.physmem.writeBursts 1902822 # Number of DRAM write bursts, including those merged in the write queue 87system.physmem.bytesReadDRAM 63617152 # Total number of bytes read from DRAM 88system.physmem.bytesReadWrQ 21248 # Total number of bytes read from write queue 89system.physmem.bytesWritten 118663680 # Total number of bytes written to DRAM 90system.physmem.bytesReadSys 61045060 # Total read bytes from the system interface side 91system.physmem.bytesWrittenSys 121636456 # Total written bytes from the system interface side 92system.physmem.servicedByWrQ 332 # Number of DRAM read bursts serviced by the write queue 93system.physmem.mergedWrBursts 48679 # Number of DRAM write bursts merged with an existing one 94system.physmem.neitherReadNorWriteReqs 115330 # Number of requests that are neither read nor write 95system.physmem.perBankRdBursts::0 57482 # Per bank write bursts 96system.physmem.perBankRdBursts::1 61474 # Per bank write bursts 97system.physmem.perBankRdBursts::2 58055 # Per bank write bursts 98system.physmem.perBankRdBursts::3 62815 # Per bank write bursts 99system.physmem.perBankRdBursts::4 61744 # Per bank write bursts 100system.physmem.perBankRdBursts::5 72443 # Per bank write bursts 101system.physmem.perBankRdBursts::6 62137 # Per bank write bursts 102system.physmem.perBankRdBursts::7 62898 # Per bank write bursts 103system.physmem.perBankRdBursts::8 53757 # Per bank write bursts 104system.physmem.perBankRdBursts::9 98485 # Per bank write bursts 105system.physmem.perBankRdBursts::10 53699 # Per bank write bursts 106system.physmem.perBankRdBursts::11 61424 # Per bank write bursts 107system.physmem.perBankRdBursts::12 50178 # Per bank write bursts 108system.physmem.perBankRdBursts::13 60766 # Per bank write bursts 109system.physmem.perBankRdBursts::14 57507 # Per bank write bursts 110system.physmem.perBankRdBursts::15 59154 # Per bank write bursts 111system.physmem.perBankWrBursts::0 114707 # Per bank write bursts 112system.physmem.perBankWrBursts::1 119877 # Per bank write bursts 113system.physmem.perBankWrBursts::2 118693 # Per bank write bursts 114system.physmem.perBankWrBursts::3 118700 # Per bank write bursts 115system.physmem.perBankWrBursts::4 118108 # Per bank write bursts 116system.physmem.perBankWrBursts::5 125436 # Per bank write bursts 117system.physmem.perBankWrBursts::6 113884 # Per bank write bursts 118system.physmem.perBankWrBursts::7 116296 # Per bank write bursts 119system.physmem.perBankWrBursts::8 112515 # Per bank write bursts 120system.physmem.perBankWrBursts::9 116242 # Per bank write bursts 121system.physmem.perBankWrBursts::10 112992 # Per bank write bursts 122system.physmem.perBankWrBursts::11 118745 # Per bank write bursts 123system.physmem.perBankWrBursts::12 107808 # Per bank write bursts 124system.physmem.perBankWrBursts::13 111387 # Per bank write bursts 125system.physmem.perBankWrBursts::14 114155 # Per bank write bursts 126system.physmem.perBankWrBursts::15 114575 # Per bank write bursts 127system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 128system.physmem.numWrRetry 406 # Number of times write queue was full causing retry 129system.physmem.totGap 47526951912500 # Total gap between requests 130system.physmem.readPktSize::0 0 # Read request sizes (log2) 131system.physmem.readPktSize::1 0 # Read request sizes (log2) 132system.physmem.readPktSize::2 43195 # Read request sizes (log2) 133system.physmem.readPktSize::3 25 # Read request sizes (log2) 134system.physmem.readPktSize::4 5 # Read request sizes (log2) 135system.physmem.readPktSize::5 0 # Read request sizes (log2) 136system.physmem.readPktSize::6 951125 # Read request sizes (log2) 137system.physmem.writePktSize::0 0 # Write request sizes (log2) 138system.physmem.writePktSize::1 0 # Write request sizes (log2) 139system.physmem.writePktSize::2 2 # Write request sizes (log2) 140system.physmem.writePktSize::3 2572 # Write request sizes (log2) 141system.physmem.writePktSize::4 0 # Write request sizes (log2) 142system.physmem.writePktSize::5 0 # Write request sizes (log2) 143system.physmem.writePktSize::6 1900248 # Write request sizes (log2) 144system.physmem.rdQLenPdf::0 698116 # What read queue length does an incoming req see 145system.physmem.rdQLenPdf::1 83658 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::2 42191 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::3 36638 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::4 31495 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::5 28119 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::6 24839 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::7 21358 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::8 17624 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::9 4596 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::10 1385 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::11 1018 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::12 839 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::13 651 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::14 464 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::15 363 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::17 218 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::18 93 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::19 61 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::20 8 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 176system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::15 55966 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::16 69244 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::17 86453 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::18 95710 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::19 99723 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::20 98450 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::21 98652 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::22 98653 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::23 101180 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::24 101256 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::25 102685 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::26 108850 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::27 104999 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::28 104785 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::29 118151 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::30 108223 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::31 102687 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::32 99179 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::33 6890 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::34 5415 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::35 5566 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::36 6838 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::37 6775 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::38 6308 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::39 6158 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::40 7224 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::41 5430 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::42 4899 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::43 4456 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::44 5091 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::45 4051 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::46 3523 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::47 3763 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::48 2982 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::49 2416 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::50 1572 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::51 1266 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::52 928 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::53 971 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::54 818 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::55 686 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::56 685 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::57 630 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::58 505 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::59 480 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::60 450 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::61 474 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::62 421 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::63 1611 # What write queue length does an incoming req see 240system.physmem.bytesPerActivate::samples 1054851 # Bytes accessed per row activation 241system.physmem.bytesPerActivate::mean 172.802142 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::gmean 106.115345 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::stdev 242.100455 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::0-127 681651 64.62% 64.62% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::128-255 201380 19.09% 83.71% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::256-383 48895 4.64% 88.35% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::384-511 24340 2.31% 90.65% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::512-639 17755 1.68% 92.34% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::640-767 11649 1.10% 93.44% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::768-895 8558 0.81% 94.25% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::896-1023 7940 0.75% 95.01% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::1024-1151 52683 4.99% 100.00% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::total 1054851 # Bytes accessed per row activation 254system.physmem.rdPerTurnAround::samples 92018 # Reads before turning the bus around for writes 255system.physmem.rdPerTurnAround::mean 10.802300 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::stdev 106.341779 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::0-1023 92015 100.00% 100.00% # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::1024-2047 1 0.00% 100.00% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::20480-21503 1 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::23552-24575 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::total 92018 # Reads before turning the bus around for writes 262system.physmem.wrPerTurnAround::samples 92018 # Writes before turning the bus around for reads 263system.physmem.wrPerTurnAround::mean 20.149536 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::gmean 18.827281 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::stdev 17.009129 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::16-31 90131 97.95% 97.95% # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::32-47 760 0.83% 98.78% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::48-63 32 0.03% 98.81% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::64-79 41 0.04% 98.85% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::80-95 142 0.15% 99.01% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::96-111 182 0.20% 99.21% # Writes before turning the bus around for reads 272system.physmem.wrPerTurnAround::112-127 347 0.38% 99.58% # Writes before turning the bus around for reads 273system.physmem.wrPerTurnAround::128-143 116 0.13% 99.71% # Writes before turning the bus around for reads 274system.physmem.wrPerTurnAround::144-159 35 0.04% 99.75% # Writes before turning the bus around for reads 275system.physmem.wrPerTurnAround::160-175 12 0.01% 99.76% # Writes before turning the bus around for reads 276system.physmem.wrPerTurnAround::176-191 63 0.07% 99.83% # Writes before turning the bus around for reads 277system.physmem.wrPerTurnAround::192-207 31 0.03% 99.86% # Writes before turning the bus around for reads 278system.physmem.wrPerTurnAround::208-223 15 0.02% 99.88% # Writes before turning the bus around for reads 279system.physmem.wrPerTurnAround::224-239 6 0.01% 99.89% # Writes before turning the bus around for reads 280system.physmem.wrPerTurnAround::240-255 1 0.00% 99.89% # Writes before turning the bus around for reads 281system.physmem.wrPerTurnAround::256-271 4 0.00% 99.89% # Writes before turning the bus around for reads 282system.physmem.wrPerTurnAround::272-287 5 0.01% 99.90% # Writes before turning the bus around for reads 283system.physmem.wrPerTurnAround::288-303 6 0.01% 99.90% # Writes before turning the bus around for reads 284system.physmem.wrPerTurnAround::304-319 11 0.01% 99.92% # Writes before turning the bus around for reads 285system.physmem.wrPerTurnAround::320-335 16 0.02% 99.93% # Writes before turning the bus around for reads 286system.physmem.wrPerTurnAround::336-351 8 0.01% 99.94% # Writes before turning the bus around for reads 287system.physmem.wrPerTurnAround::352-367 24 0.03% 99.97% # Writes before turning the bus around for reads 288system.physmem.wrPerTurnAround::368-383 5 0.01% 99.97% # Writes before turning the bus around for reads 289system.physmem.wrPerTurnAround::384-399 4 0.00% 99.98% # Writes before turning the bus around for reads 290system.physmem.wrPerTurnAround::400-415 2 0.00% 99.98% # Writes before turning the bus around for reads 291system.physmem.wrPerTurnAround::416-431 1 0.00% 99.98% # Writes before turning the bus around for reads 292system.physmem.wrPerTurnAround::432-447 1 0.00% 99.98% # Writes before turning the bus around for reads 293system.physmem.wrPerTurnAround::448-463 1 0.00% 99.98% # Writes before turning the bus around for reads 294system.physmem.wrPerTurnAround::464-479 2 0.00% 99.98% # Writes before turning the bus around for reads 295system.physmem.wrPerTurnAround::480-495 1 0.00% 99.99% # Writes before turning the bus around for reads 296system.physmem.wrPerTurnAround::496-511 1 0.00% 99.99% # Writes before turning the bus around for reads 297system.physmem.wrPerTurnAround::512-527 1 0.00% 99.99% # Writes before turning the bus around for reads 298system.physmem.wrPerTurnAround::528-543 3 0.00% 99.99% # Writes before turning the bus around for reads 299system.physmem.wrPerTurnAround::544-559 2 0.00% 99.99% # Writes before turning the bus around for reads 300system.physmem.wrPerTurnAround::560-575 2 0.00% 100.00% # Writes before turning the bus around for reads 301system.physmem.wrPerTurnAround::576-591 2 0.00% 100.00% # Writes before turning the bus around for reads 302system.physmem.wrPerTurnAround::736-751 1 0.00% 100.00% # Writes before turning the bus around for reads 303system.physmem.wrPerTurnAround::848-863 1 0.00% 100.00% # Writes before turning the bus around for reads 304system.physmem.wrPerTurnAround::total 92018 # Writes before turning the bus around for reads 305system.physmem.totQLat 36585898476 # Total ticks spent queuing 306system.physmem.totMemAccLat 55223735976 # Total ticks spent from burst creation until serviced by the DRAM 307system.physmem.totBusLat 4970090000 # Total ticks spent in databus transfers 308system.physmem.avgQLat 36806.07 # Average queueing delay per DRAM burst 309system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 310system.physmem.avgMemAccLat 55556.07 # Average memory access latency per DRAM burst 311system.physmem.avgRdBW 1.34 # Average DRAM read bandwidth in MiByte/s 312system.physmem.avgWrBW 2.50 # Average achieved write bandwidth in MiByte/s 313system.physmem.avgRdBWSys 1.28 # Average system read bandwidth in MiByte/s 314system.physmem.avgWrBWSys 2.56 # Average system write bandwidth in MiByte/s 315system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 316system.physmem.busUtil 0.03 # Data bus utilization in percentage 317system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 318system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes 319system.physmem.avgRdQLen 1.18 # Average read queue length when enqueuing 320system.physmem.avgWrQLen 25.94 # Average write queue length when enqueuing 321system.physmem.readRowHits 744165 # Number of row buffer hits during reads 322system.physmem.writeRowHits 1049121 # Number of row buffer hits during writes 323system.physmem.readRowHitRate 74.86 # Row buffer hit rate for reads 324system.physmem.writeRowHitRate 56.58 # Row buffer hit rate for writes 325system.physmem.avgGap 16404601.42 # Average gap between requests 326system.physmem.pageHitRate 62.96 # Row buffer hit rate, read and write combined 327system.physmem_0.actEnergy 4105851120 # Energy for activate commands per rank (pJ) 328system.physmem_0.preEnergy 2240295750 # Energy for precharge commands per rank (pJ) 329system.physmem_0.readEnergy 3892535400 # Energy for read commands per rank (pJ) 330system.physmem_0.writeEnergy 6128142480 # Energy for write commands per rank (pJ) 331system.physmem_0.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ) 332system.physmem_0.actBackEnergy 1214897373855 # Energy for active background per rank (pJ) 333system.physmem_0.preBackEnergy 27450471155250 # Energy for precharge background per rank (pJ) 334system.physmem_0.totalEnergy 31785964742895 # Total energy per rank (pJ) 335system.physmem_0.averagePower 668.798736 # Core power per rank (mW) 336system.physmem_0.memoryStateTime::IDLE 45665609957576 # Time in different power states 337system.physmem_0.memoryStateTime::REF 1587029340000 # Time in different power states 338system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 339system.physmem_0.memoryStateTime::ACT 274315218424 # Time in different power states 340system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 341system.physmem_1.actEnergy 3868822440 # Energy for activate commands per rank (pJ) 342system.physmem_1.preEnergy 2110964625 # Energy for precharge commands per rank (pJ) 343system.physmem_1.readEnergy 3860766000 # Energy for read commands per rank (pJ) 344system.physmem_1.writeEnergy 5886555120 # Energy for write commands per rank (pJ) 345system.physmem_1.refreshEnergy 3104229389040 # Energy for refresh commands per rank (pJ) 346system.physmem_1.actBackEnergy 1202076105075 # Energy for active background per rank (pJ) 347system.physmem_1.preBackEnergy 27461717882250 # Energy for precharge background per rank (pJ) 348system.physmem_1.totalEnergy 31783750484550 # Total energy per rank (pJ) 349system.physmem_1.averagePower 668.752146 # Core power per rank (mW) 350system.physmem_1.memoryStateTime::IDLE 45684364167822 # Time in different power states 351system.physmem_1.memoryStateTime::REF 1587029340000 # Time in different power states 352system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 353system.physmem_1.memoryStateTime::ACT 255557515928 # Time in different power states 354system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 355system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory 356system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 357system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory 358system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 359system.realview.nvmem.bytes_read::total 204 # Number of bytes read from this memory 360system.realview.nvmem.bytes_inst_read::cpu0.inst 96 # Number of instructions bytes read from this memory 361system.realview.nvmem.bytes_inst_read::cpu1.inst 64 # Number of instructions bytes read from this memory 362system.realview.nvmem.bytes_inst_read::total 160 # Number of instructions bytes read from this memory 363system.realview.nvmem.num_reads::cpu0.inst 24 # Number of read requests responded to by this memory 364system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 365system.realview.nvmem.num_reads::cpu1.inst 16 # Number of read requests responded to by this memory 366system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 367system.realview.nvmem.num_reads::total 46 # Number of read requests responded to by this memory 368system.realview.nvmem.bw_read::cpu0.inst 2 # Total read bandwidth from this memory (bytes/s) 369system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 370system.realview.nvmem.bw_read::cpu1.inst 1 # Total read bandwidth from this memory (bytes/s) 371system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 372system.realview.nvmem.bw_read::total 4 # Total read bandwidth from this memory (bytes/s) 373system.realview.nvmem.bw_inst_read::cpu0.inst 2 # Instruction read bandwidth from this memory (bytes/s) 374system.realview.nvmem.bw_inst_read::cpu1.inst 1 # Instruction read bandwidth from this memory (bytes/s) 375system.realview.nvmem.bw_inst_read::total 3 # Instruction read bandwidth from this memory (bytes/s) 376system.realview.nvmem.bw_total::cpu0.inst 2 # Total bandwidth to/from this memory (bytes/s) 377system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 378system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s) 379system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 380system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s) 381system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 382system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 383system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 384system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 385system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 386system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 387system.cpu_clk_domain.clock 500 # Clock period in ticks 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 392system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 393system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 395system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 396system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 397system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 398system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 399system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 400system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 401system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 402system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 403system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 404system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 405system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 406system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 407system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 408system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 409system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 410system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 411system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 412system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 413system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 414system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 415system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 416system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 417system.cpu0.dtb.walker.walks 101631 # Table walker walks requested 418system.cpu0.dtb.walker.walksLong 101631 # Table walker walks initiated with long descriptors 419system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 9048 # Level at which table walker walks with long descriptors terminate 420system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 76119 # Level at which table walker walks with long descriptors terminate 421system.cpu0.dtb.walker.walksSquashedBefore 11 # Table walks squashed before starting 422system.cpu0.dtb.walker.walkWaitTime::samples 101620 # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::mean 0.113167 # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::stdev 36.075158 # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkWaitTime::0-1023 101619 100.00% 100.00% # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::11264-12287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::total 101620 # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkCompletionTime::samples 85178 # Table walker service (enqueue to completion) latency 429system.cpu0.dtb.walker.walkCompletionTime::mean 19101.889572 # Table walker service (enqueue to completion) latency 430system.cpu0.dtb.walker.walkCompletionTime::gmean 17045.635811 # Table walker service (enqueue to completion) latency 431system.cpu0.dtb.walker.walkCompletionTime::stdev 15664.933997 # Table walker service (enqueue to completion) latency 432system.cpu0.dtb.walker.walkCompletionTime::0-65535 84047 98.67% 98.67% # Table walker service (enqueue to completion) latency 433system.cpu0.dtb.walker.walkCompletionTime::65536-131071 953 1.12% 99.79% # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::131072-196607 46 0.05% 99.85% # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::196608-262143 63 0.07% 99.92% # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::262144-327679 53 0.06% 99.98% # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::327680-393215 8 0.01% 99.99% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::458752-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::655360-720895 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::total 85178 # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walksPending::samples 6479942056 # Table walker pending requests distribution 445system.cpu0.dtb.walker.walksPending::mean 1.123756 # Table walker pending requests distribution 446system.cpu0.dtb.walker.walksPending::0 -801929896 -12.38% -12.38% # Table walker pending requests distribution 447system.cpu0.dtb.walker.walksPending::1 7281871952 112.38% 100.00% # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::total 6479942056 # Table walker pending requests distribution 449system.cpu0.dtb.walker.walkPageSizes::4K 76120 89.38% 89.38% # Table walker page sizes translated 450system.cpu0.dtb.walker.walkPageSizes::2M 9048 10.62% 100.00% # Table walker page sizes translated 451system.cpu0.dtb.walker.walkPageSizes::total 85168 # Table walker page sizes translated 452system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 101631 # Table walker requests started/completed, data/inst 453system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 454system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 101631 # Table walker requests started/completed, data/inst 455system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 85168 # Table walker requests started/completed, data/inst 456system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 457system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 85168 # Table walker requests started/completed, data/inst 458system.cpu0.dtb.walker.walkRequestOrigin::total 186799 # Table walker requests started/completed, data/inst 459system.cpu0.dtb.inst_hits 0 # ITB inst hits 460system.cpu0.dtb.inst_misses 0 # ITB inst misses 461system.cpu0.dtb.read_hits 83767358 # DTB read hits 462system.cpu0.dtb.read_misses 74871 # DTB read misses 463system.cpu0.dtb.write_hits 75914688 # DTB write hits 464system.cpu0.dtb.write_misses 26760 # DTB write misses 465system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed 466system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 467system.cpu0.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID 468system.cpu0.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID 469system.cpu0.dtb.flush_entries 32159 # Number of entries that have been flushed from TLB 470system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 471system.cpu0.dtb.prefetch_faults 3900 # Number of TLB faults due to prefetch 472system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 473system.cpu0.dtb.perms_faults 8424 # Number of TLB faults due to permissions restrictions 474system.cpu0.dtb.read_accesses 83842229 # DTB read accesses 475system.cpu0.dtb.write_accesses 75941448 # DTB write accesses 476system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 477system.cpu0.dtb.hits 159682046 # DTB hits 478system.cpu0.dtb.misses 101631 # DTB misses 479system.cpu0.dtb.accesses 159783677 # DTB accesses 480system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 481system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 482system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 483system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 484system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 485system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 486system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 487system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 488system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 489system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 490system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 491system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 492system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 493system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 494system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 495system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 496system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 497system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 498system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 499system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 500system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 501system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 502system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 503system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 504system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 505system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 506system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 507system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 508system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 509system.cpu0.itb.walker.walks 55722 # Table walker walks requested 510system.cpu0.itb.walker.walksLong 55722 # Table walker walks initiated with long descriptors 511system.cpu0.itb.walker.walksLongTerminationLevel::Level2 543 # Level at which table walker walks with long descriptors terminate 512system.cpu0.itb.walker.walksLongTerminationLevel::Level3 49598 # Level at which table walker walks with long descriptors terminate 513system.cpu0.itb.walker.walkWaitTime::samples 55722 # Table walker wait (enqueue to first request) latency 514system.cpu0.itb.walker.walkWaitTime::0 55722 100.00% 100.00% # Table walker wait (enqueue to first request) latency 515system.cpu0.itb.walker.walkWaitTime::total 55722 # Table walker wait (enqueue to first request) latency 516system.cpu0.itb.walker.walkCompletionTime::samples 50141 # Table walker service (enqueue to completion) latency 517system.cpu0.itb.walker.walkCompletionTime::mean 22337.612912 # Table walker service (enqueue to completion) latency 518system.cpu0.itb.walker.walkCompletionTime::gmean 19289.783493 # Table walker service (enqueue to completion) latency 519system.cpu0.itb.walker.walkCompletionTime::stdev 21041.520478 # Table walker service (enqueue to completion) latency 520system.cpu0.itb.walker.walkCompletionTime::0-65535 48785 97.30% 97.30% # Table walker service (enqueue to completion) latency 521system.cpu0.itb.walker.walkCompletionTime::65536-131071 1144 2.28% 99.58% # Table walker service (enqueue to completion) latency 522system.cpu0.itb.walker.walkCompletionTime::131072-196607 57 0.11% 99.69% # Table walker service (enqueue to completion) latency 523system.cpu0.itb.walker.walkCompletionTime::196608-262143 79 0.16% 99.85% # Table walker service (enqueue to completion) latency 524system.cpu0.itb.walker.walkCompletionTime::262144-327679 56 0.11% 99.96% # Table walker service (enqueue to completion) latency 525system.cpu0.itb.walker.walkCompletionTime::327680-393215 13 0.03% 99.99% # Table walker service (enqueue to completion) latency 526system.cpu0.itb.walker.walkCompletionTime::393216-458751 3 0.01% 99.99% # Table walker service (enqueue to completion) latency 527system.cpu0.itb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 528system.cpu0.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 529system.cpu0.itb.walker.walkCompletionTime::total 50141 # Table walker service (enqueue to completion) latency 530system.cpu0.itb.walker.walksPending::samples -241360296 # Table walker pending requests distribution 531system.cpu0.itb.walker.walksPending::0 -241360296 100.00% 100.00% # Table walker pending requests distribution 532system.cpu0.itb.walker.walksPending::total -241360296 # Table walker pending requests distribution 533system.cpu0.itb.walker.walkPageSizes::4K 49598 98.92% 98.92% # Table walker page sizes translated 534system.cpu0.itb.walker.walkPageSizes::2M 543 1.08% 100.00% # Table walker page sizes translated 535system.cpu0.itb.walker.walkPageSizes::total 50141 # Table walker page sizes translated 536system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 537system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 55722 # Table walker requests started/completed, data/inst 538system.cpu0.itb.walker.walkRequestOrigin_Requested::total 55722 # Table walker requests started/completed, data/inst 539system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 540system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 50141 # Table walker requests started/completed, data/inst 541system.cpu0.itb.walker.walkRequestOrigin_Completed::total 50141 # Table walker requests started/completed, data/inst 542system.cpu0.itb.walker.walkRequestOrigin::total 105863 # Table walker requests started/completed, data/inst 543system.cpu0.itb.inst_hits 444122432 # ITB inst hits 544system.cpu0.itb.inst_misses 55722 # ITB inst misses 545system.cpu0.itb.read_hits 0 # DTB read hits 546system.cpu0.itb.read_misses 0 # DTB read misses 547system.cpu0.itb.write_hits 0 # DTB write hits 548system.cpu0.itb.write_misses 0 # DTB write misses 549system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed 550system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 551system.cpu0.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID 552system.cpu0.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID 553system.cpu0.itb.flush_entries 22526 # Number of entries that have been flushed from TLB 554system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 555system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 556system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 557system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 558system.cpu0.itb.read_accesses 0 # DTB read accesses 559system.cpu0.itb.write_accesses 0 # DTB write accesses 560system.cpu0.itb.inst_accesses 444178154 # ITB inst accesses 561system.cpu0.itb.hits 444122432 # DTB hits 562system.cpu0.itb.misses 55722 # DTB misses 563system.cpu0.itb.accesses 444178154 # DTB accesses 564system.cpu0.numCycles 95053909934 # number of cpu cycles simulated 565system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 566system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 567system.cpu0.committedInsts 443872382 # Number of instructions committed 568system.cpu0.committedOps 521690846 # Number of ops (including micro ops) committed 569system.cpu0.num_int_alu_accesses 479475231 # Number of integer alu accesses 570system.cpu0.num_fp_alu_accesses 421225 # Number of float alu accesses 571system.cpu0.num_func_calls 26535732 # number of times a function call or return occured 572system.cpu0.num_conditional_control_insts 67239811 # number of instructions that are conditional controls 573system.cpu0.num_int_insts 479475231 # number of integer instructions 574system.cpu0.num_fp_insts 421225 # number of float instructions 575system.cpu0.num_int_register_reads 693782505 # number of times the integer registers were read 576system.cpu0.num_int_register_writes 380162379 # number of times the integer registers were written 577system.cpu0.num_fp_register_reads 701849 # number of times the floating registers were read 578system.cpu0.num_fp_register_writes 304628 # number of times the floating registers were written 579system.cpu0.num_cc_register_reads 115037577 # number of times the CC registers were read 580system.cpu0.num_cc_register_writes 114748059 # number of times the CC registers were written 581system.cpu0.num_mem_refs 159672530 # number of memory refs 582system.cpu0.num_load_insts 83761106 # Number of load instructions 583system.cpu0.num_store_insts 75911424 # Number of store instructions 584system.cpu0.num_idle_cycles 93959856753.206024 # Number of idle cycles 585system.cpu0.num_busy_cycles 1094053180.793977 # Number of busy cycles 586system.cpu0.not_idle_fraction 0.011510 # Percentage of non-idle cycles 587system.cpu0.idle_fraction 0.988490 # Percentage of idle cycles 588system.cpu0.Branches 99058393 # Number of branches fetched 589system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 590system.cpu0.op_class::IntAlu 361081858 69.17% 69.17% # Class of executed instruction 591system.cpu0.op_class::IntMult 1125018 0.22% 69.39% # Class of executed instruction 592system.cpu0.op_class::IntDiv 61306 0.01% 69.40% # Class of executed instruction 593system.cpu0.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction 594system.cpu0.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction 595system.cpu0.op_class::FloatCvt 0 0.00% 69.40% # Class of executed instruction 596system.cpu0.op_class::FloatMult 0 0.00% 69.40% # Class of executed instruction 597system.cpu0.op_class::FloatDiv 0 0.00% 69.40% # Class of executed instruction 598system.cpu0.op_class::FloatSqrt 0 0.00% 69.40% # Class of executed instruction 599system.cpu0.op_class::SimdAdd 0 0.00% 69.40% # Class of executed instruction 600system.cpu0.op_class::SimdAddAcc 0 0.00% 69.40% # Class of executed instruction 601system.cpu0.op_class::SimdAlu 0 0.00% 69.40% # Class of executed instruction 602system.cpu0.op_class::SimdCmp 0 0.00% 69.40% # Class of executed instruction 603system.cpu0.op_class::SimdCvt 0 0.00% 69.40% # Class of executed instruction 604system.cpu0.op_class::SimdMisc 0 0.00% 69.40% # Class of executed instruction 605system.cpu0.op_class::SimdMult 0 0.00% 69.40% # Class of executed instruction 606system.cpu0.op_class::SimdMultAcc 0 0.00% 69.40% # Class of executed instruction 607system.cpu0.op_class::SimdShift 0 0.00% 69.40% # Class of executed instruction 608system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.40% # Class of executed instruction 609system.cpu0.op_class::SimdSqrt 0 0.00% 69.40% # Class of executed instruction 610system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.40% # Class of executed instruction 611system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.40% # Class of executed instruction 612system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.40% # Class of executed instruction 613system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.40% # Class of executed instruction 614system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.40% # Class of executed instruction 615system.cpu0.op_class::SimdFloatMisc 43308 0.01% 69.41% # Class of executed instruction 616system.cpu0.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction 617system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction 618system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction 619system.cpu0.op_class::MemRead 83761106 16.05% 85.46% # Class of executed instruction 620system.cpu0.op_class::MemWrite 75911424 14.54% 100.00% # Class of executed instruction 621system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 622system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 623system.cpu0.op_class::total 521984020 # Class of executed instruction 624system.cpu0.kern.inst.arm 0 # number of arm instructions executed 625system.cpu0.kern.inst.quiesce 5106 # number of quiesce instructions executed 626system.cpu0.dcache.tags.replacements 5414405 # number of replacements 627system.cpu0.dcache.tags.tagsinuse 480.206026 # Cycle average of tags in use 628system.cpu0.dcache.tags.total_refs 154030593 # Total number of references to valid blocks. 629system.cpu0.dcache.tags.sampled_refs 5414914 # Sample count of references to valid blocks. 630system.cpu0.dcache.tags.avg_refs 28.445621 # Average number of references to valid blocks. 631system.cpu0.dcache.tags.warmup_cycle 4071814500 # Cycle when the warmup percentage was hit. 632system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.206026 # Average occupied blocks per requestor 633system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937902 # Average percentage of cache occupancy 634system.cpu0.dcache.tags.occ_percent::total 0.937902 # Average percentage of cache occupancy 635system.cpu0.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id 636system.cpu0.dcache.tags.age_task_id_blocks_1024::0 7 # Occupied blocks per task id 637system.cpu0.dcache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id 638system.cpu0.dcache.tags.age_task_id_blocks_1024::2 344 # Occupied blocks per task id 639system.cpu0.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id 640system.cpu0.dcache.tags.tag_accesses 324790756 # Number of tag accesses 641system.cpu0.dcache.tags.data_accesses 324790756 # Number of data accesses 642system.cpu0.dcache.ReadReq_hits::cpu0.data 77996551 # number of ReadReq hits 643system.cpu0.dcache.ReadReq_hits::total 77996551 # number of ReadReq hits 644system.cpu0.dcache.WriteReq_hits::cpu0.data 71694037 # number of WriteReq hits 645system.cpu0.dcache.WriteReq_hits::total 71694037 # number of WriteReq hits 646system.cpu0.dcache.SoftPFReq_hits::cpu0.data 187802 # number of SoftPFReq hits 647system.cpu0.dcache.SoftPFReq_hits::total 187802 # number of SoftPFReq hits 648system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 131287 # number of WriteInvalidateReq hits 649system.cpu0.dcache.WriteInvalidateReq_hits::total 131287 # number of WriteInvalidateReq hits 650system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1831493 # number of LoadLockedReq hits 651system.cpu0.dcache.LoadLockedReq_hits::total 1831493 # number of LoadLockedReq hits 652system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1787873 # number of StoreCondReq hits 653system.cpu0.dcache.StoreCondReq_hits::total 1787873 # number of StoreCondReq hits 654system.cpu0.dcache.demand_hits::cpu0.data 149690588 # number of demand (read+write) hits 655system.cpu0.dcache.demand_hits::total 149690588 # number of demand (read+write) hits 656system.cpu0.dcache.overall_hits::cpu0.data 149878390 # number of overall hits 657system.cpu0.dcache.overall_hits::total 149878390 # number of overall hits 658system.cpu0.dcache.ReadReq_misses::cpu0.data 2964325 # number of ReadReq misses 659system.cpu0.dcache.ReadReq_misses::total 2964325 # number of ReadReq misses 660system.cpu0.dcache.WriteReq_misses::cpu0.data 1343066 # number of WriteReq misses 661system.cpu0.dcache.WriteReq_misses::total 1343066 # number of WriteReq misses 662system.cpu0.dcache.SoftPFReq_misses::cpu0.data 617580 # number of SoftPFReq misses 663system.cpu0.dcache.SoftPFReq_misses::total 617580 # number of SoftPFReq misses 664system.cpu0.dcache.WriteInvalidateReq_misses::cpu0.data 739156 # number of WriteInvalidateReq misses 665system.cpu0.dcache.WriteInvalidateReq_misses::total 739156 # number of WriteInvalidateReq misses 666system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 153043 # number of LoadLockedReq misses 667system.cpu0.dcache.LoadLockedReq_misses::total 153043 # number of LoadLockedReq misses 668system.cpu0.dcache.StoreCondReq_misses::cpu0.data 195288 # number of StoreCondReq misses 669system.cpu0.dcache.StoreCondReq_misses::total 195288 # number of StoreCondReq misses 670system.cpu0.dcache.demand_misses::cpu0.data 4307391 # number of demand (read+write) misses 671system.cpu0.dcache.demand_misses::total 4307391 # number of demand (read+write) misses 672system.cpu0.dcache.overall_misses::cpu0.data 4924971 # number of overall misses 673system.cpu0.dcache.overall_misses::total 4924971 # number of overall misses 674system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 44154787210 # number of ReadReq miss cycles 675system.cpu0.dcache.ReadReq_miss_latency::total 44154787210 # number of ReadReq miss cycles 676system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26046845450 # number of WriteReq miss cycles 677system.cpu0.dcache.WriteReq_miss_latency::total 26046845450 # number of WriteReq miss cycles 678system.cpu0.dcache.WriteInvalidateReq_miss_latency::cpu0.data 30884044772 # number of WriteInvalidateReq miss cycles 679system.cpu0.dcache.WriteInvalidateReq_miss_latency::total 30884044772 # number of WriteInvalidateReq miss cycles 680system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2257944026 # number of LoadLockedReq miss cycles 681system.cpu0.dcache.LoadLockedReq_miss_latency::total 2257944026 # number of LoadLockedReq miss cycles 682system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4202199390 # number of StoreCondReq miss cycles 683system.cpu0.dcache.StoreCondReq_miss_latency::total 4202199390 # number of StoreCondReq miss cycles 684system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2186500 # number of StoreCondFailReq miss cycles 685system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2186500 # number of StoreCondFailReq miss cycles 686system.cpu0.dcache.demand_miss_latency::cpu0.data 70201632660 # number of demand (read+write) miss cycles 687system.cpu0.dcache.demand_miss_latency::total 70201632660 # number of demand (read+write) miss cycles 688system.cpu0.dcache.overall_miss_latency::cpu0.data 70201632660 # number of overall miss cycles 689system.cpu0.dcache.overall_miss_latency::total 70201632660 # number of overall miss cycles 690system.cpu0.dcache.ReadReq_accesses::cpu0.data 80960876 # number of ReadReq accesses(hits+misses) 691system.cpu0.dcache.ReadReq_accesses::total 80960876 # number of ReadReq accesses(hits+misses) 692system.cpu0.dcache.WriteReq_accesses::cpu0.data 73037103 # number of WriteReq accesses(hits+misses) 693system.cpu0.dcache.WriteReq_accesses::total 73037103 # number of WriteReq accesses(hits+misses) 694system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 805382 # number of SoftPFReq accesses(hits+misses) 695system.cpu0.dcache.SoftPFReq_accesses::total 805382 # number of SoftPFReq accesses(hits+misses) 696system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 870443 # number of WriteInvalidateReq accesses(hits+misses) 697system.cpu0.dcache.WriteInvalidateReq_accesses::total 870443 # number of WriteInvalidateReq accesses(hits+misses) 698system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1984536 # number of LoadLockedReq accesses(hits+misses) 699system.cpu0.dcache.LoadLockedReq_accesses::total 1984536 # number of LoadLockedReq accesses(hits+misses) 700system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1983161 # number of StoreCondReq accesses(hits+misses) 701system.cpu0.dcache.StoreCondReq_accesses::total 1983161 # number of StoreCondReq accesses(hits+misses) 702system.cpu0.dcache.demand_accesses::cpu0.data 153997979 # number of demand (read+write) accesses 703system.cpu0.dcache.demand_accesses::total 153997979 # number of demand (read+write) accesses 704system.cpu0.dcache.overall_accesses::cpu0.data 154803361 # number of overall (read+write) accesses 705system.cpu0.dcache.overall_accesses::total 154803361 # number of overall (read+write) accesses 706system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036614 # miss rate for ReadReq accesses 707system.cpu0.dcache.ReadReq_miss_rate::total 0.036614 # miss rate for ReadReq accesses 708system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018389 # miss rate for WriteReq accesses 709system.cpu0.dcache.WriteReq_miss_rate::total 0.018389 # miss rate for WriteReq accesses 710system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.766816 # miss rate for SoftPFReq accesses 711system.cpu0.dcache.SoftPFReq_miss_rate::total 0.766816 # miss rate for SoftPFReq accesses 712system.cpu0.dcache.WriteInvalidateReq_miss_rate::cpu0.data 0.849172 # miss rate for WriteInvalidateReq accesses 713system.cpu0.dcache.WriteInvalidateReq_miss_rate::total 0.849172 # miss rate for WriteInvalidateReq accesses 714system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.077118 # miss rate for LoadLockedReq accesses 715system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.077118 # miss rate for LoadLockedReq accesses 716system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.098473 # miss rate for StoreCondReq accesses 717system.cpu0.dcache.StoreCondReq_miss_rate::total 0.098473 # miss rate for StoreCondReq accesses 718system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027970 # miss rate for demand accesses 719system.cpu0.dcache.demand_miss_rate::total 0.027970 # miss rate for demand accesses 720system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031814 # miss rate for overall accesses 721system.cpu0.dcache.overall_miss_rate::total 0.031814 # miss rate for overall accesses 722system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14895.393457 # average ReadReq miss latency 723system.cpu0.dcache.ReadReq_avg_miss_latency::total 14895.393457 # average ReadReq miss latency 724system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19393.570718 # average WriteReq miss latency 725system.cpu0.dcache.WriteReq_avg_miss_latency::total 19393.570718 # average WriteReq miss latency 726system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::cpu0.data 41782.850673 # average WriteInvalidateReq miss latency 727system.cpu0.dcache.WriteInvalidateReq_avg_miss_latency::total 41782.850673 # average WriteInvalidateReq miss latency 728system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14753.657639 # average LoadLockedReq miss latency 729system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14753.657639 # average LoadLockedReq miss latency 730system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21517.960090 # average StoreCondReq miss latency 731system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21517.960090 # average StoreCondReq miss latency 732system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 733system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 734system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 16297.947565 # average overall miss latency 735system.cpu0.dcache.demand_avg_miss_latency::total 16297.947565 # average overall miss latency 736system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14254.222545 # average overall miss latency 737system.cpu0.dcache.overall_avg_miss_latency::total 14254.222545 # average overall miss latency 738system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 739system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 740system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 741system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked 742system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 743system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 744system.cpu0.dcache.fast_writes 0 # number of fast writes performed 745system.cpu0.dcache.cache_copies 0 # number of cache copies performed 746system.cpu0.dcache.writebacks::writebacks 3655915 # number of writebacks 747system.cpu0.dcache.writebacks::total 3655915 # number of writebacks 748system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 33290 # number of ReadReq MSHR hits 749system.cpu0.dcache.ReadReq_mshr_hits::total 33290 # number of ReadReq MSHR hits 750system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21376 # number of WriteReq MSHR hits 751system.cpu0.dcache.WriteReq_mshr_hits::total 21376 # number of WriteReq MSHR hits 752system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 42886 # number of LoadLockedReq MSHR hits 753system.cpu0.dcache.LoadLockedReq_mshr_hits::total 42886 # number of LoadLockedReq MSHR hits 754system.cpu0.dcache.demand_mshr_hits::cpu0.data 54666 # number of demand (read+write) MSHR hits 755system.cpu0.dcache.demand_mshr_hits::total 54666 # number of demand (read+write) MSHR hits 756system.cpu0.dcache.overall_mshr_hits::cpu0.data 54666 # number of overall MSHR hits 757system.cpu0.dcache.overall_mshr_hits::total 54666 # number of overall MSHR hits 758system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2931035 # number of ReadReq MSHR misses 759system.cpu0.dcache.ReadReq_mshr_misses::total 2931035 # number of ReadReq MSHR misses 760system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1321690 # number of WriteReq MSHR misses 761system.cpu0.dcache.WriteReq_mshr_misses::total 1321690 # number of WriteReq MSHR misses 762system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 611921 # number of SoftPFReq MSHR misses 763system.cpu0.dcache.SoftPFReq_mshr_misses::total 611921 # number of SoftPFReq MSHR misses 764system.cpu0.dcache.WriteInvalidateReq_mshr_misses::cpu0.data 739156 # number of WriteInvalidateReq MSHR misses 765system.cpu0.dcache.WriteInvalidateReq_mshr_misses::total 739156 # number of WriteInvalidateReq MSHR misses 766system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 110157 # number of LoadLockedReq MSHR misses 767system.cpu0.dcache.LoadLockedReq_mshr_misses::total 110157 # number of LoadLockedReq MSHR misses 768system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 195288 # number of StoreCondReq MSHR misses 769system.cpu0.dcache.StoreCondReq_mshr_misses::total 195288 # number of StoreCondReq MSHR misses 770system.cpu0.dcache.demand_mshr_misses::cpu0.data 4252725 # number of demand (read+write) MSHR misses 771system.cpu0.dcache.demand_mshr_misses::total 4252725 # number of demand (read+write) MSHR misses 772system.cpu0.dcache.overall_mshr_misses::cpu0.data 4864646 # number of overall MSHR misses 773system.cpu0.dcache.overall_mshr_misses::total 4864646 # number of overall MSHR misses 774system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable 775system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16584 # number of ReadReq MSHR uncacheable 776system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable 777system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18033 # number of WriteReq MSHR uncacheable 778system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses 779system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34617 # number of overall MSHR uncacheable misses 780system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 38329059920 # number of ReadReq MSHR miss cycles 781system.cpu0.dcache.ReadReq_mshr_miss_latency::total 38329059920 # number of ReadReq MSHR miss cycles 782system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 23455096050 # number of WriteReq MSHR miss cycles 783system.cpu0.dcache.WriteReq_mshr_miss_latency::total 23455096050 # number of WriteReq MSHR miss cycles 784system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 13388812156 # number of SoftPFReq MSHR miss cycles 785system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13388812156 # number of SoftPFReq MSHR miss cycles 786system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 29772038228 # number of WriteInvalidateReq MSHR miss cycles 787system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 29772038228 # number of WriteInvalidateReq MSHR miss cycles 788system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1440580476 # number of LoadLockedReq MSHR miss cycles 789system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1440580476 # number of LoadLockedReq MSHR miss cycles 790system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3899742610 # number of StoreCondReq MSHR miss cycles 791system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3899742610 # number of StoreCondReq MSHR miss cycles 792system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2117500 # number of StoreCondFailReq MSHR miss cycles 793system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2117500 # number of StoreCondFailReq MSHR miss cycles 794system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 61784155970 # number of demand (read+write) MSHR miss cycles 795system.cpu0.dcache.demand_mshr_miss_latency::total 61784155970 # number of demand (read+write) MSHR miss cycles 796system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 75172968126 # number of overall MSHR miss cycles 797system.cpu0.dcache.overall_mshr_miss_latency::total 75172968126 # number of overall MSHR miss cycles 798system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2701006250 # number of ReadReq MSHR uncacheable cycles 799system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2701006250 # number of ReadReq MSHR uncacheable cycles 800system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2792188500 # number of WriteReq MSHR uncacheable cycles 801system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2792188500 # number of WriteReq MSHR uncacheable cycles 802system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 5493194750 # number of overall MSHR uncacheable cycles 803system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5493194750 # number of overall MSHR uncacheable cycles 804system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036203 # mshr miss rate for ReadReq accesses 805system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036203 # mshr miss rate for ReadReq accesses 806system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018096 # mshr miss rate for WriteReq accesses 807system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018096 # mshr miss rate for WriteReq accesses 808system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.759790 # mshr miss rate for SoftPFReq accesses 809system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.759790 # mshr miss rate for SoftPFReq accesses 810system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.849172 # mshr miss rate for WriteInvalidateReq accesses 811system.cpu0.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.849172 # mshr miss rate for WriteInvalidateReq accesses 812system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055508 # mshr miss rate for LoadLockedReq accesses 813system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055508 # mshr miss rate for LoadLockedReq accesses 814system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.098473 # mshr miss rate for StoreCondReq accesses 815system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.098473 # mshr miss rate for StoreCondReq accesses 816system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027615 # mshr miss rate for demand accesses 817system.cpu0.dcache.demand_mshr_miss_rate::total 0.027615 # mshr miss rate for demand accesses 818system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031425 # mshr miss rate for overall accesses 819system.cpu0.dcache.overall_mshr_miss_rate::total 0.031425 # mshr miss rate for overall accesses 820system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13076.971077 # average ReadReq mshr miss latency 821system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13076.971077 # average ReadReq mshr miss latency 822system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17746.291528 # average WriteReq mshr miss latency 823system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17746.291528 # average WriteReq mshr miss latency 824system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 21879.968421 # average SoftPFReq mshr miss latency 825system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 21879.968421 # average SoftPFReq mshr miss latency 826system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 40278.423267 # average WriteInvalidateReq mshr miss latency 827system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 40278.423267 # average WriteInvalidateReq mshr miss latency 828system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 13077.520956 # average LoadLockedReq mshr miss latency 829system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13077.520956 # average LoadLockedReq mshr miss latency 830system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19969.187098 # average StoreCondReq mshr miss latency 831system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19969.187098 # average StoreCondReq mshr miss latency 832system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 833system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 834system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14528.133366 # average overall mshr miss latency 835system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14528.133366 # average overall mshr miss latency 836system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15452.916435 # average overall mshr miss latency 837system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15452.916435 # average overall mshr miss latency 838system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 162868.201278 # average ReadReq mshr uncacheable latency 839system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 162868.201278 # average ReadReq mshr uncacheable latency 840system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 154837.714191 # average WriteReq mshr uncacheable latency 841system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154837.714191 # average WriteReq mshr uncacheable latency 842system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 158684.887483 # average overall mshr uncacheable latency 843system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 158684.887483 # average overall mshr uncacheable latency 844system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 845system.cpu0.icache.tags.replacements 5032307 # number of replacements 846system.cpu0.icache.tags.tagsinuse 511.899757 # Cycle average of tags in use 847system.cpu0.icache.tags.total_refs 439089613 # Total number of references to valid blocks. 848system.cpu0.icache.tags.sampled_refs 5032819 # Sample count of references to valid blocks. 849system.cpu0.icache.tags.avg_refs 87.245262 # Average number of references to valid blocks. 850system.cpu0.icache.tags.warmup_cycle 33435686250 # Cycle when the warmup percentage was hit. 851system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.899757 # Average occupied blocks per requestor 852system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999804 # Average percentage of cache occupancy 853system.cpu0.icache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy 854system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 855system.cpu0.icache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 856system.cpu0.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id 857system.cpu0.icache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id 858system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 859system.cpu0.icache.tags.tag_accesses 893277683 # Number of tag accesses 860system.cpu0.icache.tags.data_accesses 893277683 # Number of data accesses 861system.cpu0.icache.ReadReq_hits::cpu0.inst 439089613 # number of ReadReq hits 862system.cpu0.icache.ReadReq_hits::total 439089613 # number of ReadReq hits 863system.cpu0.icache.demand_hits::cpu0.inst 439089613 # number of demand (read+write) hits 864system.cpu0.icache.demand_hits::total 439089613 # number of demand (read+write) hits 865system.cpu0.icache.overall_hits::cpu0.inst 439089613 # number of overall hits 866system.cpu0.icache.overall_hits::total 439089613 # number of overall hits 867system.cpu0.icache.ReadReq_misses::cpu0.inst 5032819 # number of ReadReq misses 868system.cpu0.icache.ReadReq_misses::total 5032819 # number of ReadReq misses 869system.cpu0.icache.demand_misses::cpu0.inst 5032819 # number of demand (read+write) misses 870system.cpu0.icache.demand_misses::total 5032819 # number of demand (read+write) misses 871system.cpu0.icache.overall_misses::cpu0.inst 5032819 # number of overall misses 872system.cpu0.icache.overall_misses::total 5032819 # number of overall misses 873system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 52854361147 # number of ReadReq miss cycles 874system.cpu0.icache.ReadReq_miss_latency::total 52854361147 # number of ReadReq miss cycles 875system.cpu0.icache.demand_miss_latency::cpu0.inst 52854361147 # number of demand (read+write) miss cycles 876system.cpu0.icache.demand_miss_latency::total 52854361147 # number of demand (read+write) miss cycles 877system.cpu0.icache.overall_miss_latency::cpu0.inst 52854361147 # number of overall miss cycles 878system.cpu0.icache.overall_miss_latency::total 52854361147 # number of overall miss cycles 879system.cpu0.icache.ReadReq_accesses::cpu0.inst 444122432 # number of ReadReq accesses(hits+misses) 880system.cpu0.icache.ReadReq_accesses::total 444122432 # number of ReadReq accesses(hits+misses) 881system.cpu0.icache.demand_accesses::cpu0.inst 444122432 # number of demand (read+write) accesses 882system.cpu0.icache.demand_accesses::total 444122432 # number of demand (read+write) accesses 883system.cpu0.icache.overall_accesses::cpu0.inst 444122432 # number of overall (read+write) accesses 884system.cpu0.icache.overall_accesses::total 444122432 # number of overall (read+write) accesses 885system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.011332 # miss rate for ReadReq accesses 886system.cpu0.icache.ReadReq_miss_rate::total 0.011332 # miss rate for ReadReq accesses 887system.cpu0.icache.demand_miss_rate::cpu0.inst 0.011332 # miss rate for demand accesses 888system.cpu0.icache.demand_miss_rate::total 0.011332 # miss rate for demand accesses 889system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011332 # miss rate for overall accesses 890system.cpu0.icache.overall_miss_rate::total 0.011332 # miss rate for overall accesses 891system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10501.939598 # average ReadReq miss latency 892system.cpu0.icache.ReadReq_avg_miss_latency::total 10501.939598 # average ReadReq miss latency 893system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10501.939598 # average overall miss latency 894system.cpu0.icache.demand_avg_miss_latency::total 10501.939598 # average overall miss latency 895system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10501.939598 # average overall miss latency 896system.cpu0.icache.overall_avg_miss_latency::total 10501.939598 # average overall miss latency 897system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 898system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 899system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked 900system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked 901system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 902system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 903system.cpu0.icache.fast_writes 0 # number of fast writes performed 904system.cpu0.icache.cache_copies 0 # number of cache copies performed 905system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 5032819 # number of ReadReq MSHR misses 906system.cpu0.icache.ReadReq_mshr_misses::total 5032819 # number of ReadReq MSHR misses 907system.cpu0.icache.demand_mshr_misses::cpu0.inst 5032819 # number of demand (read+write) MSHR misses 908system.cpu0.icache.demand_mshr_misses::total 5032819 # number of demand (read+write) MSHR misses 909system.cpu0.icache.overall_mshr_misses::cpu0.inst 5032819 # number of overall MSHR misses 910system.cpu0.icache.overall_mshr_misses::total 5032819 # number of overall MSHR misses 911system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 912system.cpu0.icache.ReadReq_mshr_uncacheable::total 43125 # number of ReadReq MSHR uncacheable 913system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 914system.cpu0.icache.overall_mshr_uncacheable_misses::total 43125 # number of overall MSHR uncacheable misses 915system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 47804251855 # number of ReadReq MSHR miss cycles 916system.cpu0.icache.ReadReq_mshr_miss_latency::total 47804251855 # number of ReadReq MSHR miss cycles 917system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 47804251855 # number of demand (read+write) MSHR miss cycles 918system.cpu0.icache.demand_mshr_miss_latency::total 47804251855 # number of demand (read+write) MSHR miss cycles 919system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 47804251855 # number of overall MSHR miss cycles 920system.cpu0.icache.overall_mshr_miss_latency::total 47804251855 # number of overall MSHR miss cycles 921system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of ReadReq MSHR uncacheable cycles 922system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 3811870500 # number of ReadReq MSHR uncacheable cycles 923system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 3811870500 # number of overall MSHR uncacheable cycles 924system.cpu0.icache.overall_mshr_uncacheable_latency::total 3811870500 # number of overall MSHR uncacheable cycles 925system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for ReadReq accesses 926system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.011332 # mshr miss rate for ReadReq accesses 927system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for demand accesses 928system.cpu0.icache.demand_mshr_miss_rate::total 0.011332 # mshr miss rate for demand accesses 929system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.011332 # mshr miss rate for overall accesses 930system.cpu0.icache.overall_mshr_miss_rate::total 0.011332 # mshr miss rate for overall accesses 931system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average ReadReq mshr miss latency 932system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9498.504090 # average ReadReq mshr miss latency 933system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average overall mshr miss latency 934system.cpu0.icache.demand_avg_mshr_miss_latency::total 9498.504090 # average overall mshr miss latency 935system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9498.504090 # average overall mshr miss latency 936system.cpu0.icache.overall_avg_mshr_miss_latency::total 9498.504090 # average overall mshr miss latency 937system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000 # average ReadReq mshr uncacheable latency 938system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88391.200000 # average ReadReq mshr uncacheable latency 939system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88391.200000 # average overall mshr uncacheable latency 940system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88391.200000 # average overall mshr uncacheable latency 941system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate 942system.cpu0.l2cache.prefetcher.num_hwpf_issued 7211191 # number of hwpf issued 943system.cpu0.l2cache.prefetcher.pfIdentified 7211221 # number of prefetch candidates identified 944system.cpu0.l2cache.prefetcher.pfBufferHit 21 # number of redundant prefetches already in prefetch queue 945system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 946system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 947system.cpu0.l2cache.prefetcher.pfSpanPage 945331 # number of prefetches not generated due to page crossing 948system.cpu0.l2cache.tags.replacements 2374120 # number of replacements 949system.cpu0.l2cache.tags.tagsinuse 16169.428044 # Cycle average of tags in use 950system.cpu0.l2cache.tags.total_refs 10531211 # Total number of references to valid blocks. 951system.cpu0.l2cache.tags.sampled_refs 2389368 # Sample count of references to valid blocks. 952system.cpu0.l2cache.tags.avg_refs 4.407530 # Average number of references to valid blocks. 953system.cpu0.l2cache.tags.warmup_cycle 5341335500 # Cycle when the warmup percentage was hit. 954system.cpu0.l2cache.tags.occ_blocks::writebacks 8264.618229 # Average occupied blocks per requestor 955system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 69.150581 # Average occupied blocks per requestor 956system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 77.449352 # Average occupied blocks per requestor 957system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3311.410043 # Average occupied blocks per requestor 958system.cpu0.l2cache.tags.occ_blocks::cpu0.data 3382.587139 # Average occupied blocks per requestor 959system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1064.212699 # Average occupied blocks per requestor 960system.cpu0.l2cache.tags.occ_percent::writebacks 0.504432 # Average percentage of cache occupancy 961system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004221 # Average percentage of cache occupancy 962system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.004727 # Average percentage of cache occupancy 963system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.202112 # Average percentage of cache occupancy 964system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.206457 # Average percentage of cache occupancy 965system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.064954 # Average percentage of cache occupancy 966system.cpu0.l2cache.tags.occ_percent::total 0.986904 # Average percentage of cache occupancy 967system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1373 # Occupied blocks per task id 968system.cpu0.l2cache.tags.occ_task_id_blocks::1023 85 # Occupied blocks per task id 969system.cpu0.l2cache.tags.occ_task_id_blocks::1024 13790 # Occupied blocks per task id 970system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 971system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 173 # Occupied blocks per task id 972system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 780 # Occupied blocks per task id 973system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 417 # Occupied blocks per task id 974system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 54 # Occupied blocks per task id 975system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 15 # Occupied blocks per task id 976system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id 977system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id 978system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3709 # Occupied blocks per task id 979system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6679 # Occupied blocks per task id 980system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3275 # Occupied blocks per task id 981system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.083801 # Percentage of cache occupancy per task id 982system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005188 # Percentage of cache occupancy per task id 983system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.841675 # Percentage of cache occupancy per task id 984system.cpu0.l2cache.tags.tag_accesses 244043620 # Number of tag accesses 985system.cpu0.l2cache.tags.data_accesses 244043620 # Number of data accesses 986system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 211402 # number of ReadReq hits 987system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 128647 # number of ReadReq hits 988system.cpu0.l2cache.ReadReq_hits::cpu0.inst 4517111 # number of ReadReq hits 989system.cpu0.l2cache.ReadReq_hits::cpu0.data 2702351 # number of ReadReq hits 990system.cpu0.l2cache.ReadReq_hits::total 7559511 # number of ReadReq hits 991system.cpu0.l2cache.Writeback_hits::writebacks 3655914 # number of Writeback hits 992system.cpu0.l2cache.Writeback_hits::total 3655914 # number of Writeback hits 993system.cpu0.l2cache.WriteInvalidateReq_hits::cpu0.data 175642 # number of WriteInvalidateReq hits 994system.cpu0.l2cache.WriteInvalidateReq_hits::total 175642 # number of WriteInvalidateReq hits 995system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 102383 # number of UpgradeReq hits 996system.cpu0.l2cache.UpgradeReq_hits::total 102383 # number of UpgradeReq hits 997system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 30801 # number of SCUpgradeReq hits 998system.cpu0.l2cache.SCUpgradeReq_hits::total 30801 # number of SCUpgradeReq hits 999system.cpu0.l2cache.ReadExReq_hits::cpu0.data 876779 # number of ReadExReq hits 1000system.cpu0.l2cache.ReadExReq_hits::total 876779 # number of ReadExReq hits 1001system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 211402 # number of demand (read+write) hits 1002system.cpu0.l2cache.demand_hits::cpu0.itb.walker 128647 # number of demand (read+write) hits 1003system.cpu0.l2cache.demand_hits::cpu0.inst 4517111 # number of demand (read+write) hits 1004system.cpu0.l2cache.demand_hits::cpu0.data 3579130 # number of demand (read+write) hits 1005system.cpu0.l2cache.demand_hits::total 8436290 # number of demand (read+write) hits 1006system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 211402 # number of overall hits 1007system.cpu0.l2cache.overall_hits::cpu0.itb.walker 128647 # number of overall hits 1008system.cpu0.l2cache.overall_hits::cpu0.inst 4517111 # number of overall hits 1009system.cpu0.l2cache.overall_hits::cpu0.data 3579130 # number of overall hits 1010system.cpu0.l2cache.overall_hits::total 8436290 # number of overall hits 1011system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 10881 # number of ReadReq misses 1012system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 8892 # number of ReadReq misses 1013system.cpu0.l2cache.ReadReq_misses::cpu0.inst 515708 # number of ReadReq misses 1014system.cpu0.l2cache.ReadReq_misses::cpu0.data 950762 # number of ReadReq misses 1015system.cpu0.l2cache.ReadReq_misses::total 1486243 # number of ReadReq misses 1016system.cpu0.l2cache.WriteInvalidateReq_misses::cpu0.data 562136 # number of WriteInvalidateReq misses 1017system.cpu0.l2cache.WriteInvalidateReq_misses::total 562136 # number of WriteInvalidateReq misses 1018system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 120119 # number of UpgradeReq misses 1019system.cpu0.l2cache.UpgradeReq_misses::total 120119 # number of UpgradeReq misses 1020system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 164484 # number of SCUpgradeReq misses 1021system.cpu0.l2cache.SCUpgradeReq_misses::total 164484 # number of SCUpgradeReq misses 1022system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 3 # number of SCUpgradeFailReq misses 1023system.cpu0.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses 1024system.cpu0.l2cache.ReadExReq_misses::cpu0.data 240029 # number of ReadExReq misses 1025system.cpu0.l2cache.ReadExReq_misses::total 240029 # number of ReadExReq misses 1026system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 10881 # number of demand (read+write) misses 1027system.cpu0.l2cache.demand_misses::cpu0.itb.walker 8892 # number of demand (read+write) misses 1028system.cpu0.l2cache.demand_misses::cpu0.inst 515708 # number of demand (read+write) misses 1029system.cpu0.l2cache.demand_misses::cpu0.data 1190791 # number of demand (read+write) misses 1030system.cpu0.l2cache.demand_misses::total 1726272 # number of demand (read+write) misses 1031system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 10881 # number of overall misses 1032system.cpu0.l2cache.overall_misses::cpu0.itb.walker 8892 # number of overall misses 1033system.cpu0.l2cache.overall_misses::cpu0.inst 515708 # number of overall misses 1034system.cpu0.l2cache.overall_misses::cpu0.data 1190791 # number of overall misses 1035system.cpu0.l2cache.overall_misses::total 1726272 # number of overall misses 1036system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 393469249 # number of ReadReq miss cycles 1037system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 355451999 # number of ReadReq miss cycles 1038system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 15907969852 # number of ReadReq miss cycles 1039system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 31938942740 # number of ReadReq miss cycles 1040system.cpu0.l2cache.ReadReq_miss_latency::total 48595833840 # number of ReadReq miss cycles 1041system.cpu0.l2cache.WriteInvalidateReq_miss_latency::cpu0.data 181717619 # number of WriteInvalidateReq miss cycles 1042system.cpu0.l2cache.WriteInvalidateReq_miss_latency::total 181717619 # number of WriteInvalidateReq miss cycles 1043system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 2563026586 # number of UpgradeReq miss cycles 1044system.cpu0.l2cache.UpgradeReq_miss_latency::total 2563026586 # number of UpgradeReq miss cycles 1045system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 3399427212 # number of SCUpgradeReq miss cycles 1046system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 3399427212 # number of SCUpgradeReq miss cycles 1047system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2070498 # number of SCUpgradeFailReq miss cycles 1048system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2070498 # number of SCUpgradeFailReq miss cycles 1049system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 12166293140 # number of ReadExReq miss cycles 1050system.cpu0.l2cache.ReadExReq_miss_latency::total 12166293140 # number of ReadExReq miss cycles 1051system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 393469249 # number of demand (read+write) miss cycles 1052system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 355451999 # number of demand (read+write) miss cycles 1053system.cpu0.l2cache.demand_miss_latency::cpu0.inst 15907969852 # number of demand (read+write) miss cycles 1054system.cpu0.l2cache.demand_miss_latency::cpu0.data 44105235880 # number of demand (read+write) miss cycles 1055system.cpu0.l2cache.demand_miss_latency::total 60762126980 # number of demand (read+write) miss cycles 1056system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 393469249 # number of overall miss cycles 1057system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 355451999 # number of overall miss cycles 1058system.cpu0.l2cache.overall_miss_latency::cpu0.inst 15907969852 # number of overall miss cycles 1059system.cpu0.l2cache.overall_miss_latency::cpu0.data 44105235880 # number of overall miss cycles 1060system.cpu0.l2cache.overall_miss_latency::total 60762126980 # number of overall miss cycles 1061system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 222283 # number of ReadReq accesses(hits+misses) 1062system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 137539 # number of ReadReq accesses(hits+misses) 1063system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 5032819 # number of ReadReq accesses(hits+misses) 1064system.cpu0.l2cache.ReadReq_accesses::cpu0.data 3653113 # number of ReadReq accesses(hits+misses) 1065system.cpu0.l2cache.ReadReq_accesses::total 9045754 # number of ReadReq accesses(hits+misses) 1066system.cpu0.l2cache.Writeback_accesses::writebacks 3655914 # number of Writeback accesses(hits+misses) 1067system.cpu0.l2cache.Writeback_accesses::total 3655914 # number of Writeback accesses(hits+misses) 1068system.cpu0.l2cache.WriteInvalidateReq_accesses::cpu0.data 737778 # number of WriteInvalidateReq accesses(hits+misses) 1069system.cpu0.l2cache.WriteInvalidateReq_accesses::total 737778 # number of WriteInvalidateReq accesses(hits+misses) 1070system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 222502 # number of UpgradeReq accesses(hits+misses) 1071system.cpu0.l2cache.UpgradeReq_accesses::total 222502 # number of UpgradeReq accesses(hits+misses) 1072system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 195285 # number of SCUpgradeReq accesses(hits+misses) 1073system.cpu0.l2cache.SCUpgradeReq_accesses::total 195285 # number of SCUpgradeReq accesses(hits+misses) 1074system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 3 # number of SCUpgradeFailReq accesses(hits+misses) 1075system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 3 # number of SCUpgradeFailReq accesses(hits+misses) 1076system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1116808 # number of ReadExReq accesses(hits+misses) 1077system.cpu0.l2cache.ReadExReq_accesses::total 1116808 # number of ReadExReq accesses(hits+misses) 1078system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 222283 # number of demand (read+write) accesses 1079system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 137539 # number of demand (read+write) accesses 1080system.cpu0.l2cache.demand_accesses::cpu0.inst 5032819 # number of demand (read+write) accesses 1081system.cpu0.l2cache.demand_accesses::cpu0.data 4769921 # number of demand (read+write) accesses 1082system.cpu0.l2cache.demand_accesses::total 10162562 # number of demand (read+write) accesses 1083system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 222283 # number of overall (read+write) accesses 1084system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 137539 # number of overall (read+write) accesses 1085system.cpu0.l2cache.overall_accesses::cpu0.inst 5032819 # number of overall (read+write) accesses 1086system.cpu0.l2cache.overall_accesses::cpu0.data 4769921 # number of overall (read+write) accesses 1087system.cpu0.l2cache.overall_accesses::total 10162562 # number of overall (read+write) accesses 1088system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for ReadReq accesses 1089system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.064651 # miss rate for ReadReq accesses 1090system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.102469 # miss rate for ReadReq accesses 1091system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.260261 # miss rate for ReadReq accesses 1092system.cpu0.l2cache.ReadReq_miss_rate::total 0.164303 # miss rate for ReadReq accesses 1093system.cpu0.l2cache.WriteInvalidateReq_miss_rate::cpu0.data 0.761931 # miss rate for WriteInvalidateReq accesses 1094system.cpu0.l2cache.WriteInvalidateReq_miss_rate::total 0.761931 # miss rate for WriteInvalidateReq accesses 1095system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.539856 # miss rate for UpgradeReq accesses 1096system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.539856 # miss rate for UpgradeReq accesses 1097system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.842277 # miss rate for SCUpgradeReq accesses 1098system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.842277 # miss rate for SCUpgradeReq accesses 1099system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1100system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1101system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.214924 # miss rate for ReadExReq accesses 1102system.cpu0.l2cache.ReadExReq_miss_rate::total 0.214924 # miss rate for ReadExReq accesses 1103system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for demand accesses 1104system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.064651 # miss rate for demand accesses 1105system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.102469 # miss rate for demand accesses 1106system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.249646 # miss rate for demand accesses 1107system.cpu0.l2cache.demand_miss_rate::total 0.169866 # miss rate for demand accesses 1108system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.048951 # miss rate for overall accesses 1109system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.064651 # miss rate for overall accesses 1110system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.102469 # miss rate for overall accesses 1111system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.249646 # miss rate for overall accesses 1112system.cpu0.l2cache.overall_miss_rate::total 0.169866 # miss rate for overall accesses 1113system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average ReadReq miss latency 1114system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 39974.358862 # average ReadReq miss latency 1115system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30846.854910 # average ReadReq miss latency 1116system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 33592.994609 # average ReadReq miss latency 1117system.cpu0.l2cache.ReadReq_avg_miss_latency::total 32697.098550 # average ReadReq miss latency 1118system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::cpu0.data 323.262732 # average WriteInvalidateReq miss latency 1119system.cpu0.l2cache.WriteInvalidateReq_avg_miss_latency::total 323.262732 # average WriteInvalidateReq miss latency 1120system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 21337.395300 # average UpgradeReq miss latency 1121system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 21337.395300 # average UpgradeReq miss latency 1122system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20667.221201 # average SCUpgradeReq miss latency 1123system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20667.221201 # average SCUpgradeReq miss latency 1124system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 690166 # average SCUpgradeFailReq miss latency 1125system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 690166 # average SCUpgradeFailReq miss latency 1126system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 50686.763433 # average ReadExReq miss latency 1127system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 50686.763433 # average ReadExReq miss latency 1128system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average overall miss latency 1129system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 39974.358862 # average overall miss latency 1130system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30846.854910 # average overall miss latency 1131system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37038.603651 # average overall miss latency 1132system.cpu0.l2cache.demand_avg_miss_latency::total 35198.466395 # average overall miss latency 1133system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36161.129400 # average overall miss latency 1134system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 39974.358862 # average overall miss latency 1135system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30846.854910 # average overall miss latency 1136system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37038.603651 # average overall miss latency 1137system.cpu0.l2cache.overall_avg_miss_latency::total 35198.466395 # average overall miss latency 1138system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1139system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1140system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1141system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1142system.cpu0.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1143system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1144system.cpu0.l2cache.fast_writes 0 # number of fast writes performed 1145system.cpu0.l2cache.cache_copies 0 # number of cache copies performed 1146system.cpu0.l2cache.writebacks::writebacks 1321734 # number of writebacks 1147system.cpu0.l2cache.writebacks::total 1321734 # number of writebacks 1148system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 498 # number of ReadReq MSHR hits 1149system.cpu0.l2cache.ReadReq_mshr_hits::total 498 # number of ReadReq MSHR hits 1150system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6011 # number of ReadExReq MSHR hits 1151system.cpu0.l2cache.ReadExReq_mshr_hits::total 6011 # number of ReadExReq MSHR hits 1152system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6509 # number of demand (read+write) MSHR hits 1153system.cpu0.l2cache.demand_mshr_hits::total 6509 # number of demand (read+write) MSHR hits 1154system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6509 # number of overall MSHR hits 1155system.cpu0.l2cache.overall_mshr_hits::total 6509 # number of overall MSHR hits 1156system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 10881 # number of ReadReq MSHR misses 1157system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 8892 # number of ReadReq MSHR misses 1158system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 515708 # number of ReadReq MSHR misses 1159system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 950264 # number of ReadReq MSHR misses 1160system.cpu0.l2cache.ReadReq_mshr_misses::total 1485745 # number of ReadReq MSHR misses 1161system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 659076 # number of HardPFReq MSHR misses 1162system.cpu0.l2cache.HardPFReq_mshr_misses::total 659076 # number of HardPFReq MSHR misses 1163system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::cpu0.data 562136 # number of WriteInvalidateReq MSHR misses 1164system.cpu0.l2cache.WriteInvalidateReq_mshr_misses::total 562136 # number of WriteInvalidateReq MSHR misses 1165system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 120119 # number of UpgradeReq MSHR misses 1166system.cpu0.l2cache.UpgradeReq_mshr_misses::total 120119 # number of UpgradeReq MSHR misses 1167system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 164484 # number of SCUpgradeReq MSHR misses 1168system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 164484 # number of SCUpgradeReq MSHR misses 1169system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 3 # number of SCUpgradeFailReq MSHR misses 1170system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 3 # number of SCUpgradeFailReq MSHR misses 1171system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 234018 # number of ReadExReq MSHR misses 1172system.cpu0.l2cache.ReadExReq_mshr_misses::total 234018 # number of ReadExReq MSHR misses 1173system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 10881 # number of demand (read+write) MSHR misses 1174system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 8892 # number of demand (read+write) MSHR misses 1175system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 515708 # number of demand (read+write) MSHR misses 1176system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1184282 # number of demand (read+write) MSHR misses 1177system.cpu0.l2cache.demand_mshr_misses::total 1719763 # number of demand (read+write) MSHR misses 1178system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 10881 # number of overall MSHR misses 1179system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 8892 # number of overall MSHR misses 1180system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 515708 # number of overall MSHR misses 1181system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1184282 # number of overall MSHR misses 1182system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 659076 # number of overall MSHR misses 1183system.cpu0.l2cache.overall_mshr_misses::total 2378839 # number of overall MSHR misses 1184system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 1185system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable 1186system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 59709 # number of ReadReq MSHR uncacheable 1187system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable 1188system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18033 # number of WriteReq MSHR uncacheable 1189system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 1190system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses 1191system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 77742 # number of overall MSHR uncacheable misses 1192system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of ReadReq MSHR miss cycles 1193system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 297082001 # number of ReadReq MSHR miss cycles 1194system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 12538366148 # number of ReadReq MSHR miss cycles 1195system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 25676104173 # number of ReadReq MSHR miss cycles 1196system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 38833742573 # number of ReadReq MSHR miss cycles 1197system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 32139076466 # number of HardPFReq MSHR miss cycles 1198system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 32139076466 # number of HardPFReq MSHR miss cycles 1199system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 24223804784 # number of WriteInvalidateReq MSHR miss cycles 1200system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_latency::total 24223804784 # number of WriteInvalidateReq MSHR miss cycles 1201system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 2466827080 # number of UpgradeReq MSHR miss cycles 1202system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 2466827080 # number of UpgradeReq MSHR miss cycles 1203system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 2435399890 # number of SCUpgradeReq MSHR miss cycles 1204system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 2435399890 # number of SCUpgradeReq MSHR miss cycles 1205system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 1771498 # number of SCUpgradeFailReq MSHR miss cycles 1206system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1771498 # number of SCUpgradeFailReq MSHR miss cycles 1207system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 9980703954 # number of ReadExReq MSHR miss cycles 1208system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 9980703954 # number of ReadExReq MSHR miss cycles 1209system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of demand (read+write) MSHR miss cycles 1210system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 297082001 # number of demand (read+write) MSHR miss cycles 1211system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 12538366148 # number of demand (read+write) MSHR miss cycles 1212system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 35656808127 # number of demand (read+write) MSHR miss cycles 1213system.cpu0.l2cache.demand_mshr_miss_latency::total 48814446527 # number of demand (read+write) MSHR miss cycles 1214system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 322190251 # number of overall MSHR miss cycles 1215system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 297082001 # number of overall MSHR miss cycles 1216system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 12538366148 # number of overall MSHR miss cycles 1217system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 35656808127 # number of overall MSHR miss cycles 1218system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 32139076466 # number of overall MSHR miss cycles 1219system.cpu0.l2cache.overall_mshr_miss_latency::total 80953522993 # number of overall MSHR miss cycles 1220system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of ReadReq MSHR uncacheable cycles 1221system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2568327500 # number of ReadReq MSHR uncacheable cycles 1222system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6036578500 # number of ReadReq MSHR uncacheable cycles 1223system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2656940000 # number of WriteReq MSHR uncacheable cycles 1224system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2656940000 # number of WriteReq MSHR uncacheable cycles 1225system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 3468251000 # number of overall MSHR uncacheable cycles 1226system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 5225267500 # number of overall MSHR uncacheable cycles 1227system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 8693518500 # number of overall MSHR uncacheable cycles 1228system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for ReadReq accesses 1229system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for ReadReq accesses 1230system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for ReadReq accesses 1231system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.260124 # mshr miss rate for ReadReq accesses 1232system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.164248 # mshr miss rate for ReadReq accesses 1233system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1234system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1235system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.761931 # mshr miss rate for WriteInvalidateReq accesses 1236system.cpu0.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.761931 # mshr miss rate for WriteInvalidateReq accesses 1237system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.539856 # mshr miss rate for UpgradeReq accesses 1238system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.539856 # mshr miss rate for UpgradeReq accesses 1239system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.842277 # mshr miss rate for SCUpgradeReq accesses 1240system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.842277 # mshr miss rate for SCUpgradeReq accesses 1241system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1242system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1243system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.209542 # mshr miss rate for ReadExReq accesses 1244system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.209542 # mshr miss rate for ReadExReq accesses 1245system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for demand accesses 1246system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for demand accesses 1247system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for demand accesses 1248system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.248281 # mshr miss rate for demand accesses 1249system.cpu0.l2cache.demand_mshr_miss_rate::total 0.169225 # mshr miss rate for demand accesses 1250system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.048951 # mshr miss rate for overall accesses 1251system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.064651 # mshr miss rate for overall accesses 1252system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.102469 # mshr miss rate for overall accesses 1253system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.248281 # mshr miss rate for overall accesses 1254system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1255system.cpu0.l2cache.overall_mshr_miss_rate::total 0.234079 # mshr miss rate for overall accesses 1256system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average ReadReq mshr miss latency 1257system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average ReadReq mshr miss latency 1258system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average ReadReq mshr miss latency 1259system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 27019.969370 # average ReadReq mshr miss latency 1260system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 26137.555619 # average ReadReq mshr miss latency 1261system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779 # average HardPFReq mshr miss latency 1262system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 48763.839779 # average HardPFReq mshr miss latency 1263system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 43092.427427 # average WriteInvalidateReq mshr miss latency 1264system.cpu0.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 43092.427427 # average WriteInvalidateReq mshr miss latency 1265system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20536.526944 # average UpgradeReq mshr miss latency 1266system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20536.526944 # average UpgradeReq mshr miss latency 1267system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14806.302680 # average SCUpgradeReq mshr miss latency 1268system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14806.302680 # average SCUpgradeReq mshr miss latency 1269system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 590499.333333 # average SCUpgradeFailReq mshr miss latency 1270system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 590499.333333 # average SCUpgradeFailReq mshr miss latency 1271system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42649.300285 # average ReadExReq mshr miss latency 1272system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42649.300285 # average ReadExReq mshr miss latency 1273system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average overall mshr miss latency 1274system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average overall mshr miss latency 1275system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average overall mshr miss latency 1276system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 30108.376322 # average overall mshr miss latency 1277system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 28384.403274 # average overall mshr miss latency 1278system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 29610.353001 # average overall mshr miss latency 1279system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 33410.031601 # average overall mshr miss latency 1280system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 24312.917674 # average overall mshr miss latency 1281system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 30108.376322 # average overall mshr miss latency 1282system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 48763.839779 # average overall mshr miss latency 1283system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34030.685975 # average overall mshr miss latency 1284system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average ReadReq mshr uncacheable latency 1285system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 154867.794260 # average ReadReq mshr uncacheable latency 1286system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 101099.976553 # average ReadReq mshr uncacheable latency 1287system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 147337.658737 # average WriteReq mshr uncacheable latency 1288system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 147337.658737 # average WriteReq mshr uncacheable latency 1289system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80423.211594 # average overall mshr uncacheable latency 1290system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 150945.128116 # average overall mshr uncacheable latency 1291system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 111825.248900 # average overall mshr uncacheable latency 1292system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1293system.cpu0.toL2Bus.trans_dist::ReadReq 11389901 # Transaction distribution 1294system.cpu0.toL2Bus.trans_dist::ReadResp 9301467 # Transaction distribution 1295system.cpu0.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution 1296system.cpu0.toL2Bus.trans_dist::WriteResp 18033 # Transaction distribution 1297system.cpu0.toL2Bus.trans_dist::Writeback 3655914 # Transaction distribution 1298system.cpu0.toL2Bus.trans_dist::HardPFReq 950949 # Transaction distribution 1299system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1103178 # Transaction distribution 1300system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 737778 # Transaction distribution 1301system.cpu0.toL2Bus.trans_dist::UpgradeReq 440847 # Transaction distribution 1302system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 362789 # Transaction distribution 1303system.cpu0.toL2Bus.trans_dist::UpgradeResp 484218 # Transaction distribution 1304system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 43 # Transaction distribution 1305system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution 1306system.cpu0.toL2Bus.trans_dist::ReadExReq 1248974 # Transaction distribution 1307system.cpu0.toL2Bus.trans_dist::ReadExResp 1125262 # Transaction distribution 1308system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10151888 # Packet count per connected master and slave (bytes) 1309system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15745151 # Packet count per connected master and slave (bytes) 1310system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 304033 # Packet count per connected master and slave (bytes) 1311system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 517558 # Packet count per connected master and slave (bytes) 1312system.cpu0.toL2Bus.pkt_count::total 26718630 # Packet count per connected master and slave (bytes) 1313system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 322272916 # Cumulative packet size per connected master and slave (bytes) 1314system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 593126965 # Cumulative packet size per connected master and slave (bytes) 1315system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1100312 # Cumulative packet size per connected master and slave (bytes) 1316system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1778264 # Cumulative packet size per connected master and slave (bytes) 1317system.cpu0.toL2Bus.pkt_size::total 918278457 # Cumulative packet size per connected master and slave (bytes) 1318system.cpu0.toL2Bus.snoops 4307980 # Total snoops (count) 1319system.cpu0.toL2Bus.snoop_fanout::samples 19190741 # Request fanout histogram 1320system.cpu0.toL2Bus.snoop_fanout::mean 1.234424 # Request fanout histogram 1321system.cpu0.toL2Bus.snoop_fanout::stdev 0.423639 # Request fanout histogram 1322system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1323system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1324system.cpu0.toL2Bus.snoop_fanout::1 14691964 76.56% 76.56% # Request fanout histogram 1325system.cpu0.toL2Bus.snoop_fanout::2 4498777 23.44% 100.00% # Request fanout histogram 1326system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1327system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1328system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1329system.cpu0.toL2Bus.snoop_fanout::total 19190741 # Request fanout histogram 1330system.cpu0.toL2Bus.reqLayer0.occupancy 11979643994 # Layer occupancy (ticks) 1331system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 1332system.cpu0.toL2Bus.snoopLayer0.occupancy 187059488 # Layer occupancy (ticks) 1333system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1334system.cpu0.toL2Bus.respLayer0.occupancy 7611089646 # Layer occupancy (ticks) 1335system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1336system.cpu0.toL2Bus.respLayer1.occupancy 7824710310 # Layer occupancy (ticks) 1337system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1338system.cpu0.toL2Bus.respLayer2.occupancy 166780001 # Layer occupancy (ticks) 1339system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1340system.cpu0.toL2Bus.respLayer3.occupancy 295551751 # Layer occupancy (ticks) 1341system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1342system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1343system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1344system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1345system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1346system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1347system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1348system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1349system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1350system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1351system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1352system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1353system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1354system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1355system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1356system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1357system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1358system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1359system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1360system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1361system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1362system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1363system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1364system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1365system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1366system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1367system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1368system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1369system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1370system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1371system.cpu1.dtb.walker.walks 115983 # Table walker walks requested 1372system.cpu1.dtb.walker.walksLong 115983 # Table walker walks initiated with long descriptors 1373system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11170 # Level at which table walker walks with long descriptors terminate 1374system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 89969 # Level at which table walker walks with long descriptors terminate 1375system.cpu1.dtb.walker.walksSquashedBefore 19 # Table walks squashed before starting 1376system.cpu1.dtb.walker.walkWaitTime::samples 115964 # Table walker wait (enqueue to first request) latency 1377system.cpu1.dtb.walker.walkWaitTime::mean 0.064675 # Table walker wait (enqueue to first request) latency 1378system.cpu1.dtb.walker.walkWaitTime::stdev 22.024176 # Table walker wait (enqueue to first request) latency 1379system.cpu1.dtb.walker.walkWaitTime::0-511 115963 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1380system.cpu1.dtb.walker.walkWaitTime::7168-7679 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1381system.cpu1.dtb.walker.walkWaitTime::total 115964 # Table walker wait (enqueue to first request) latency 1382system.cpu1.dtb.walker.walkCompletionTime::samples 101158 # Table walker service (enqueue to completion) latency 1383system.cpu1.dtb.walker.walkCompletionTime::mean 19050.238172 # Table walker service (enqueue to completion) latency 1384system.cpu1.dtb.walker.walkCompletionTime::gmean 17171.563979 # Table walker service (enqueue to completion) latency 1385system.cpu1.dtb.walker.walkCompletionTime::stdev 14858.973019 # Table walker service (enqueue to completion) latency 1386system.cpu1.dtb.walker.walkCompletionTime::0-65535 99918 98.77% 98.77% # Table walker service (enqueue to completion) latency 1387system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1061 1.05% 99.82% # Table walker service (enqueue to completion) latency 1388system.cpu1.dtb.walker.walkCompletionTime::131072-196607 33 0.03% 99.86% # Table walker service (enqueue to completion) latency 1389system.cpu1.dtb.walker.walkCompletionTime::196608-262143 72 0.07% 99.93% # Table walker service (enqueue to completion) latency 1390system.cpu1.dtb.walker.walkCompletionTime::262144-327679 53 0.05% 99.98% # Table walker service (enqueue to completion) latency 1391system.cpu1.dtb.walker.walkCompletionTime::327680-393215 11 0.01% 99.99% # Table walker service (enqueue to completion) latency 1392system.cpu1.dtb.walker.walkCompletionTime::393216-458751 4 0.00% 99.99% # Table walker service (enqueue to completion) latency 1393system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1394system.cpu1.dtb.walker.walkCompletionTime::524288-589823 3 0.00% 100.00% # Table walker service (enqueue to completion) latency 1395system.cpu1.dtb.walker.walkCompletionTime::total 101158 # Table walker service (enqueue to completion) latency 1396system.cpu1.dtb.walker.walksPending::samples 3223072220 # Table walker pending requests distribution 1397system.cpu1.dtb.walker.walksPending::mean 0.344065 # Table walker pending requests distribution 1398system.cpu1.dtb.walker.walksPending::stdev 0.475063 # Table walker pending requests distribution 1399system.cpu1.dtb.walker.walksPending::0 2114124352 65.59% 65.59% # Table walker pending requests distribution 1400system.cpu1.dtb.walker.walksPending::1 1108947868 34.41% 100.00% # Table walker pending requests distribution 1401system.cpu1.dtb.walker.walksPending::total 3223072220 # Table walker pending requests distribution 1402system.cpu1.dtb.walker.walkPageSizes::4K 89969 88.96% 88.96% # Table walker page sizes translated 1403system.cpu1.dtb.walker.walkPageSizes::2M 11170 11.04% 100.00% # Table walker page sizes translated 1404system.cpu1.dtb.walker.walkPageSizes::total 101139 # Table walker page sizes translated 1405system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 115983 # Table walker requests started/completed, data/inst 1406system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1407system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 115983 # Table walker requests started/completed, data/inst 1408system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 101139 # Table walker requests started/completed, data/inst 1409system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1410system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 101139 # Table walker requests started/completed, data/inst 1411system.cpu1.dtb.walker.walkRequestOrigin::total 217122 # Table walker requests started/completed, data/inst 1412system.cpu1.dtb.inst_hits 0 # ITB inst hits 1413system.cpu1.dtb.inst_misses 0 # ITB inst misses 1414system.cpu1.dtb.read_hits 83993689 # DTB read hits 1415system.cpu1.dtb.read_misses 86321 # DTB read misses 1416system.cpu1.dtb.write_hits 76478778 # DTB write hits 1417system.cpu1.dtb.write_misses 29662 # DTB write misses 1418system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed 1419system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1420system.cpu1.dtb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID 1421system.cpu1.dtb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID 1422system.cpu1.dtb.flush_entries 42752 # Number of entries that have been flushed from TLB 1423system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 1424system.cpu1.dtb.prefetch_faults 4958 # Number of TLB faults due to prefetch 1425system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1426system.cpu1.dtb.perms_faults 11385 # Number of TLB faults due to permissions restrictions 1427system.cpu1.dtb.read_accesses 84080010 # DTB read accesses 1428system.cpu1.dtb.write_accesses 76508440 # DTB write accesses 1429system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1430system.cpu1.dtb.hits 160472467 # DTB hits 1431system.cpu1.dtb.misses 115983 # DTB misses 1432system.cpu1.dtb.accesses 160588450 # DTB accesses 1433system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1434system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1435system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1436system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1437system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1438system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1439system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1440system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1441system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1442system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1443system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1444system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1445system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1446system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1447system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1448system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1449system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1450system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1451system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1452system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1453system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1454system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1455system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1456system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1457system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1458system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1459system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1460system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1461system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1462system.cpu1.itb.walker.walks 60651 # Table walker walks requested 1463system.cpu1.itb.walker.walksLong 60651 # Table walker walks initiated with long descriptors 1464system.cpu1.itb.walker.walksLongTerminationLevel::Level2 616 # Level at which table walker walks with long descriptors terminate 1465system.cpu1.itb.walker.walksLongTerminationLevel::Level3 54731 # Level at which table walker walks with long descriptors terminate 1466system.cpu1.itb.walker.walkWaitTime::samples 60651 # Table walker wait (enqueue to first request) latency 1467system.cpu1.itb.walker.walkWaitTime::0 60651 100.00% 100.00% # Table walker wait (enqueue to first request) latency 1468system.cpu1.itb.walker.walkWaitTime::total 60651 # Table walker wait (enqueue to first request) latency 1469system.cpu1.itb.walker.walkCompletionTime::samples 55347 # Table walker service (enqueue to completion) latency 1470system.cpu1.itb.walker.walkCompletionTime::mean 21982.528123 # Table walker service (enqueue to completion) latency 1471system.cpu1.itb.walker.walkCompletionTime::gmean 19135.216139 # Table walker service (enqueue to completion) latency 1472system.cpu1.itb.walker.walkCompletionTime::stdev 20466.687075 # Table walker service (enqueue to completion) latency 1473system.cpu1.itb.walker.walkCompletionTime::0-65535 53969 97.51% 97.51% # Table walker service (enqueue to completion) latency 1474system.cpu1.itb.walker.walkCompletionTime::65536-131071 1178 2.13% 99.64% # Table walker service (enqueue to completion) latency 1475system.cpu1.itb.walker.walkCompletionTime::131072-196607 42 0.08% 99.71% # Table walker service (enqueue to completion) latency 1476system.cpu1.itb.walker.walkCompletionTime::196608-262143 68 0.12% 99.84% # Table walker service (enqueue to completion) latency 1477system.cpu1.itb.walker.walkCompletionTime::262144-327679 60 0.11% 99.95% # Table walker service (enqueue to completion) latency 1478system.cpu1.itb.walker.walkCompletionTime::327680-393215 20 0.04% 99.98% # Table walker service (enqueue to completion) latency 1479system.cpu1.itb.walker.walkCompletionTime::393216-458751 5 0.01% 99.99% # Table walker service (enqueue to completion) latency 1480system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.01% 100.00% # Table walker service (enqueue to completion) latency 1481system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1482system.cpu1.itb.walker.walkCompletionTime::total 55347 # Table walker service (enqueue to completion) latency 1483system.cpu1.itb.walker.walksPending::samples 2053569352 # Table walker pending requests distribution 1484system.cpu1.itb.walker.walksPending::0 2053569352 100.00% 100.00% # Table walker pending requests distribution 1485system.cpu1.itb.walker.walksPending::total 2053569352 # Table walker pending requests distribution 1486system.cpu1.itb.walker.walkPageSizes::4K 54731 98.89% 98.89% # Table walker page sizes translated 1487system.cpu1.itb.walker.walkPageSizes::2M 616 1.11% 100.00% # Table walker page sizes translated 1488system.cpu1.itb.walker.walkPageSizes::total 55347 # Table walker page sizes translated 1489system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1490system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 60651 # Table walker requests started/completed, data/inst 1491system.cpu1.itb.walker.walkRequestOrigin_Requested::total 60651 # Table walker requests started/completed, data/inst 1492system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1493system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 55347 # Table walker requests started/completed, data/inst 1494system.cpu1.itb.walker.walkRequestOrigin_Completed::total 55347 # Table walker requests started/completed, data/inst 1495system.cpu1.itb.walker.walkRequestOrigin::total 115998 # Table walker requests started/completed, data/inst 1496system.cpu1.itb.inst_hits 446979774 # ITB inst hits 1497system.cpu1.itb.inst_misses 60651 # ITB inst misses 1498system.cpu1.itb.read_hits 0 # DTB read hits 1499system.cpu1.itb.read_misses 0 # DTB read misses 1500system.cpu1.itb.write_hits 0 # DTB write hits 1501system.cpu1.itb.write_misses 0 # DTB write misses 1502system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed 1503system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1504system.cpu1.itb.flush_tlb_mva_asid 42080 # Number of times TLB was flushed by MVA & ASID 1505system.cpu1.itb.flush_tlb_asid 1042 # Number of times TLB was flushed by ASID 1506system.cpu1.itb.flush_entries 29800 # Number of entries that have been flushed from TLB 1507system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1508system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1509system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1510system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1511system.cpu1.itb.read_accesses 0 # DTB read accesses 1512system.cpu1.itb.write_accesses 0 # DTB write accesses 1513system.cpu1.itb.inst_accesses 447040425 # ITB inst accesses 1514system.cpu1.itb.hits 446979774 # DTB hits 1515system.cpu1.itb.misses 60651 # DTB misses 1516system.cpu1.itb.accesses 447040425 # DTB accesses 1517system.cpu1.numCycles 95053909934 # number of cpu cycles simulated 1518system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1519system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1520system.cpu1.committedInsts 446673984 # Number of instructions committed 1521system.cpu1.committedOps 525768473 # Number of ops (including micro ops) committed 1522system.cpu1.num_int_alu_accesses 482657433 # Number of integer alu accesses 1523system.cpu1.num_fp_alu_accesses 472663 # Number of float alu accesses 1524system.cpu1.num_func_calls 26533376 # number of times a function call or return occured 1525system.cpu1.num_conditional_control_insts 68272280 # number of instructions that are conditional controls 1526system.cpu1.num_int_insts 482657433 # number of integer instructions 1527system.cpu1.num_fp_insts 472663 # number of float instructions 1528system.cpu1.num_int_register_reads 706740468 # number of times the integer registers were read 1529system.cpu1.num_int_register_writes 383340050 # number of times the integer registers were written 1530system.cpu1.num_fp_register_reads 750974 # number of times the floating registers were read 1531system.cpu1.num_fp_register_writes 430296 # number of times the floating registers were written 1532system.cpu1.num_cc_register_reads 118015071 # number of times the CC registers were read 1533system.cpu1.num_cc_register_writes 117677935 # number of times the CC registers were written 1534system.cpu1.num_mem_refs 160465117 # number of memory refs 1535system.cpu1.num_load_insts 83993061 # Number of load instructions 1536system.cpu1.num_store_insts 76472056 # Number of store instructions 1537system.cpu1.num_idle_cycles 93999959015.450027 # Number of idle cycles 1538system.cpu1.num_busy_cycles 1053950918.549978 # Number of busy cycles 1539system.cpu1.not_idle_fraction 0.011088 # Percentage of non-idle cycles 1540system.cpu1.idle_fraction 0.988912 # Percentage of idle cycles 1541system.cpu1.Branches 99666047 # Number of branches fetched 1542system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction 1543system.cpu1.op_class::IntAlu 364374913 69.26% 69.26% # Class of executed instruction 1544system.cpu1.op_class::IntMult 1108574 0.21% 69.47% # Class of executed instruction 1545system.cpu1.op_class::IntDiv 57501 0.01% 69.48% # Class of executed instruction 1546system.cpu1.op_class::FloatAdd 0 0.00% 69.48% # Class of executed instruction 1547system.cpu1.op_class::FloatCmp 0 0.00% 69.48% # Class of executed instruction 1548system.cpu1.op_class::FloatCvt 0 0.00% 69.48% # Class of executed instruction 1549system.cpu1.op_class::FloatMult 0 0.00% 69.48% # Class of executed instruction 1550system.cpu1.op_class::FloatDiv 0 0.00% 69.48% # Class of executed instruction 1551system.cpu1.op_class::FloatSqrt 0 0.00% 69.48% # Class of executed instruction 1552system.cpu1.op_class::SimdAdd 0 0.00% 69.48% # Class of executed instruction 1553system.cpu1.op_class::SimdAddAcc 0 0.00% 69.48% # Class of executed instruction 1554system.cpu1.op_class::SimdAlu 0 0.00% 69.48% # Class of executed instruction 1555system.cpu1.op_class::SimdCmp 0 0.00% 69.48% # Class of executed instruction 1556system.cpu1.op_class::SimdCvt 0 0.00% 69.48% # Class of executed instruction 1557system.cpu1.op_class::SimdMisc 0 0.00% 69.48% # Class of executed instruction 1558system.cpu1.op_class::SimdMult 0 0.00% 69.48% # Class of executed instruction 1559system.cpu1.op_class::SimdMultAcc 0 0.00% 69.48% # Class of executed instruction 1560system.cpu1.op_class::SimdShift 0 0.00% 69.48% # Class of executed instruction 1561system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.48% # Class of executed instruction 1562system.cpu1.op_class::SimdSqrt 0 0.00% 69.48% # Class of executed instruction 1563system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.48% # Class of executed instruction 1564system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.48% # Class of executed instruction 1565system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.48% # Class of executed instruction 1566system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.48% # Class of executed instruction 1567system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.48% # Class of executed instruction 1568system.cpu1.op_class::SimdFloatMisc 68224 0.01% 69.50% # Class of executed instruction 1569system.cpu1.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction 1570system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction 1571system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction 1572system.cpu1.op_class::MemRead 83993061 15.97% 85.46% # Class of executed instruction 1573system.cpu1.op_class::MemWrite 76472056 14.54% 100.00% # Class of executed instruction 1574system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 1575system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 1576system.cpu1.op_class::total 526074372 # Class of executed instruction 1577system.cpu1.kern.inst.arm 0 # number of arm instructions executed 1578system.cpu1.kern.inst.quiesce 14059 # number of quiesce instructions executed 1579system.cpu1.dcache.tags.replacements 5413042 # number of replacements 1580system.cpu1.dcache.tags.tagsinuse 455.092206 # Cycle average of tags in use 1581system.cpu1.dcache.tags.total_refs 154856630 # Total number of references to valid blocks. 1582system.cpu1.dcache.tags.sampled_refs 5413554 # Sample count of references to valid blocks. 1583system.cpu1.dcache.tags.avg_refs 28.605354 # Average number of references to valid blocks. 1584system.cpu1.dcache.tags.warmup_cycle 8382280704500 # Cycle when the warmup percentage was hit. 1585system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.092206 # Average occupied blocks per requestor 1586system.cpu1.dcache.tags.occ_percent::cpu1.data 0.888852 # Average percentage of cache occupancy 1587system.cpu1.dcache.tags.occ_percent::total 0.888852 # Average percentage of cache occupancy 1588system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1589system.cpu1.dcache.tags.age_task_id_blocks_1024::0 58 # Occupied blocks per task id 1590system.cpu1.dcache.tags.age_task_id_blocks_1024::1 419 # Occupied blocks per task id 1591system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id 1592system.cpu1.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 1593system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1594system.cpu1.dcache.tags.tag_accesses 326337345 # Number of tag accesses 1595system.cpu1.dcache.tags.data_accesses 326337345 # Number of data accesses 1596system.cpu1.dcache.ReadReq_hits::cpu1.data 78172197 # number of ReadReq hits 1597system.cpu1.dcache.ReadReq_hits::total 78172197 # number of ReadReq hits 1598system.cpu1.dcache.WriteReq_hits::cpu1.data 72471418 # number of WriteReq hits 1599system.cpu1.dcache.WriteReq_hits::total 72471418 # number of WriteReq hits 1600system.cpu1.dcache.SoftPFReq_hits::cpu1.data 183858 # number of SoftPFReq hits 1601system.cpu1.dcache.SoftPFReq_hits::total 183858 # number of SoftPFReq hits 1602system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 197039 # number of WriteInvalidateReq hits 1603system.cpu1.dcache.WriteInvalidateReq_hits::total 197039 # number of WriteInvalidateReq hits 1604system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1730902 # number of LoadLockedReq hits 1605system.cpu1.dcache.LoadLockedReq_hits::total 1730902 # number of LoadLockedReq hits 1606system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1704111 # number of StoreCondReq hits 1607system.cpu1.dcache.StoreCondReq_hits::total 1704111 # number of StoreCondReq hits 1608system.cpu1.dcache.demand_hits::cpu1.data 150643615 # number of demand (read+write) hits 1609system.cpu1.dcache.demand_hits::total 150643615 # number of demand (read+write) hits 1610system.cpu1.dcache.overall_hits::cpu1.data 150827473 # number of overall hits 1611system.cpu1.dcache.overall_hits::total 150827473 # number of overall hits 1612system.cpu1.dcache.ReadReq_misses::cpu1.data 3026410 # number of ReadReq misses 1613system.cpu1.dcache.ReadReq_misses::total 3026410 # number of ReadReq misses 1614system.cpu1.dcache.WriteReq_misses::cpu1.data 1374450 # number of WriteReq misses 1615system.cpu1.dcache.WriteReq_misses::total 1374450 # number of WriteReq misses 1616system.cpu1.dcache.SoftPFReq_misses::cpu1.data 681215 # number of SoftPFReq misses 1617system.cpu1.dcache.SoftPFReq_misses::total 681215 # number of SoftPFReq misses 1618system.cpu1.dcache.WriteInvalidateReq_misses::cpu1.data 497314 # number of WriteInvalidateReq misses 1619system.cpu1.dcache.WriteInvalidateReq_misses::total 497314 # number of WriteInvalidateReq misses 1620system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 177400 # number of LoadLockedReq misses 1621system.cpu1.dcache.LoadLockedReq_misses::total 177400 # number of LoadLockedReq misses 1622system.cpu1.dcache.StoreCondReq_misses::cpu1.data 202765 # number of StoreCondReq misses 1623system.cpu1.dcache.StoreCondReq_misses::total 202765 # number of StoreCondReq misses 1624system.cpu1.dcache.demand_misses::cpu1.data 4400860 # number of demand (read+write) misses 1625system.cpu1.dcache.demand_misses::total 4400860 # number of demand (read+write) misses 1626system.cpu1.dcache.overall_misses::cpu1.data 5082075 # number of overall misses 1627system.cpu1.dcache.overall_misses::total 5082075 # number of overall misses 1628system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 44105582717 # number of ReadReq miss cycles 1629system.cpu1.dcache.ReadReq_miss_latency::total 44105582717 # number of ReadReq miss cycles 1630system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 23281173553 # number of WriteReq miss cycles 1631system.cpu1.dcache.WriteReq_miss_latency::total 23281173553 # number of WriteReq miss cycles 1632system.cpu1.dcache.WriteInvalidateReq_miss_latency::cpu1.data 13579881027 # number of WriteInvalidateReq miss cycles 1633system.cpu1.dcache.WriteInvalidateReq_miss_latency::total 13579881027 # number of WriteInvalidateReq miss cycles 1634system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2688373759 # number of LoadLockedReq miss cycles 1635system.cpu1.dcache.LoadLockedReq_miss_latency::total 2688373759 # number of LoadLockedReq miss cycles 1636system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4348203540 # number of StoreCondReq miss cycles 1637system.cpu1.dcache.StoreCondReq_miss_latency::total 4348203540 # number of StoreCondReq miss cycles 1638system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1867000 # number of StoreCondFailReq miss cycles 1639system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1867000 # number of StoreCondFailReq miss cycles 1640system.cpu1.dcache.demand_miss_latency::cpu1.data 67386756270 # number of demand (read+write) miss cycles 1641system.cpu1.dcache.demand_miss_latency::total 67386756270 # number of demand (read+write) miss cycles 1642system.cpu1.dcache.overall_miss_latency::cpu1.data 67386756270 # number of overall miss cycles 1643system.cpu1.dcache.overall_miss_latency::total 67386756270 # number of overall miss cycles 1644system.cpu1.dcache.ReadReq_accesses::cpu1.data 81198607 # number of ReadReq accesses(hits+misses) 1645system.cpu1.dcache.ReadReq_accesses::total 81198607 # number of ReadReq accesses(hits+misses) 1646system.cpu1.dcache.WriteReq_accesses::cpu1.data 73845868 # number of WriteReq accesses(hits+misses) 1647system.cpu1.dcache.WriteReq_accesses::total 73845868 # number of WriteReq accesses(hits+misses) 1648system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 865073 # number of SoftPFReq accesses(hits+misses) 1649system.cpu1.dcache.SoftPFReq_accesses::total 865073 # number of SoftPFReq accesses(hits+misses) 1650system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 694353 # number of WriteInvalidateReq accesses(hits+misses) 1651system.cpu1.dcache.WriteInvalidateReq_accesses::total 694353 # number of WriteInvalidateReq accesses(hits+misses) 1652system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1908302 # number of LoadLockedReq accesses(hits+misses) 1653system.cpu1.dcache.LoadLockedReq_accesses::total 1908302 # number of LoadLockedReq accesses(hits+misses) 1654system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1906876 # number of StoreCondReq accesses(hits+misses) 1655system.cpu1.dcache.StoreCondReq_accesses::total 1906876 # number of StoreCondReq accesses(hits+misses) 1656system.cpu1.dcache.demand_accesses::cpu1.data 155044475 # number of demand (read+write) accesses 1657system.cpu1.dcache.demand_accesses::total 155044475 # number of demand (read+write) accesses 1658system.cpu1.dcache.overall_accesses::cpu1.data 155909548 # number of overall (read+write) accesses 1659system.cpu1.dcache.overall_accesses::total 155909548 # number of overall (read+write) accesses 1660system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037272 # miss rate for ReadReq accesses 1661system.cpu1.dcache.ReadReq_miss_rate::total 0.037272 # miss rate for ReadReq accesses 1662system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018612 # miss rate for WriteReq accesses 1663system.cpu1.dcache.WriteReq_miss_rate::total 0.018612 # miss rate for WriteReq accesses 1664system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.787465 # miss rate for SoftPFReq accesses 1665system.cpu1.dcache.SoftPFReq_miss_rate::total 0.787465 # miss rate for SoftPFReq accesses 1666system.cpu1.dcache.WriteInvalidateReq_miss_rate::cpu1.data 0.716226 # miss rate for WriteInvalidateReq accesses 1667system.cpu1.dcache.WriteInvalidateReq_miss_rate::total 0.716226 # miss rate for WriteInvalidateReq accesses 1668system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.092962 # miss rate for LoadLockedReq accesses 1669system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.092962 # miss rate for LoadLockedReq accesses 1670system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.106334 # miss rate for StoreCondReq accesses 1671system.cpu1.dcache.StoreCondReq_miss_rate::total 0.106334 # miss rate for StoreCondReq accesses 1672system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028385 # miss rate for demand accesses 1673system.cpu1.dcache.demand_miss_rate::total 0.028385 # miss rate for demand accesses 1674system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032596 # miss rate for overall accesses 1675system.cpu1.dcache.overall_miss_rate::total 0.032596 # miss rate for overall accesses 1676system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14573.564956 # average ReadReq miss latency 1677system.cpu1.dcache.ReadReq_avg_miss_latency::total 14573.564956 # average ReadReq miss latency 1678system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 16938.537999 # average WriteReq miss latency 1679system.cpu1.dcache.WriteReq_avg_miss_latency::total 16938.537999 # average WriteReq miss latency 1680system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::cpu1.data 27306.452316 # average WriteInvalidateReq miss latency 1681system.cpu1.dcache.WriteInvalidateReq_avg_miss_latency::total 27306.452316 # average WriteInvalidateReq miss latency 1682system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 15154.305293 # average LoadLockedReq miss latency 1683system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 15154.305293 # average LoadLockedReq miss latency 1684system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21444.546840 # average StoreCondReq miss latency 1685system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21444.546840 # average StoreCondReq miss latency 1686system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 1687system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1688system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15312.179045 # average overall miss latency 1689system.cpu1.dcache.demand_avg_miss_latency::total 15312.179045 # average overall miss latency 1690system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13259.693387 # average overall miss latency 1691system.cpu1.dcache.overall_avg_miss_latency::total 13259.693387 # average overall miss latency 1692system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1693system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1694system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 1695system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked 1696system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1697system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1698system.cpu1.dcache.fast_writes 0 # number of fast writes performed 1699system.cpu1.dcache.cache_copies 0 # number of cache copies performed 1700system.cpu1.dcache.writebacks::writebacks 3550271 # number of writebacks 1701system.cpu1.dcache.writebacks::total 3550271 # number of writebacks 1702system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18006 # number of ReadReq MSHR hits 1703system.cpu1.dcache.ReadReq_mshr_hits::total 18006 # number of ReadReq MSHR hits 1704system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 425 # number of WriteReq MSHR hits 1705system.cpu1.dcache.WriteReq_mshr_hits::total 425 # number of WriteReq MSHR hits 1706system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 44886 # number of LoadLockedReq MSHR hits 1707system.cpu1.dcache.LoadLockedReq_mshr_hits::total 44886 # number of LoadLockedReq MSHR hits 1708system.cpu1.dcache.demand_mshr_hits::cpu1.data 18431 # number of demand (read+write) MSHR hits 1709system.cpu1.dcache.demand_mshr_hits::total 18431 # number of demand (read+write) MSHR hits 1710system.cpu1.dcache.overall_mshr_hits::cpu1.data 18431 # number of overall MSHR hits 1711system.cpu1.dcache.overall_mshr_hits::total 18431 # number of overall MSHR hits 1712system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3008404 # number of ReadReq MSHR misses 1713system.cpu1.dcache.ReadReq_mshr_misses::total 3008404 # number of ReadReq MSHR misses 1714system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1374025 # number of WriteReq MSHR misses 1715system.cpu1.dcache.WriteReq_mshr_misses::total 1374025 # number of WriteReq MSHR misses 1716system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 681215 # number of SoftPFReq MSHR misses 1717system.cpu1.dcache.SoftPFReq_mshr_misses::total 681215 # number of SoftPFReq MSHR misses 1718system.cpu1.dcache.WriteInvalidateReq_mshr_misses::cpu1.data 497314 # number of WriteInvalidateReq MSHR misses 1719system.cpu1.dcache.WriteInvalidateReq_mshr_misses::total 497314 # number of WriteInvalidateReq MSHR misses 1720system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 132514 # number of LoadLockedReq MSHR misses 1721system.cpu1.dcache.LoadLockedReq_mshr_misses::total 132514 # number of LoadLockedReq MSHR misses 1722system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 202765 # number of StoreCondReq MSHR misses 1723system.cpu1.dcache.StoreCondReq_mshr_misses::total 202765 # number of StoreCondReq MSHR misses 1724system.cpu1.dcache.demand_mshr_misses::cpu1.data 4382429 # number of demand (read+write) MSHR misses 1725system.cpu1.dcache.demand_mshr_misses::total 4382429 # number of demand (read+write) MSHR misses 1726system.cpu1.dcache.overall_mshr_misses::cpu1.data 5063644 # number of overall MSHR misses 1727system.cpu1.dcache.overall_mshr_misses::total 5063644 # number of overall MSHR misses 1728system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21725 # number of ReadReq MSHR uncacheable 1729system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21725 # number of ReadReq MSHR uncacheable 1730system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable 1731system.cpu1.dcache.WriteReq_mshr_uncacheable::total 20113 # number of WriteReq MSHR uncacheable 1732system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 41838 # number of overall MSHR uncacheable misses 1733system.cpu1.dcache.overall_mshr_uncacheable_misses::total 41838 # number of overall MSHR uncacheable misses 1734system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38446720676 # number of ReadReq MSHR miss cycles 1735system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38446720676 # number of ReadReq MSHR miss cycles 1736system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 21137642197 # number of WriteReq MSHR miss cycles 1737system.cpu1.dcache.WriteReq_mshr_miss_latency::total 21137642197 # number of WriteReq MSHR miss cycles 1738system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13605784836 # number of SoftPFReq MSHR miss cycles 1739system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13605784836 # number of SoftPFReq MSHR miss cycles 1740system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 12830642973 # number of WriteInvalidateReq MSHR miss cycles 1741system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 12830642973 # number of WriteInvalidateReq MSHR miss cycles 1742system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1690394742 # number of LoadLockedReq MSHR miss cycles 1743system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1690394742 # number of LoadLockedReq MSHR miss cycles 1744system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4033173960 # number of StoreCondReq MSHR miss cycles 1745system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4033173960 # number of StoreCondReq MSHR miss cycles 1746system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1807000 # number of StoreCondFailReq MSHR miss cycles 1747system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1807000 # number of StoreCondFailReq MSHR miss cycles 1748system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 59584362873 # number of demand (read+write) MSHR miss cycles 1749system.cpu1.dcache.demand_mshr_miss_latency::total 59584362873 # number of demand (read+write) MSHR miss cycles 1750system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 73190147709 # number of overall MSHR miss cycles 1751system.cpu1.dcache.overall_mshr_miss_latency::total 73190147709 # number of overall MSHR miss cycles 1752system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3727466501 # number of ReadReq MSHR uncacheable cycles 1753system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3727466501 # number of ReadReq MSHR uncacheable cycles 1754system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3465674500 # number of WriteReq MSHR uncacheable cycles 1755system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3465674500 # number of WriteReq MSHR uncacheable cycles 1756system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7193141001 # number of overall MSHR uncacheable cycles 1757system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7193141001 # number of overall MSHR uncacheable cycles 1758system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037050 # mshr miss rate for ReadReq accesses 1759system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037050 # mshr miss rate for ReadReq accesses 1760system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018607 # mshr miss rate for WriteReq accesses 1761system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018607 # mshr miss rate for WriteReq accesses 1762system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.787465 # mshr miss rate for SoftPFReq accesses 1763system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.787465 # mshr miss rate for SoftPFReq accesses 1764system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.716226 # mshr miss rate for WriteInvalidateReq accesses 1765system.cpu1.dcache.WriteInvalidateReq_mshr_miss_rate::total 0.716226 # mshr miss rate for WriteInvalidateReq accesses 1766system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.069441 # mshr miss rate for LoadLockedReq accesses 1767system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.069441 # mshr miss rate for LoadLockedReq accesses 1768system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.106334 # mshr miss rate for StoreCondReq accesses 1769system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.106334 # mshr miss rate for StoreCondReq accesses 1770system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028266 # mshr miss rate for demand accesses 1771system.cpu1.dcache.demand_mshr_miss_rate::total 0.028266 # mshr miss rate for demand accesses 1772system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032478 # mshr miss rate for overall accesses 1773system.cpu1.dcache.overall_mshr_miss_rate::total 0.032478 # mshr miss rate for overall accesses 1774system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12779.773154 # average ReadReq mshr miss latency 1775system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12779.773154 # average ReadReq mshr miss latency 1776system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15383.739158 # average WriteReq mshr miss latency 1777system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15383.739158 # average WriteReq mshr miss latency 1778system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 19972.820381 # average SoftPFReq mshr miss latency 1779system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 19972.820381 # average SoftPFReq mshr miss latency 1780system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 25799.882917 # average WriteInvalidateReq mshr miss latency 1781system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total 25799.882917 # average WriteInvalidateReq mshr miss latency 1782system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12756.348325 # average LoadLockedReq mshr miss latency 1783system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12756.348325 # average LoadLockedReq mshr miss latency 1784system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19890.878406 # average StoreCondReq mshr miss latency 1785system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19890.878406 # average StoreCondReq mshr miss latency 1786system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 1787system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1788system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13596.195825 # average overall mshr miss latency 1789system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13596.195825 # average overall mshr miss latency 1790system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14454.046870 # average overall mshr miss latency 1791system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14454.046870 # average overall mshr miss latency 1792system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171574.982785 # average ReadReq mshr uncacheable latency 1793system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171574.982785 # average ReadReq mshr uncacheable latency 1794system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 172310.172525 # average WriteReq mshr uncacheable latency 1795system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 172310.172525 # average WriteReq mshr uncacheable latency 1796system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171928.414384 # average overall mshr uncacheable latency 1797system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 171928.414384 # average overall mshr uncacheable latency 1798system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1799system.cpu1.icache.tags.replacements 4892397 # number of replacements 1800system.cpu1.icache.tags.tagsinuse 496.394395 # Cycle average of tags in use 1801system.cpu1.icache.tags.total_refs 442086860 # Total number of references to valid blocks. 1802system.cpu1.icache.tags.sampled_refs 4892909 # Sample count of references to valid blocks. 1803system.cpu1.icache.tags.avg_refs 90.352561 # Average number of references to valid blocks. 1804system.cpu1.icache.tags.warmup_cycle 8382252985250 # Cycle when the warmup percentage was hit. 1805system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.394395 # Average occupied blocks per requestor 1806system.cpu1.icache.tags.occ_percent::cpu1.inst 0.969520 # Average percentage of cache occupancy 1807system.cpu1.icache.tags.occ_percent::total 0.969520 # Average percentage of cache occupancy 1808system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1809system.cpu1.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id 1810system.cpu1.icache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id 1811system.cpu1.icache.tags.age_task_id_blocks_1024::2 151 # Occupied blocks per task id 1812system.cpu1.icache.tags.age_task_id_blocks_1024::3 14 # Occupied blocks per task id 1813system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1814system.cpu1.icache.tags.tag_accesses 898852462 # Number of tag accesses 1815system.cpu1.icache.tags.data_accesses 898852462 # Number of data accesses 1816system.cpu1.icache.ReadReq_hits::cpu1.inst 442086860 # number of ReadReq hits 1817system.cpu1.icache.ReadReq_hits::total 442086860 # number of ReadReq hits 1818system.cpu1.icache.demand_hits::cpu1.inst 442086860 # number of demand (read+write) hits 1819system.cpu1.icache.demand_hits::total 442086860 # number of demand (read+write) hits 1820system.cpu1.icache.overall_hits::cpu1.inst 442086860 # number of overall hits 1821system.cpu1.icache.overall_hits::total 442086860 # number of overall hits 1822system.cpu1.icache.ReadReq_misses::cpu1.inst 4892914 # number of ReadReq misses 1823system.cpu1.icache.ReadReq_misses::total 4892914 # number of ReadReq misses 1824system.cpu1.icache.demand_misses::cpu1.inst 4892914 # number of demand (read+write) misses 1825system.cpu1.icache.demand_misses::total 4892914 # number of demand (read+write) misses 1826system.cpu1.icache.overall_misses::cpu1.inst 4892914 # number of overall misses 1827system.cpu1.icache.overall_misses::total 4892914 # number of overall misses 1828system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 51771462698 # number of ReadReq miss cycles 1829system.cpu1.icache.ReadReq_miss_latency::total 51771462698 # number of ReadReq miss cycles 1830system.cpu1.icache.demand_miss_latency::cpu1.inst 51771462698 # number of demand (read+write) miss cycles 1831system.cpu1.icache.demand_miss_latency::total 51771462698 # number of demand (read+write) miss cycles 1832system.cpu1.icache.overall_miss_latency::cpu1.inst 51771462698 # number of overall miss cycles 1833system.cpu1.icache.overall_miss_latency::total 51771462698 # number of overall miss cycles 1834system.cpu1.icache.ReadReq_accesses::cpu1.inst 446979774 # number of ReadReq accesses(hits+misses) 1835system.cpu1.icache.ReadReq_accesses::total 446979774 # number of ReadReq accesses(hits+misses) 1836system.cpu1.icache.demand_accesses::cpu1.inst 446979774 # number of demand (read+write) accesses 1837system.cpu1.icache.demand_accesses::total 446979774 # number of demand (read+write) accesses 1838system.cpu1.icache.overall_accesses::cpu1.inst 446979774 # number of overall (read+write) accesses 1839system.cpu1.icache.overall_accesses::total 446979774 # number of overall (read+write) accesses 1840system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.010947 # miss rate for ReadReq accesses 1841system.cpu1.icache.ReadReq_miss_rate::total 0.010947 # miss rate for ReadReq accesses 1842system.cpu1.icache.demand_miss_rate::cpu1.inst 0.010947 # miss rate for demand accesses 1843system.cpu1.icache.demand_miss_rate::total 0.010947 # miss rate for demand accesses 1844system.cpu1.icache.overall_miss_rate::cpu1.inst 0.010947 # miss rate for overall accesses 1845system.cpu1.icache.overall_miss_rate::total 0.010947 # miss rate for overall accesses 1846system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10580.905918 # average ReadReq miss latency 1847system.cpu1.icache.ReadReq_avg_miss_latency::total 10580.905918 # average ReadReq miss latency 1848system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10580.905918 # average overall miss latency 1849system.cpu1.icache.demand_avg_miss_latency::total 10580.905918 # average overall miss latency 1850system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10580.905918 # average overall miss latency 1851system.cpu1.icache.overall_avg_miss_latency::total 10580.905918 # average overall miss latency 1852system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1853system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1854system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked 1855system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked 1856system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1857system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1858system.cpu1.icache.fast_writes 0 # number of fast writes performed 1859system.cpu1.icache.cache_copies 0 # number of cache copies performed 1860system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 4892914 # number of ReadReq MSHR misses 1861system.cpu1.icache.ReadReq_mshr_misses::total 4892914 # number of ReadReq MSHR misses 1862system.cpu1.icache.demand_mshr_misses::cpu1.inst 4892914 # number of demand (read+write) MSHR misses 1863system.cpu1.icache.demand_mshr_misses::total 4892914 # number of demand (read+write) MSHR misses 1864system.cpu1.icache.overall_mshr_misses::cpu1.inst 4892914 # number of overall MSHR misses 1865system.cpu1.icache.overall_mshr_misses::total 4892914 # number of overall MSHR misses 1866system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 1867system.cpu1.icache.ReadReq_mshr_uncacheable::total 110 # number of ReadReq MSHR uncacheable 1868system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 1869system.cpu1.icache.overall_mshr_uncacheable_misses::total 110 # number of overall MSHR uncacheable misses 1870system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 46862593334 # number of ReadReq MSHR miss cycles 1871system.cpu1.icache.ReadReq_mshr_miss_latency::total 46862593334 # number of ReadReq MSHR miss cycles 1872system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 46862593334 # number of demand (read+write) MSHR miss cycles 1873system.cpu1.icache.demand_mshr_miss_latency::total 46862593334 # number of demand (read+write) MSHR miss cycles 1874system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 46862593334 # number of overall MSHR miss cycles 1875system.cpu1.icache.overall_mshr_miss_latency::total 46862593334 # number of overall MSHR miss cycles 1876system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10105750 # number of ReadReq MSHR uncacheable cycles 1877system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10105750 # number of ReadReq MSHR uncacheable cycles 1878system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10105750 # number of overall MSHR uncacheable cycles 1879system.cpu1.icache.overall_mshr_uncacheable_latency::total 10105750 # number of overall MSHR uncacheable cycles 1880system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for ReadReq accesses 1881system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.010947 # mshr miss rate for ReadReq accesses 1882system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for demand accesses 1883system.cpu1.icache.demand_mshr_miss_rate::total 0.010947 # mshr miss rate for demand accesses 1884system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.010947 # mshr miss rate for overall accesses 1885system.cpu1.icache.overall_mshr_miss_rate::total 0.010947 # mshr miss rate for overall accesses 1886system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average ReadReq mshr miss latency 1887system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 9577.645005 # average ReadReq mshr miss latency 1888system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average overall mshr miss latency 1889system.cpu1.icache.demand_avg_mshr_miss_latency::total 9577.645005 # average overall mshr miss latency 1890system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 9577.645005 # average overall mshr miss latency 1891system.cpu1.icache.overall_avg_mshr_miss_latency::total 9577.645005 # average overall mshr miss latency 1892system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545 # average ReadReq mshr uncacheable latency 1893system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 91870.454545 # average ReadReq mshr uncacheable latency 1894system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 91870.454545 # average overall mshr uncacheable latency 1895system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 91870.454545 # average overall mshr uncacheable latency 1896system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate 1897system.cpu1.l2cache.prefetcher.num_hwpf_issued 7631682 # number of hwpf issued 1898system.cpu1.l2cache.prefetcher.pfIdentified 7631760 # number of prefetch candidates identified 1899system.cpu1.l2cache.prefetcher.pfBufferHit 35 # number of redundant prefetches already in prefetch queue 1900system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1901system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1902system.cpu1.l2cache.prefetcher.pfSpanPage 935080 # number of prefetches not generated due to page crossing 1903system.cpu1.l2cache.tags.replacements 2142260 # number of replacements 1904system.cpu1.l2cache.tags.tagsinuse 13497.078408 # Cycle average of tags in use 1905system.cpu1.l2cache.tags.total_refs 10799538 # Total number of references to valid blocks. 1906system.cpu1.l2cache.tags.sampled_refs 2158371 # Sample count of references to valid blocks. 1907system.cpu1.l2cache.tags.avg_refs 5.003560 # Average number of references to valid blocks. 1908system.cpu1.l2cache.tags.warmup_cycle 9893608612000 # Cycle when the warmup percentage was hit. 1909system.cpu1.l2cache.tags.occ_blocks::writebacks 5297.531895 # Average occupied blocks per requestor 1910system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 78.016993 # Average occupied blocks per requestor 1911system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 87.104378 # Average occupied blocks per requestor 1912system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3470.735386 # Average occupied blocks per requestor 1913system.cpu1.l2cache.tags.occ_blocks::cpu1.data 3768.987855 # Average occupied blocks per requestor 1914system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 794.701900 # Average occupied blocks per requestor 1915system.cpu1.l2cache.tags.occ_percent::writebacks 0.323336 # Average percentage of cache occupancy 1916system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.004762 # Average percentage of cache occupancy 1917system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.005316 # Average percentage of cache occupancy 1918system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.211837 # Average percentage of cache occupancy 1919system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.230041 # Average percentage of cache occupancy 1920system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.048505 # Average percentage of cache occupancy 1921system.cpu1.l2cache.tags.occ_percent::total 0.823796 # Average percentage of cache occupancy 1922system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1633 # Occupied blocks per task id 1923system.cpu1.l2cache.tags.occ_task_id_blocks::1023 75 # Occupied blocks per task id 1924system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14403 # Occupied blocks per task id 1925system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 31 # Occupied blocks per task id 1926system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id 1927system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 713 # Occupied blocks per task id 1928system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 761 # Occupied blocks per task id 1929system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 32 # Occupied blocks per task id 1930system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 43 # Occupied blocks per task id 1931system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 1932system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 926 # Occupied blocks per task id 1933system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1571 # Occupied blocks per task id 1934system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5509 # Occupied blocks per task id 1935system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 6302 # Occupied blocks per task id 1936system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.099670 # Percentage of cache occupancy per task id 1937system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.004578 # Percentage of cache occupancy per task id 1938system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.879089 # Percentage of cache occupancy per task id 1939system.cpu1.l2cache.tags.tag_accesses 240281832 # Number of tag accesses 1940system.cpu1.l2cache.tags.data_accesses 240281832 # Number of data accesses 1941system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 248777 # number of ReadReq hits 1942system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 141659 # number of ReadReq hits 1943system.cpu1.l2cache.ReadReq_hits::cpu1.inst 4360207 # number of ReadReq hits 1944system.cpu1.l2cache.ReadReq_hits::cpu1.data 2869888 # number of ReadReq hits 1945system.cpu1.l2cache.ReadReq_hits::total 7620531 # number of ReadReq hits 1946system.cpu1.l2cache.Writeback_hits::writebacks 3550270 # number of Writeback hits 1947system.cpu1.l2cache.Writeback_hits::total 3550270 # number of Writeback hits 1948system.cpu1.l2cache.WriteInvalidateReq_hits::cpu1.data 228063 # number of WriteInvalidateReq hits 1949system.cpu1.l2cache.WriteInvalidateReq_hits::total 228063 # number of WriteInvalidateReq hits 1950system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 73786 # number of UpgradeReq hits 1951system.cpu1.l2cache.UpgradeReq_hits::total 73786 # number of UpgradeReq hits 1952system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 35221 # number of SCUpgradeReq hits 1953system.cpu1.l2cache.SCUpgradeReq_hits::total 35221 # number of SCUpgradeReq hits 1954system.cpu1.l2cache.ReadExReq_hits::cpu1.data 953536 # number of ReadExReq hits 1955system.cpu1.l2cache.ReadExReq_hits::total 953536 # number of ReadExReq hits 1956system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 248777 # number of demand (read+write) hits 1957system.cpu1.l2cache.demand_hits::cpu1.itb.walker 141659 # number of demand (read+write) hits 1958system.cpu1.l2cache.demand_hits::cpu1.inst 4360207 # number of demand (read+write) hits 1959system.cpu1.l2cache.demand_hits::cpu1.data 3823424 # number of demand (read+write) hits 1960system.cpu1.l2cache.demand_hits::total 8574067 # number of demand (read+write) hits 1961system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 248777 # number of overall hits 1962system.cpu1.l2cache.overall_hits::cpu1.itb.walker 141659 # number of overall hits 1963system.cpu1.l2cache.overall_hits::cpu1.inst 4360207 # number of overall hits 1964system.cpu1.l2cache.overall_hits::cpu1.data 3823424 # number of overall hits 1965system.cpu1.l2cache.overall_hits::total 8574067 # number of overall hits 1966system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 9961 # number of ReadReq misses 1967system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 7958 # number of ReadReq misses 1968system.cpu1.l2cache.ReadReq_misses::cpu1.inst 532707 # number of ReadReq misses 1969system.cpu1.l2cache.ReadReq_misses::cpu1.data 952245 # number of ReadReq misses 1970system.cpu1.l2cache.ReadReq_misses::total 1502871 # number of ReadReq misses 1971system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses 1972system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses 1973system.cpu1.l2cache.WriteInvalidateReq_misses::cpu1.data 267701 # number of WriteInvalidateReq misses 1974system.cpu1.l2cache.WriteInvalidateReq_misses::total 267701 # number of WriteInvalidateReq misses 1975system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 120750 # number of UpgradeReq misses 1976system.cpu1.l2cache.UpgradeReq_misses::total 120750 # number of UpgradeReq misses 1977system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 167539 # number of SCUpgradeReq misses 1978system.cpu1.l2cache.SCUpgradeReq_misses::total 167539 # number of SCUpgradeReq misses 1979system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses 1980system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1981system.cpu1.l2cache.ReadExReq_misses::cpu1.data 227703 # number of ReadExReq misses 1982system.cpu1.l2cache.ReadExReq_misses::total 227703 # number of ReadExReq misses 1983system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 9961 # number of demand (read+write) misses 1984system.cpu1.l2cache.demand_misses::cpu1.itb.walker 7958 # number of demand (read+write) misses 1985system.cpu1.l2cache.demand_misses::cpu1.inst 532707 # number of demand (read+write) misses 1986system.cpu1.l2cache.demand_misses::cpu1.data 1179948 # number of demand (read+write) misses 1987system.cpu1.l2cache.demand_misses::total 1730574 # number of demand (read+write) misses 1988system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 9961 # number of overall misses 1989system.cpu1.l2cache.overall_misses::cpu1.itb.walker 7958 # number of overall misses 1990system.cpu1.l2cache.overall_misses::cpu1.inst 532707 # number of overall misses 1991system.cpu1.l2cache.overall_misses::cpu1.data 1179948 # number of overall misses 1992system.cpu1.l2cache.overall_misses::total 1730574 # number of overall misses 1993system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 394640977 # number of ReadReq miss cycles 1994system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 358915726 # number of ReadReq miss cycles 1995system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 16056528318 # number of ReadReq miss cycles 1996system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 31264991014 # number of ReadReq miss cycles 1997system.cpu1.l2cache.ReadReq_miss_latency::total 48075076035 # number of ReadReq miss cycles 1998system.cpu1.l2cache.WriteInvalidateReq_miss_latency::cpu1.data 240883663 # number of WriteInvalidateReq miss cycles 1999system.cpu1.l2cache.WriteInvalidateReq_miss_latency::total 240883663 # number of WriteInvalidateReq miss cycles 2000system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 2642176746 # number of UpgradeReq miss cycles 2001system.cpu1.l2cache.UpgradeReq_miss_latency::total 2642176746 # number of UpgradeReq miss cycles 2002system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 3519293594 # number of SCUpgradeReq miss cycles 2003system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 3519293594 # number of SCUpgradeReq miss cycles 2004system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1767000 # number of SCUpgradeFailReq miss cycles 2005system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1767000 # number of SCUpgradeFailReq miss cycles 2006system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 9869071556 # number of ReadExReq miss cycles 2007system.cpu1.l2cache.ReadExReq_miss_latency::total 9869071556 # number of ReadExReq miss cycles 2008system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 394640977 # number of demand (read+write) miss cycles 2009system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 358915726 # number of demand (read+write) miss cycles 2010system.cpu1.l2cache.demand_miss_latency::cpu1.inst 16056528318 # number of demand (read+write) miss cycles 2011system.cpu1.l2cache.demand_miss_latency::cpu1.data 41134062570 # number of demand (read+write) miss cycles 2012system.cpu1.l2cache.demand_miss_latency::total 57944147591 # number of demand (read+write) miss cycles 2013system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 394640977 # number of overall miss cycles 2014system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 358915726 # number of overall miss cycles 2015system.cpu1.l2cache.overall_miss_latency::cpu1.inst 16056528318 # number of overall miss cycles 2016system.cpu1.l2cache.overall_miss_latency::cpu1.data 41134062570 # number of overall miss cycles 2017system.cpu1.l2cache.overall_miss_latency::total 57944147591 # number of overall miss cycles 2018system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 258738 # number of ReadReq accesses(hits+misses) 2019system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 149617 # number of ReadReq accesses(hits+misses) 2020system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 4892914 # number of ReadReq accesses(hits+misses) 2021system.cpu1.l2cache.ReadReq_accesses::cpu1.data 3822133 # number of ReadReq accesses(hits+misses) 2022system.cpu1.l2cache.ReadReq_accesses::total 9123402 # number of ReadReq accesses(hits+misses) 2023system.cpu1.l2cache.Writeback_accesses::writebacks 3550271 # number of Writeback accesses(hits+misses) 2024system.cpu1.l2cache.Writeback_accesses::total 3550271 # number of Writeback accesses(hits+misses) 2025system.cpu1.l2cache.WriteInvalidateReq_accesses::cpu1.data 495764 # number of WriteInvalidateReq accesses(hits+misses) 2026system.cpu1.l2cache.WriteInvalidateReq_accesses::total 495764 # number of WriteInvalidateReq accesses(hits+misses) 2027system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 194536 # number of UpgradeReq accesses(hits+misses) 2028system.cpu1.l2cache.UpgradeReq_accesses::total 194536 # number of UpgradeReq accesses(hits+misses) 2029system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 202760 # number of SCUpgradeReq accesses(hits+misses) 2030system.cpu1.l2cache.SCUpgradeReq_accesses::total 202760 # number of SCUpgradeReq accesses(hits+misses) 2031system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 2032system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 2033system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1181239 # number of ReadExReq accesses(hits+misses) 2034system.cpu1.l2cache.ReadExReq_accesses::total 1181239 # number of ReadExReq accesses(hits+misses) 2035system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 258738 # number of demand (read+write) accesses 2036system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 149617 # number of demand (read+write) accesses 2037system.cpu1.l2cache.demand_accesses::cpu1.inst 4892914 # number of demand (read+write) accesses 2038system.cpu1.l2cache.demand_accesses::cpu1.data 5003372 # number of demand (read+write) accesses 2039system.cpu1.l2cache.demand_accesses::total 10304641 # number of demand (read+write) accesses 2040system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 258738 # number of overall (read+write) accesses 2041system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 149617 # number of overall (read+write) accesses 2042system.cpu1.l2cache.overall_accesses::cpu1.inst 4892914 # number of overall (read+write) accesses 2043system.cpu1.l2cache.overall_accesses::cpu1.data 5003372 # number of overall (read+write) accesses 2044system.cpu1.l2cache.overall_accesses::total 10304641 # number of overall (read+write) accesses 2045system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for ReadReq accesses 2046system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.053189 # miss rate for ReadReq accesses 2047system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.108873 # miss rate for ReadReq accesses 2048system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.249140 # miss rate for ReadReq accesses 2049system.cpu1.l2cache.ReadReq_miss_rate::total 0.164727 # miss rate for ReadReq accesses 2050system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000000 # miss rate for Writeback accesses 2051system.cpu1.l2cache.Writeback_miss_rate::total 0.000000 # miss rate for Writeback accesses 2052system.cpu1.l2cache.WriteInvalidateReq_miss_rate::cpu1.data 0.539977 # miss rate for WriteInvalidateReq accesses 2053system.cpu1.l2cache.WriteInvalidateReq_miss_rate::total 0.539977 # miss rate for WriteInvalidateReq accesses 2054system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.620708 # miss rate for UpgradeReq accesses 2055system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.620708 # miss rate for UpgradeReq accesses 2056system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.826292 # miss rate for SCUpgradeReq accesses 2057system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.826292 # miss rate for SCUpgradeReq accesses 2058system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2059system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2060system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.192766 # miss rate for ReadExReq accesses 2061system.cpu1.l2cache.ReadExReq_miss_rate::total 0.192766 # miss rate for ReadExReq accesses 2062system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for demand accesses 2063system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.053189 # miss rate for demand accesses 2064system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.108873 # miss rate for demand accesses 2065system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.235831 # miss rate for demand accesses 2066system.cpu1.l2cache.demand_miss_rate::total 0.167941 # miss rate for demand accesses 2067system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.038498 # miss rate for overall accesses 2068system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.053189 # miss rate for overall accesses 2069system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.108873 # miss rate for overall accesses 2070system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.235831 # miss rate for overall accesses 2071system.cpu1.l2cache.overall_miss_rate::total 0.167941 # miss rate for overall accesses 2072system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average ReadReq miss latency 2073system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 45101.247298 # average ReadReq miss latency 2074system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 30141.387889 # average ReadReq miss latency 2075system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 32832.927465 # average ReadReq miss latency 2076system.cpu1.l2cache.ReadReq_avg_miss_latency::total 31988.824081 # average ReadReq miss latency 2077system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::cpu1.data 899.823546 # average WriteInvalidateReq miss latency 2078system.cpu1.l2cache.WriteInvalidateReq_avg_miss_latency::total 899.823546 # average WriteInvalidateReq miss latency 2079system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 21881.380919 # average UpgradeReq miss latency 2080system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 21881.380919 # average UpgradeReq miss latency 2081system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 21005.817117 # average SCUpgradeReq miss latency 2082system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 21005.817117 # average SCUpgradeReq miss latency 2083system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 353400 # average SCUpgradeFailReq miss latency 2084system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 353400 # average SCUpgradeFailReq miss latency 2085system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 43341.860037 # average ReadExReq miss latency 2086system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 43341.860037 # average ReadExReq miss latency 2087system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average overall miss latency 2088system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 45101.247298 # average overall miss latency 2089system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 30141.387889 # average overall miss latency 2090system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 34860.911303 # average overall miss latency 2091system.cpu1.l2cache.demand_avg_miss_latency::total 33482.617670 # average overall miss latency 2092system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 39618.610280 # average overall miss latency 2093system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 45101.247298 # average overall miss latency 2094system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 30141.387889 # average overall miss latency 2095system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 34860.911303 # average overall miss latency 2096system.cpu1.l2cache.overall_avg_miss_latency::total 33482.617670 # average overall miss latency 2097system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 2098system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2099system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 2100system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2101system.cpu1.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 2102system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2103system.cpu1.l2cache.fast_writes 0 # number of fast writes performed 2104system.cpu1.l2cache.cache_copies 0 # number of cache copies performed 2105system.cpu1.l2cache.writebacks::writebacks 1053113 # number of writebacks 2106system.cpu1.l2cache.writebacks::total 1053113 # number of writebacks 2107system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 432 # number of ReadReq MSHR hits 2108system.cpu1.l2cache.ReadReq_mshr_hits::total 432 # number of ReadReq MSHR hits 2109system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::cpu1.data 1 # number of WriteInvalidateReq MSHR hits 2110system.cpu1.l2cache.WriteInvalidateReq_mshr_hits::total 1 # number of WriteInvalidateReq MSHR hits 2111system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 7197 # number of ReadExReq MSHR hits 2112system.cpu1.l2cache.ReadExReq_mshr_hits::total 7197 # number of ReadExReq MSHR hits 2113system.cpu1.l2cache.demand_mshr_hits::cpu1.data 7629 # number of demand (read+write) MSHR hits 2114system.cpu1.l2cache.demand_mshr_hits::total 7629 # number of demand (read+write) MSHR hits 2115system.cpu1.l2cache.overall_mshr_hits::cpu1.data 7629 # number of overall MSHR hits 2116system.cpu1.l2cache.overall_mshr_hits::total 7629 # number of overall MSHR hits 2117system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 9961 # number of ReadReq MSHR misses 2118system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 7958 # number of ReadReq MSHR misses 2119system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 532707 # number of ReadReq MSHR misses 2120system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 951813 # number of ReadReq MSHR misses 2121system.cpu1.l2cache.ReadReq_mshr_misses::total 1502439 # number of ReadReq MSHR misses 2122system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses 2123system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses 2124system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 707306 # number of HardPFReq MSHR misses 2125system.cpu1.l2cache.HardPFReq_mshr_misses::total 707306 # number of HardPFReq MSHR misses 2126system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::cpu1.data 267700 # number of WriteInvalidateReq MSHR misses 2127system.cpu1.l2cache.WriteInvalidateReq_mshr_misses::total 267700 # number of WriteInvalidateReq MSHR misses 2128system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 120750 # number of UpgradeReq MSHR misses 2129system.cpu1.l2cache.UpgradeReq_mshr_misses::total 120750 # number of UpgradeReq MSHR misses 2130system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 167539 # number of SCUpgradeReq MSHR misses 2131system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 167539 # number of SCUpgradeReq MSHR misses 2132system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 5 # number of SCUpgradeFailReq MSHR misses 2133system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 2134system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 220506 # number of ReadExReq MSHR misses 2135system.cpu1.l2cache.ReadExReq_mshr_misses::total 220506 # number of ReadExReq MSHR misses 2136system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 9961 # number of demand (read+write) MSHR misses 2137system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 7958 # number of demand (read+write) MSHR misses 2138system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 532707 # number of demand (read+write) MSHR misses 2139system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1172319 # number of demand (read+write) MSHR misses 2140system.cpu1.l2cache.demand_mshr_misses::total 1722945 # number of demand (read+write) MSHR misses 2141system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 9961 # number of overall MSHR misses 2142system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 7958 # number of overall MSHR misses 2143system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 532707 # number of overall MSHR misses 2144system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1172319 # number of overall MSHR misses 2145system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 707306 # number of overall MSHR misses 2146system.cpu1.l2cache.overall_mshr_misses::total 2430251 # number of overall MSHR misses 2147system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2148system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21725 # number of ReadReq MSHR uncacheable 2149system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21835 # number of ReadReq MSHR uncacheable 2150system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable 2151system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 20113 # number of WriteReq MSHR uncacheable 2152system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2153system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 41838 # number of overall MSHR uncacheable misses 2154system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 41948 # number of overall MSHR uncacheable misses 2155system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of ReadReq MSHR miss cycles 2156system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 306561274 # number of ReadReq MSHR miss cycles 2157system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 12577785182 # number of ReadReq MSHR miss cycles 2158system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 24989286886 # number of ReadReq MSHR miss cycles 2159system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 38202866865 # number of ReadReq MSHR miss cycles 2160system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 35407537019 # number of HardPFReq MSHR miss cycles 2161system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 35407537019 # number of HardPFReq MSHR miss cycles 2162system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 9092223824 # number of WriteInvalidateReq MSHR miss cycles 2163system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_latency::total 9092223824 # number of WriteInvalidateReq MSHR miss cycles 2164system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 2448079564 # number of UpgradeReq MSHR miss cycles 2165system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 2448079564 # number of UpgradeReq MSHR miss cycles 2166system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2512705540 # number of SCUpgradeReq MSHR miss cycles 2167system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2512705540 # number of SCUpgradeReq MSHR miss cycles 2168system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 1507000 # number of SCUpgradeFailReq MSHR miss cycles 2169system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 1507000 # number of SCUpgradeFailReq MSHR miss cycles 2170system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 7591763498 # number of ReadExReq MSHR miss cycles 2171system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 7591763498 # number of ReadExReq MSHR miss cycles 2172system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of demand (read+write) MSHR miss cycles 2173system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 306561274 # number of demand (read+write) MSHR miss cycles 2174system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 12577785182 # number of demand (read+write) MSHR miss cycles 2175system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 32581050384 # number of demand (read+write) MSHR miss cycles 2176system.cpu1.l2cache.demand_mshr_miss_latency::total 45794630363 # number of demand (read+write) MSHR miss cycles 2177system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 329233523 # number of overall MSHR miss cycles 2178system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 306561274 # number of overall MSHR miss cycles 2179system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 12577785182 # number of overall MSHR miss cycles 2180system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 32581050384 # number of overall MSHR miss cycles 2181system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 35407537019 # number of overall MSHR miss cycles 2182system.cpu1.l2cache.overall_mshr_miss_latency::total 81202167382 # number of overall MSHR miss cycles 2183system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9241250 # number of ReadReq MSHR uncacheable cycles 2184system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3553660750 # number of ReadReq MSHR uncacheable cycles 2185system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3562902000 # number of ReadReq MSHR uncacheable cycles 2186system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3314826000 # number of WriteReq MSHR uncacheable cycles 2187system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3314826000 # number of WriteReq MSHR uncacheable cycles 2188system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9241250 # number of overall MSHR uncacheable cycles 2189system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 6868486750 # number of overall MSHR uncacheable cycles 2190system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 6877728000 # number of overall MSHR uncacheable cycles 2191system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for ReadReq accesses 2192system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for ReadReq accesses 2193system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for ReadReq accesses 2194system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.249027 # mshr miss rate for ReadReq accesses 2195system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.164680 # mshr miss rate for ReadReq accesses 2196system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000000 # mshr miss rate for Writeback accesses 2197system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000000 # mshr miss rate for Writeback accesses 2198system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2199system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2200system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.539975 # mshr miss rate for WriteInvalidateReq accesses 2201system.cpu1.l2cache.WriteInvalidateReq_mshr_miss_rate::total 0.539975 # mshr miss rate for WriteInvalidateReq accesses 2202system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.620708 # mshr miss rate for UpgradeReq accesses 2203system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.620708 # mshr miss rate for UpgradeReq accesses 2204system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.826292 # mshr miss rate for SCUpgradeReq accesses 2205system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.826292 # mshr miss rate for SCUpgradeReq accesses 2206system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2207system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2208system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.186673 # mshr miss rate for ReadExReq accesses 2209system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.186673 # mshr miss rate for ReadExReq accesses 2210system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for demand accesses 2211system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for demand accesses 2212system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for demand accesses 2213system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for demand accesses 2214system.cpu1.l2cache.demand_mshr_miss_rate::total 0.167201 # mshr miss rate for demand accesses 2215system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.038498 # mshr miss rate for overall accesses 2216system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.053189 # mshr miss rate for overall accesses 2217system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.108873 # mshr miss rate for overall accesses 2218system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.234306 # mshr miss rate for overall accesses 2219system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2220system.cpu1.l2cache.overall_mshr_miss_rate::total 0.235840 # mshr miss rate for overall accesses 2221system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average ReadReq mshr miss latency 2222system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average ReadReq mshr miss latency 2223system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average ReadReq mshr miss latency 2224system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 26254.408047 # average ReadReq mshr miss latency 2225system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25427.233229 # average ReadReq mshr miss latency 2226system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average HardPFReq mshr miss latency 2227system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50059.715341 # average HardPFReq mshr miss latency 2228system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 33964.227957 # average WriteInvalidateReq mshr miss latency 2229system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total 33964.227957 # average WriteInvalidateReq mshr miss latency 2230system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20273.950841 # average UpgradeReq mshr miss latency 2231system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20273.950841 # average UpgradeReq mshr miss latency 2232system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14997.735095 # average SCUpgradeReq mshr miss latency 2233system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14997.735095 # average SCUpgradeReq mshr miss latency 2234system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 301400 # average SCUpgradeFailReq mshr miss latency 2235system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 301400 # average SCUpgradeFailReq mshr miss latency 2236system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34428.829592 # average ReadExReq mshr miss latency 2237system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34428.829592 # average ReadExReq mshr miss latency 2238system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency 2239system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency 2240system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency 2241system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency 2242system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26579.275811 # average overall mshr miss latency 2243system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 33052.256099 # average overall mshr miss latency 2244system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 38522.401860 # average overall mshr miss latency 2245system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 23611.075473 # average overall mshr miss latency 2246system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27791.966507 # average overall mshr miss latency 2247system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50059.715341 # average overall mshr miss latency 2248system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33413.078477 # average overall mshr miss latency 2249system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average ReadReq mshr uncacheable latency 2250system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163574.718067 # average ReadReq mshr uncacheable latency 2251system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163173.895123 # average ReadReq mshr uncacheable latency 2252system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 164810.122806 # average WriteReq mshr uncacheable latency 2253system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 164810.122806 # average WriteReq mshr uncacheable latency 2254system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84011.363636 # average overall mshr uncacheable latency 2255system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 164168.620632 # average overall mshr uncacheable latency 2256system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 163958.424716 # average overall mshr uncacheable latency 2257system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 2258system.cpu1.toL2Bus.trans_dist::ReadReq 11407818 # Transaction distribution 2259system.cpu1.toL2Bus.trans_dist::ReadResp 9339972 # Transaction distribution 2260system.cpu1.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution 2261system.cpu1.toL2Bus.trans_dist::WriteResp 20113 # Transaction distribution 2262system.cpu1.toL2Bus.trans_dist::Writeback 3550271 # Transaction distribution 2263system.cpu1.toL2Bus.trans_dist::HardPFReq 1013669 # Transaction distribution 2264system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1157980 # Transaction distribution 2265system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 495764 # Transaction distribution 2266system.cpu1.toL2Bus.trans_dist::UpgradeReq 395206 # Transaction distribution 2267system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 367201 # Transaction distribution 2268system.cpu1.toL2Bus.trans_dist::UpgradeResp 457834 # Transaction distribution 2269system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 51 # Transaction distribution 2270system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution 2271system.cpu1.toL2Bus.trans_dist::ReadExReq 1341582 # Transaction distribution 2272system.cpu1.toL2Bus.trans_dist::ReadExResp 1187599 # Transaction distribution 2273system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9786048 # Packet count per connected master and slave (bytes) 2274system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15579584 # Packet count per connected master and slave (bytes) 2275system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 330806 # Packet count per connected master and slave (bytes) 2276system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 594855 # Packet count per connected master and slave (bytes) 2277system.cpu1.toL2Bus.pkt_count::total 26291293 # Packet count per connected master and slave (bytes) 2278system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 313146936 # Cumulative packet size per connected master and slave (bytes) 2279system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 585201818 # Cumulative packet size per connected master and slave (bytes) 2280system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1196936 # Cumulative packet size per connected master and slave (bytes) 2281system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 2069904 # Cumulative packet size per connected master and slave (bytes) 2282system.cpu1.toL2Bus.pkt_size::total 901615594 # Cumulative packet size per connected master and slave (bytes) 2283system.cpu1.toL2Bus.snoops 4634762 # Total snoops (count) 2284system.cpu1.toL2Bus.snoop_fanout::samples 19271924 # Request fanout histogram 2285system.cpu1.toL2Bus.snoop_fanout::mean 1.253755 # Request fanout histogram 2286system.cpu1.toL2Bus.snoop_fanout::stdev 0.435159 # Request fanout histogram 2287system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2288system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 2289system.cpu1.toL2Bus.snoop_fanout::1 14381570 74.62% 74.62% # Request fanout histogram 2290system.cpu1.toL2Bus.snoop_fanout::2 4890354 25.38% 100.00% # Request fanout histogram 2291system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2292system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 2293system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2294system.cpu1.toL2Bus.snoop_fanout::total 19271924 # Request fanout histogram 2295system.cpu1.toL2Bus.reqLayer0.occupancy 11505600998 # Layer occupancy (ticks) 2296system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2297system.cpu1.toL2Bus.snoopLayer0.occupancy 168563993 # Layer occupancy (ticks) 2298system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2299system.cpu1.toL2Bus.respLayer0.occupancy 7347478432 # Layer occupancy (ticks) 2300system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2301system.cpu1.toL2Bus.respLayer1.occupancy 8042476622 # Layer occupancy (ticks) 2302system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2303system.cpu1.toL2Bus.respLayer2.occupancy 181503274 # Layer occupancy (ticks) 2304system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2305system.cpu1.toL2Bus.respLayer3.occupancy 336447522 # Layer occupancy (ticks) 2306system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2307system.iobus.trans_dist::ReadReq 40366 # Transaction distribution 2308system.iobus.trans_dist::ReadResp 40366 # Transaction distribution 2309system.iobus.trans_dist::WriteReq 136641 # Transaction distribution 2310system.iobus.trans_dist::WriteResp 29913 # Transaction distribution 2311system.iobus.trans_dist::WriteInvalidateResp 106728 # Transaction distribution 2312system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47782 # Packet count per connected master and slave (bytes) 2313system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2314system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2315system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2316system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2317system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2318system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2319system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2320system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 2321system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 2322system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 2323system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) 2324system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 2325system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) 2326system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 2327system.iobus.pkt_count_system.bridge.master::total 122716 # Packet count per connected master and slave (bytes) 2328system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231218 # Packet count per connected master and slave (bytes) 2329system.iobus.pkt_count_system.realview.ide.dma::total 231218 # Packet count per connected master and slave (bytes) 2330system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 2331system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 2332system.iobus.pkt_count::total 354014 # Packet count per connected master and slave (bytes) 2333system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47802 # Cumulative packet size per connected master and slave (bytes) 2334system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 2335system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 2336system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 2337system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 2338system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2339system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2340system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2341system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 2342system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 2343system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 2344system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes) 2345system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 2346system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes) 2347system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 2348system.iobus.pkt_size_system.bridge.master::total 155823 # Cumulative packet size per connected master and slave (bytes) 2349system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7338888 # Cumulative packet size per connected master and slave (bytes) 2350system.iobus.pkt_size_system.realview.ide.dma::total 7338888 # Cumulative packet size per connected master and slave (bytes) 2351system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 2352system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 2353system.iobus.pkt_size::total 7496797 # Cumulative packet size per connected master and slave (bytes) 2354system.iobus.reqLayer0.occupancy 36274000 # Layer occupancy (ticks) 2355system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 2356system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks) 2357system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 2358system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks) 2359system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 2360system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks) 2361system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 2362system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) 2363system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 2364system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) 2365system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 2366system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) 2367system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 2368system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) 2369system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 2370system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks) 2371system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 2372system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) 2373system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 2374system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks) 2375system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 2376system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks) 2377system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 2378system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks) 2379system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 2380system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks) 2381system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) 2382system.iobus.reqLayer27.occupancy 607607215 # Layer occupancy (ticks) 2383system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) 2384system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) 2385system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) 2386system.iobus.respLayer0.occupancy 92806000 # Layer occupancy (ticks) 2387system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 2388system.iobus.respLayer3.occupancy 148515621 # Layer occupancy (ticks) 2389system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 2390system.iobus.respLayer4.occupancy 170500 # Layer occupancy (ticks) 2391system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 2392system.iocache.tags.replacements 115613 # number of replacements 2393system.iocache.tags.tagsinuse 11.298152 # Cycle average of tags in use 2394system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 2395system.iocache.tags.sampled_refs 115629 # Sample count of references to valid blocks. 2396system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 2397system.iocache.tags.warmup_cycle 9179138787000 # Cycle when the warmup percentage was hit. 2398system.iocache.tags.occ_blocks::realview.ethernet 7.392909 # Average occupied blocks per requestor 2399system.iocache.tags.occ_blocks::realview.ide 3.905243 # Average occupied blocks per requestor 2400system.iocache.tags.occ_percent::realview.ethernet 0.462057 # Average percentage of cache occupancy 2401system.iocache.tags.occ_percent::realview.ide 0.244078 # Average percentage of cache occupancy 2402system.iocache.tags.occ_percent::total 0.706135 # Average percentage of cache occupancy 2403system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 2404system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 2405system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 2406system.iocache.tags.tag_accesses 1040838 # Number of tag accesses 2407system.iocache.tags.data_accesses 1040838 # Number of data accesses 2408system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 2409system.iocache.ReadReq_misses::realview.ide 8881 # number of ReadReq misses 2410system.iocache.ReadReq_misses::total 8918 # number of ReadReq misses 2411system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 2412system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 2413system.iocache.WriteInvalidateReq_misses::realview.ide 106728 # number of WriteInvalidateReq misses 2414system.iocache.WriteInvalidateReq_misses::total 106728 # number of WriteInvalidateReq misses 2415system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 2416system.iocache.demand_misses::realview.ide 8881 # number of demand (read+write) misses 2417system.iocache.demand_misses::total 8921 # number of demand (read+write) misses 2418system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 2419system.iocache.overall_misses::realview.ide 8881 # number of overall misses 2420system.iocache.overall_misses::total 8921 # number of overall misses 2421system.iocache.ReadReq_miss_latency::realview.ethernet 5195500 # number of ReadReq miss cycles 2422system.iocache.ReadReq_miss_latency::realview.ide 1629816861 # number of ReadReq miss cycles 2423system.iocache.ReadReq_miss_latency::total 1635012361 # number of ReadReq miss cycles 2424system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 2425system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 2426system.iocache.WriteInvalidateReq_miss_latency::realview.ide 19901379733 # number of WriteInvalidateReq miss cycles 2427system.iocache.WriteInvalidateReq_miss_latency::total 19901379733 # number of WriteInvalidateReq miss cycles 2428system.iocache.demand_miss_latency::realview.ethernet 5564500 # number of demand (read+write) miss cycles 2429system.iocache.demand_miss_latency::realview.ide 1629816861 # number of demand (read+write) miss cycles 2430system.iocache.demand_miss_latency::total 1635381361 # number of demand (read+write) miss cycles 2431system.iocache.overall_miss_latency::realview.ethernet 5564500 # number of overall miss cycles 2432system.iocache.overall_miss_latency::realview.ide 1629816861 # number of overall miss cycles 2433system.iocache.overall_miss_latency::total 1635381361 # number of overall miss cycles 2434system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 2435system.iocache.ReadReq_accesses::realview.ide 8881 # number of ReadReq accesses(hits+misses) 2436system.iocache.ReadReq_accesses::total 8918 # number of ReadReq accesses(hits+misses) 2437system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 2438system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 2439system.iocache.WriteInvalidateReq_accesses::realview.ide 106728 # number of WriteInvalidateReq accesses(hits+misses) 2440system.iocache.WriteInvalidateReq_accesses::total 106728 # number of WriteInvalidateReq accesses(hits+misses) 2441system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 2442system.iocache.demand_accesses::realview.ide 8881 # number of demand (read+write) accesses 2443system.iocache.demand_accesses::total 8921 # number of demand (read+write) accesses 2444system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 2445system.iocache.overall_accesses::realview.ide 8881 # number of overall (read+write) accesses 2446system.iocache.overall_accesses::total 8921 # number of overall (read+write) accesses 2447system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 2448system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 2449system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 2450system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 2451system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 2452system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses 2453system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 2454system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 2455system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 2456system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 2457system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 2458system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 2459system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 2460system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140418.918919 # average ReadReq miss latency 2461system.iocache.ReadReq_avg_miss_latency::realview.ide 183517.268438 # average ReadReq miss latency 2462system.iocache.ReadReq_avg_miss_latency::total 183338.457165 # average ReadReq miss latency 2463system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 2464system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 2465system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 186468.215773 # average WriteInvalidateReq miss latency 2466system.iocache.WriteInvalidateReq_avg_miss_latency::total 186468.215773 # average WriteInvalidateReq miss latency 2467system.iocache.demand_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency 2468system.iocache.demand_avg_miss_latency::realview.ide 183517.268438 # average overall miss latency 2469system.iocache.demand_avg_miss_latency::total 183318.166237 # average overall miss latency 2470system.iocache.overall_avg_miss_latency::realview.ethernet 139112.500000 # average overall miss latency 2471system.iocache.overall_avg_miss_latency::realview.ide 183517.268438 # average overall miss latency 2472system.iocache.overall_avg_miss_latency::total 183318.166237 # average overall miss latency 2473system.iocache.blocked_cycles::no_mshrs 110961 # number of cycles access was blocked 2474system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2475system.iocache.blocked::no_mshrs 16203 # number of cycles access was blocked 2476system.iocache.blocked::no_targets 0 # number of cycles access was blocked 2477system.iocache.avg_blocked_cycles::no_mshrs 6.848176 # average number of cycles each access was blocked 2478system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2479system.iocache.fast_writes 0 # number of fast writes performed 2480system.iocache.cache_copies 0 # number of cache copies performed 2481system.iocache.writebacks::writebacks 106702 # number of writebacks 2482system.iocache.writebacks::total 106702 # number of writebacks 2483system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 2484system.iocache.ReadReq_mshr_misses::realview.ide 8881 # number of ReadReq MSHR misses 2485system.iocache.ReadReq_mshr_misses::total 8918 # number of ReadReq MSHR misses 2486system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 2487system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 2488system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 106728 # number of WriteInvalidateReq MSHR misses 2489system.iocache.WriteInvalidateReq_mshr_misses::total 106728 # number of WriteInvalidateReq MSHR misses 2490system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 2491system.iocache.demand_mshr_misses::realview.ide 8881 # number of demand (read+write) MSHR misses 2492system.iocache.demand_mshr_misses::total 8921 # number of demand (read+write) MSHR misses 2493system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 2494system.iocache.overall_mshr_misses::realview.ide 8881 # number of overall MSHR misses 2495system.iocache.overall_mshr_misses::total 8921 # number of overall MSHR misses 2496system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3270500 # number of ReadReq MSHR miss cycles 2497system.iocache.ReadReq_mshr_miss_latency::realview.ide 1166890035 # number of ReadReq MSHR miss cycles 2498system.iocache.ReadReq_mshr_miss_latency::total 1170160535 # number of ReadReq MSHR miss cycles 2499system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 213000 # number of WriteReq MSHR miss cycles 2500system.iocache.WriteReq_mshr_miss_latency::total 213000 # number of WriteReq MSHR miss cycles 2501system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 14351455801 # number of WriteInvalidateReq MSHR miss cycles 2502system.iocache.WriteInvalidateReq_mshr_miss_latency::total 14351455801 # number of WriteInvalidateReq MSHR miss cycles 2503system.iocache.demand_mshr_miss_latency::realview.ethernet 3483500 # number of demand (read+write) MSHR miss cycles 2504system.iocache.demand_mshr_miss_latency::realview.ide 1166890035 # number of demand (read+write) MSHR miss cycles 2505system.iocache.demand_mshr_miss_latency::total 1170373535 # number of demand (read+write) MSHR miss cycles 2506system.iocache.overall_mshr_miss_latency::realview.ethernet 3483500 # number of overall MSHR miss cycles 2507system.iocache.overall_mshr_miss_latency::realview.ide 1166890035 # number of overall MSHR miss cycles 2508system.iocache.overall_mshr_miss_latency::total 1170373535 # number of overall MSHR miss cycles 2509system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 2510system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 2511system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 2512system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 2513system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 2514system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses 2515system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses 2516system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 2517system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 2518system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 2519system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 2520system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 2521system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 2522system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 88391.891892 # average ReadReq mshr miss latency 2523system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131391.739106 # average ReadReq mshr miss latency 2524system.iocache.ReadReq_avg_mshr_miss_latency::total 131213.336510 # average ReadReq mshr miss latency 2525system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 71000 # average WriteReq mshr miss latency 2526system.iocache.WriteReq_avg_mshr_miss_latency::total 71000 # average WriteReq mshr miss latency 2527system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 134467.579276 # average WriteInvalidateReq mshr miss latency 2528system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 134467.579276 # average WriteInvalidateReq mshr miss latency 2529system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency 2530system.iocache.demand_avg_mshr_miss_latency::realview.ide 131391.739106 # average overall mshr miss latency 2531system.iocache.demand_avg_mshr_miss_latency::total 131193.087658 # average overall mshr miss latency 2532system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 87087.500000 # average overall mshr miss latency 2533system.iocache.overall_avg_mshr_miss_latency::realview.ide 131391.739106 # average overall mshr miss latency 2534system.iocache.overall_avg_mshr_miss_latency::total 131193.087658 # average overall mshr miss latency 2535system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 2536system.l2c.tags.replacements 1448041 # number of replacements 2537system.l2c.tags.tagsinuse 64131.287175 # Cycle average of tags in use 2538system.l2c.tags.total_refs 4245095 # Total number of references to valid blocks. 2539system.l2c.tags.sampled_refs 1507106 # Sample count of references to valid blocks. 2540system.l2c.tags.avg_refs 2.816720 # Average number of references to valid blocks. 2541system.l2c.tags.warmup_cycle 11172879000 # Cycle when the warmup percentage was hit. 2542system.l2c.tags.occ_blocks::writebacks 19347.050639 # Average occupied blocks per requestor 2543system.l2c.tags.occ_blocks::cpu0.dtb.walker 116.894544 # Average occupied blocks per requestor 2544system.l2c.tags.occ_blocks::cpu0.itb.walker 154.865125 # Average occupied blocks per requestor 2545system.l2c.tags.occ_blocks::cpu0.inst 3200.431152 # Average occupied blocks per requestor 2546system.l2c.tags.occ_blocks::cpu0.data 7856.746302 # Average occupied blocks per requestor 2547system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 9704.320174 # Average occupied blocks per requestor 2548system.l2c.tags.occ_blocks::cpu1.dtb.walker 227.109782 # Average occupied blocks per requestor 2549system.l2c.tags.occ_blocks::cpu1.itb.walker 297.906768 # Average occupied blocks per requestor 2550system.l2c.tags.occ_blocks::cpu1.inst 3324.337079 # Average occupied blocks per requestor 2551system.l2c.tags.occ_blocks::cpu1.data 8639.334854 # Average occupied blocks per requestor 2552system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 11262.290757 # Average occupied blocks per requestor 2553system.l2c.tags.occ_percent::writebacks 0.295213 # Average percentage of cache occupancy 2554system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001784 # Average percentage of cache occupancy 2555system.l2c.tags.occ_percent::cpu0.itb.walker 0.002363 # Average percentage of cache occupancy 2556system.l2c.tags.occ_percent::cpu0.inst 0.048835 # Average percentage of cache occupancy 2557system.l2c.tags.occ_percent::cpu0.data 0.119884 # Average percentage of cache occupancy 2558system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.148076 # Average percentage of cache occupancy 2559system.l2c.tags.occ_percent::cpu1.dtb.walker 0.003465 # Average percentage of cache occupancy 2560system.l2c.tags.occ_percent::cpu1.itb.walker 0.004546 # Average percentage of cache occupancy 2561system.l2c.tags.occ_percent::cpu1.inst 0.050725 # Average percentage of cache occupancy 2562system.l2c.tags.occ_percent::cpu1.data 0.131826 # Average percentage of cache occupancy 2563system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.171849 # Average percentage of cache occupancy 2564system.l2c.tags.occ_percent::total 0.978566 # Average percentage of cache occupancy 2565system.l2c.tags.occ_task_id_blocks::1022 10716 # Occupied blocks per task id 2566system.l2c.tags.occ_task_id_blocks::1023 318 # Occupied blocks per task id 2567system.l2c.tags.occ_task_id_blocks::1024 48031 # Occupied blocks per task id 2568system.l2c.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id 2569system.l2c.tags.age_task_id_blocks_1022::2 38 # Occupied blocks per task id 2570system.l2c.tags.age_task_id_blocks_1022::3 439 # Occupied blocks per task id 2571system.l2c.tags.age_task_id_blocks_1022::4 10237 # Occupied blocks per task id 2572system.l2c.tags.age_task_id_blocks_1023::4 318 # Occupied blocks per task id 2573system.l2c.tags.age_task_id_blocks_1024::0 17 # Occupied blocks per task id 2574system.l2c.tags.age_task_id_blocks_1024::1 99 # Occupied blocks per task id 2575system.l2c.tags.age_task_id_blocks_1024::2 1326 # Occupied blocks per task id 2576system.l2c.tags.age_task_id_blocks_1024::3 4887 # Occupied blocks per task id 2577system.l2c.tags.age_task_id_blocks_1024::4 41702 # Occupied blocks per task id 2578system.l2c.tags.occ_task_id_percent::1022 0.163513 # Percentage of cache occupancy per task id 2579system.l2c.tags.occ_task_id_percent::1023 0.004852 # Percentage of cache occupancy per task id 2580system.l2c.tags.occ_task_id_percent::1024 0.732895 # Percentage of cache occupancy per task id 2581system.l2c.tags.tag_accesses 58352089 # Number of tag accesses 2582system.l2c.tags.data_accesses 58352089 # Number of data accesses 2583system.l2c.ReadReq_hits::cpu0.dtb.walker 5485 # number of ReadReq hits 2584system.l2c.ReadReq_hits::cpu0.itb.walker 4305 # number of ReadReq hits 2585system.l2c.ReadReq_hits::cpu0.inst 465111 # number of ReadReq hits 2586system.l2c.ReadReq_hits::cpu0.data 536784 # number of ReadReq hits 2587system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 265347 # number of ReadReq hits 2588system.l2c.ReadReq_hits::cpu1.dtb.walker 5257 # number of ReadReq hits 2589system.l2c.ReadReq_hits::cpu1.itb.walker 3875 # number of ReadReq hits 2590system.l2c.ReadReq_hits::cpu1.inst 485070 # number of ReadReq hits 2591system.l2c.ReadReq_hits::cpu1.data 556488 # number of ReadReq hits 2592system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 285641 # number of ReadReq hits 2593system.l2c.ReadReq_hits::total 2613363 # number of ReadReq hits 2594system.l2c.Writeback_hits::writebacks 2374848 # number of Writeback hits 2595system.l2c.Writeback_hits::total 2374848 # number of Writeback hits 2596system.l2c.WriteInvalidateReq_hits::cpu0.data 123464 # number of WriteInvalidateReq hits 2597system.l2c.WriteInvalidateReq_hits::cpu1.data 121626 # number of WriteInvalidateReq hits 2598system.l2c.WriteInvalidateReq_hits::total 245090 # number of WriteInvalidateReq hits 2599system.l2c.UpgradeReq_hits::cpu0.data 24332 # number of UpgradeReq hits 2600system.l2c.UpgradeReq_hits::cpu1.data 31013 # number of UpgradeReq hits 2601system.l2c.UpgradeReq_hits::total 55345 # number of UpgradeReq hits 2602system.l2c.SCUpgradeReq_hits::cpu0.data 5518 # number of SCUpgradeReq hits 2603system.l2c.SCUpgradeReq_hits::cpu1.data 6203 # number of SCUpgradeReq hits 2604system.l2c.SCUpgradeReq_hits::total 11721 # number of SCUpgradeReq hits 2605system.l2c.ReadExReq_hits::cpu0.data 54595 # number of ReadExReq hits 2606system.l2c.ReadExReq_hits::cpu1.data 49708 # number of ReadExReq hits 2607system.l2c.ReadExReq_hits::total 104303 # number of ReadExReq hits 2608system.l2c.demand_hits::cpu0.dtb.walker 5485 # number of demand (read+write) hits 2609system.l2c.demand_hits::cpu0.itb.walker 4305 # number of demand (read+write) hits 2610system.l2c.demand_hits::cpu0.inst 465111 # number of demand (read+write) hits 2611system.l2c.demand_hits::cpu0.data 591379 # number of demand (read+write) hits 2612system.l2c.demand_hits::cpu0.l2cache.prefetcher 265347 # number of demand (read+write) hits 2613system.l2c.demand_hits::cpu1.dtb.walker 5257 # number of demand (read+write) hits 2614system.l2c.demand_hits::cpu1.itb.walker 3875 # number of demand (read+write) hits 2615system.l2c.demand_hits::cpu1.inst 485070 # number of demand (read+write) hits 2616system.l2c.demand_hits::cpu1.data 606196 # number of demand (read+write) hits 2617system.l2c.demand_hits::cpu1.l2cache.prefetcher 285641 # number of demand (read+write) hits 2618system.l2c.demand_hits::total 2717666 # number of demand (read+write) hits 2619system.l2c.overall_hits::cpu0.dtb.walker 5485 # number of overall hits 2620system.l2c.overall_hits::cpu0.itb.walker 4305 # number of overall hits 2621system.l2c.overall_hits::cpu0.inst 465111 # number of overall hits 2622system.l2c.overall_hits::cpu0.data 591379 # number of overall hits 2623system.l2c.overall_hits::cpu0.l2cache.prefetcher 265347 # number of overall hits 2624system.l2c.overall_hits::cpu1.dtb.walker 5257 # number of overall hits 2625system.l2c.overall_hits::cpu1.itb.walker 3875 # number of overall hits 2626system.l2c.overall_hits::cpu1.inst 485070 # number of overall hits 2627system.l2c.overall_hits::cpu1.data 606196 # number of overall hits 2628system.l2c.overall_hits::cpu1.l2cache.prefetcher 285641 # number of overall hits 2629system.l2c.overall_hits::total 2717666 # number of overall hits 2630system.l2c.ReadReq_misses::cpu0.dtb.walker 1889 # number of ReadReq misses 2631system.l2c.ReadReq_misses::cpu0.itb.walker 1930 # number of ReadReq misses 2632system.l2c.ReadReq_misses::cpu0.inst 50597 # number of ReadReq misses 2633system.l2c.ReadReq_misses::cpu0.data 131294 # number of ReadReq misses 2634system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 216525 # number of ReadReq misses 2635system.l2c.ReadReq_misses::cpu1.dtb.walker 2185 # number of ReadReq misses 2636system.l2c.ReadReq_misses::cpu1.itb.walker 2247 # number of ReadReq misses 2637system.l2c.ReadReq_misses::cpu1.inst 47637 # number of ReadReq misses 2638system.l2c.ReadReq_misses::cpu1.data 122248 # number of ReadReq misses 2639system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 240093 # number of ReadReq misses 2640system.l2c.ReadReq_misses::total 816645 # number of ReadReq misses 2641system.l2c.WriteInvalidateReq_misses::cpu0.data 431801 # number of WriteInvalidateReq misses 2642system.l2c.WriteInvalidateReq_misses::cpu1.data 136823 # number of WriteInvalidateReq misses 2643system.l2c.WriteInvalidateReq_misses::total 568624 # number of WriteInvalidateReq misses 2644system.l2c.UpgradeReq_misses::cpu0.data 44180 # number of UpgradeReq misses 2645system.l2c.UpgradeReq_misses::cpu1.data 43907 # number of UpgradeReq misses 2646system.l2c.UpgradeReq_misses::total 88087 # number of UpgradeReq misses 2647system.l2c.SCUpgradeReq_misses::cpu0.data 9646 # number of SCUpgradeReq misses 2648system.l2c.SCUpgradeReq_misses::cpu1.data 11002 # number of SCUpgradeReq misses 2649system.l2c.SCUpgradeReq_misses::total 20648 # number of SCUpgradeReq misses 2650system.l2c.ReadExReq_misses::cpu0.data 78703 # number of ReadExReq misses 2651system.l2c.ReadExReq_misses::cpu1.data 53921 # number of ReadExReq misses 2652system.l2c.ReadExReq_misses::total 132624 # number of ReadExReq misses 2653system.l2c.demand_misses::cpu0.dtb.walker 1889 # number of demand (read+write) misses 2654system.l2c.demand_misses::cpu0.itb.walker 1930 # number of demand (read+write) misses 2655system.l2c.demand_misses::cpu0.inst 50597 # number of demand (read+write) misses 2656system.l2c.demand_misses::cpu0.data 209997 # number of demand (read+write) misses 2657system.l2c.demand_misses::cpu0.l2cache.prefetcher 216525 # number of demand (read+write) misses 2658system.l2c.demand_misses::cpu1.dtb.walker 2185 # number of demand (read+write) misses 2659system.l2c.demand_misses::cpu1.itb.walker 2247 # number of demand (read+write) misses 2660system.l2c.demand_misses::cpu1.inst 47637 # number of demand (read+write) misses 2661system.l2c.demand_misses::cpu1.data 176169 # number of demand (read+write) misses 2662system.l2c.demand_misses::cpu1.l2cache.prefetcher 240093 # number of demand (read+write) misses 2663system.l2c.demand_misses::total 949269 # number of demand (read+write) misses 2664system.l2c.overall_misses::cpu0.dtb.walker 1889 # number of overall misses 2665system.l2c.overall_misses::cpu0.itb.walker 1930 # number of overall misses 2666system.l2c.overall_misses::cpu0.inst 50597 # number of overall misses 2667system.l2c.overall_misses::cpu0.data 209997 # number of overall misses 2668system.l2c.overall_misses::cpu0.l2cache.prefetcher 216525 # number of overall misses 2669system.l2c.overall_misses::cpu1.dtb.walker 2185 # number of overall misses 2670system.l2c.overall_misses::cpu1.itb.walker 2247 # number of overall misses 2671system.l2c.overall_misses::cpu1.inst 47637 # number of overall misses 2672system.l2c.overall_misses::cpu1.data 176169 # number of overall misses 2673system.l2c.overall_misses::cpu1.l2cache.prefetcher 240093 # number of overall misses 2674system.l2c.overall_misses::total 949269 # number of overall misses 2675system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 170785750 # number of ReadReq miss cycles 2676system.l2c.ReadReq_miss_latency::cpu0.itb.walker 176668500 # number of ReadReq miss cycles 2677system.l2c.ReadReq_miss_latency::cpu0.inst 4301026862 # number of ReadReq miss cycles 2678system.l2c.ReadReq_miss_latency::cpu0.data 11907133634 # number of ReadReq miss cycles 2679system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of ReadReq miss cycles 2680system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 192678771 # number of ReadReq miss cycles 2681system.l2c.ReadReq_miss_latency::cpu1.itb.walker 202084771 # number of ReadReq miss cycles 2682system.l2c.ReadReq_miss_latency::cpu1.inst 4020493910 # number of ReadReq miss cycles 2683system.l2c.ReadReq_miss_latency::cpu1.data 11059922872 # number of ReadReq miss cycles 2684system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of ReadReq miss cycles 2685system.l2c.ReadReq_miss_latency::total 90717840977 # number of ReadReq miss cycles 2686system.l2c.WriteInvalidateReq_miss_latency::cpu0.data 51822854 # number of WriteInvalidateReq miss cycles 2687system.l2c.WriteInvalidateReq_miss_latency::cpu1.data 41218687 # number of WriteInvalidateReq miss cycles 2688system.l2c.WriteInvalidateReq_miss_latency::total 93041541 # number of WriteInvalidateReq miss cycles 2689system.l2c.UpgradeReq_miss_latency::cpu0.data 233428095 # number of UpgradeReq miss cycles 2690system.l2c.UpgradeReq_miss_latency::cpu1.data 271641854 # number of UpgradeReq miss cycles 2691system.l2c.UpgradeReq_miss_latency::total 505069949 # number of UpgradeReq miss cycles 2692system.l2c.SCUpgradeReq_miss_latency::cpu0.data 51474876 # number of SCUpgradeReq miss cycles 2693system.l2c.SCUpgradeReq_miss_latency::cpu1.data 56093222 # number of SCUpgradeReq miss cycles 2694system.l2c.SCUpgradeReq_miss_latency::total 107568098 # number of SCUpgradeReq miss cycles 2695system.l2c.ReadExReq_miss_latency::cpu0.data 6900295884 # number of ReadExReq miss cycles 2696system.l2c.ReadExReq_miss_latency::cpu1.data 4492674608 # number of ReadExReq miss cycles 2697system.l2c.ReadExReq_miss_latency::total 11392970492 # number of ReadExReq miss cycles 2698system.l2c.demand_miss_latency::cpu0.dtb.walker 170785750 # number of demand (read+write) miss cycles 2699system.l2c.demand_miss_latency::cpu0.itb.walker 176668500 # number of demand (read+write) miss cycles 2700system.l2c.demand_miss_latency::cpu0.inst 4301026862 # number of demand (read+write) miss cycles 2701system.l2c.demand_miss_latency::cpu0.data 18807429518 # number of demand (read+write) miss cycles 2702system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of demand (read+write) miss cycles 2703system.l2c.demand_miss_latency::cpu1.dtb.walker 192678771 # number of demand (read+write) miss cycles 2704system.l2c.demand_miss_latency::cpu1.itb.walker 202084771 # number of demand (read+write) miss cycles 2705system.l2c.demand_miss_latency::cpu1.inst 4020493910 # number of demand (read+write) miss cycles 2706system.l2c.demand_miss_latency::cpu1.data 15552597480 # number of demand (read+write) miss cycles 2707system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of demand (read+write) miss cycles 2708system.l2c.demand_miss_latency::total 102110811469 # number of demand (read+write) miss cycles 2709system.l2c.overall_miss_latency::cpu0.dtb.walker 170785750 # number of overall miss cycles 2710system.l2c.overall_miss_latency::cpu0.itb.walker 176668500 # number of overall miss cycles 2711system.l2c.overall_miss_latency::cpu0.inst 4301026862 # number of overall miss cycles 2712system.l2c.overall_miss_latency::cpu0.data 18807429518 # number of overall miss cycles 2713system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 27854403488 # number of overall miss cycles 2714system.l2c.overall_miss_latency::cpu1.dtb.walker 192678771 # number of overall miss cycles 2715system.l2c.overall_miss_latency::cpu1.itb.walker 202084771 # number of overall miss cycles 2716system.l2c.overall_miss_latency::cpu1.inst 4020493910 # number of overall miss cycles 2717system.l2c.overall_miss_latency::cpu1.data 15552597480 # number of overall miss cycles 2718system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 30832642419 # number of overall miss cycles 2719system.l2c.overall_miss_latency::total 102110811469 # number of overall miss cycles 2720system.l2c.ReadReq_accesses::cpu0.dtb.walker 7374 # number of ReadReq accesses(hits+misses) 2721system.l2c.ReadReq_accesses::cpu0.itb.walker 6235 # number of ReadReq accesses(hits+misses) 2722system.l2c.ReadReq_accesses::cpu0.inst 515708 # number of ReadReq accesses(hits+misses) 2723system.l2c.ReadReq_accesses::cpu0.data 668078 # number of ReadReq accesses(hits+misses) 2724system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 481872 # number of ReadReq accesses(hits+misses) 2725system.l2c.ReadReq_accesses::cpu1.dtb.walker 7442 # number of ReadReq accesses(hits+misses) 2726system.l2c.ReadReq_accesses::cpu1.itb.walker 6122 # number of ReadReq accesses(hits+misses) 2727system.l2c.ReadReq_accesses::cpu1.inst 532707 # number of ReadReq accesses(hits+misses) 2728system.l2c.ReadReq_accesses::cpu1.data 678736 # number of ReadReq accesses(hits+misses) 2729system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 525734 # number of ReadReq accesses(hits+misses) 2730system.l2c.ReadReq_accesses::total 3430008 # number of ReadReq accesses(hits+misses) 2731system.l2c.Writeback_accesses::writebacks 2374848 # number of Writeback accesses(hits+misses) 2732system.l2c.Writeback_accesses::total 2374848 # number of Writeback accesses(hits+misses) 2733system.l2c.WriteInvalidateReq_accesses::cpu0.data 555265 # number of WriteInvalidateReq accesses(hits+misses) 2734system.l2c.WriteInvalidateReq_accesses::cpu1.data 258449 # number of WriteInvalidateReq accesses(hits+misses) 2735system.l2c.WriteInvalidateReq_accesses::total 813714 # number of WriteInvalidateReq accesses(hits+misses) 2736system.l2c.UpgradeReq_accesses::cpu0.data 68512 # number of UpgradeReq accesses(hits+misses) 2737system.l2c.UpgradeReq_accesses::cpu1.data 74920 # number of UpgradeReq accesses(hits+misses) 2738system.l2c.UpgradeReq_accesses::total 143432 # number of UpgradeReq accesses(hits+misses) 2739system.l2c.SCUpgradeReq_accesses::cpu0.data 15164 # number of SCUpgradeReq accesses(hits+misses) 2740system.l2c.SCUpgradeReq_accesses::cpu1.data 17205 # number of SCUpgradeReq accesses(hits+misses) 2741system.l2c.SCUpgradeReq_accesses::total 32369 # number of SCUpgradeReq accesses(hits+misses) 2742system.l2c.ReadExReq_accesses::cpu0.data 133298 # number of ReadExReq accesses(hits+misses) 2743system.l2c.ReadExReq_accesses::cpu1.data 103629 # number of ReadExReq accesses(hits+misses) 2744system.l2c.ReadExReq_accesses::total 236927 # number of ReadExReq accesses(hits+misses) 2745system.l2c.demand_accesses::cpu0.dtb.walker 7374 # number of demand (read+write) accesses 2746system.l2c.demand_accesses::cpu0.itb.walker 6235 # number of demand (read+write) accesses 2747system.l2c.demand_accesses::cpu0.inst 515708 # number of demand (read+write) accesses 2748system.l2c.demand_accesses::cpu0.data 801376 # number of demand (read+write) accesses 2749system.l2c.demand_accesses::cpu0.l2cache.prefetcher 481872 # number of demand (read+write) accesses 2750system.l2c.demand_accesses::cpu1.dtb.walker 7442 # number of demand (read+write) accesses 2751system.l2c.demand_accesses::cpu1.itb.walker 6122 # number of demand (read+write) accesses 2752system.l2c.demand_accesses::cpu1.inst 532707 # number of demand (read+write) accesses 2753system.l2c.demand_accesses::cpu1.data 782365 # number of demand (read+write) accesses 2754system.l2c.demand_accesses::cpu1.l2cache.prefetcher 525734 # number of demand (read+write) accesses 2755system.l2c.demand_accesses::total 3666935 # number of demand (read+write) accesses 2756system.l2c.overall_accesses::cpu0.dtb.walker 7374 # number of overall (read+write) accesses 2757system.l2c.overall_accesses::cpu0.itb.walker 6235 # number of overall (read+write) accesses 2758system.l2c.overall_accesses::cpu0.inst 515708 # number of overall (read+write) accesses 2759system.l2c.overall_accesses::cpu0.data 801376 # number of overall (read+write) accesses 2760system.l2c.overall_accesses::cpu0.l2cache.prefetcher 481872 # number of overall (read+write) accesses 2761system.l2c.overall_accesses::cpu1.dtb.walker 7442 # number of overall (read+write) accesses 2762system.l2c.overall_accesses::cpu1.itb.walker 6122 # number of overall (read+write) accesses 2763system.l2c.overall_accesses::cpu1.inst 532707 # number of overall (read+write) accesses 2764system.l2c.overall_accesses::cpu1.data 782365 # number of overall (read+write) accesses 2765system.l2c.overall_accesses::cpu1.l2cache.prefetcher 525734 # number of overall (read+write) accesses 2766system.l2c.overall_accesses::total 3666935 # number of overall (read+write) accesses 2767system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for ReadReq accesses 2768system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.309543 # miss rate for ReadReq accesses 2769system.l2c.ReadReq_miss_rate::cpu0.inst 0.098112 # miss rate for ReadReq accesses 2770system.l2c.ReadReq_miss_rate::cpu0.data 0.196525 # miss rate for ReadReq accesses 2771system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for ReadReq accesses 2772system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for ReadReq accesses 2773system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.367037 # miss rate for ReadReq accesses 2774system.l2c.ReadReq_miss_rate::cpu1.inst 0.089424 # miss rate for ReadReq accesses 2775system.l2c.ReadReq_miss_rate::cpu1.data 0.180111 # miss rate for ReadReq accesses 2776system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for ReadReq accesses 2777system.l2c.ReadReq_miss_rate::total 0.238088 # miss rate for ReadReq accesses 2778system.l2c.WriteInvalidateReq_miss_rate::cpu0.data 0.777649 # miss rate for WriteInvalidateReq accesses 2779system.l2c.WriteInvalidateReq_miss_rate::cpu1.data 0.529400 # miss rate for WriteInvalidateReq accesses 2780system.l2c.WriteInvalidateReq_miss_rate::total 0.698801 # miss rate for WriteInvalidateReq accesses 2781system.l2c.UpgradeReq_miss_rate::cpu0.data 0.644851 # miss rate for UpgradeReq accesses 2782system.l2c.UpgradeReq_miss_rate::cpu1.data 0.586052 # miss rate for UpgradeReq accesses 2783system.l2c.UpgradeReq_miss_rate::total 0.614138 # miss rate for UpgradeReq accesses 2784system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.636112 # miss rate for SCUpgradeReq accesses 2785system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.639465 # miss rate for SCUpgradeReq accesses 2786system.l2c.SCUpgradeReq_miss_rate::total 0.637894 # miss rate for SCUpgradeReq accesses 2787system.l2c.ReadExReq_miss_rate::cpu0.data 0.590429 # miss rate for ReadExReq accesses 2788system.l2c.ReadExReq_miss_rate::cpu1.data 0.520327 # miss rate for ReadExReq accesses 2789system.l2c.ReadExReq_miss_rate::total 0.559767 # miss rate for ReadExReq accesses 2790system.l2c.demand_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for demand accesses 2791system.l2c.demand_miss_rate::cpu0.itb.walker 0.309543 # miss rate for demand accesses 2792system.l2c.demand_miss_rate::cpu0.inst 0.098112 # miss rate for demand accesses 2793system.l2c.demand_miss_rate::cpu0.data 0.262046 # miss rate for demand accesses 2794system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for demand accesses 2795system.l2c.demand_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for demand accesses 2796system.l2c.demand_miss_rate::cpu1.itb.walker 0.367037 # miss rate for demand accesses 2797system.l2c.demand_miss_rate::cpu1.inst 0.089424 # miss rate for demand accesses 2798system.l2c.demand_miss_rate::cpu1.data 0.225175 # miss rate for demand accesses 2799system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for demand accesses 2800system.l2c.demand_miss_rate::total 0.258873 # miss rate for demand accesses 2801system.l2c.overall_miss_rate::cpu0.dtb.walker 0.256170 # miss rate for overall accesses 2802system.l2c.overall_miss_rate::cpu0.itb.walker 0.309543 # miss rate for overall accesses 2803system.l2c.overall_miss_rate::cpu0.inst 0.098112 # miss rate for overall accesses 2804system.l2c.overall_miss_rate::cpu0.data 0.262046 # miss rate for overall accesses 2805system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.449341 # miss rate for overall accesses 2806system.l2c.overall_miss_rate::cpu1.dtb.walker 0.293604 # miss rate for overall accesses 2807system.l2c.overall_miss_rate::cpu1.itb.walker 0.367037 # miss rate for overall accesses 2808system.l2c.overall_miss_rate::cpu1.inst 0.089424 # miss rate for overall accesses 2809system.l2c.overall_miss_rate::cpu1.data 0.225175 # miss rate for overall accesses 2810system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.456682 # miss rate for overall accesses 2811system.l2c.overall_miss_rate::total 0.258873 # miss rate for overall accesses 2812system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average ReadReq miss latency 2813system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 91538.082902 # average ReadReq miss latency 2814system.l2c.ReadReq_avg_miss_latency::cpu0.inst 85005.570726 # average ReadReq miss latency 2815system.l2c.ReadReq_avg_miss_latency::cpu0.data 90690.615215 # average ReadReq miss latency 2816system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average ReadReq miss latency 2817system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average ReadReq miss latency 2818system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 89935.367601 # average ReadReq miss latency 2819system.l2c.ReadReq_avg_miss_latency::cpu1.inst 84398.553855 # average ReadReq miss latency 2820system.l2c.ReadReq_avg_miss_latency::cpu1.data 90471.196846 # average ReadReq miss latency 2821system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average ReadReq miss latency 2822system.l2c.ReadReq_avg_miss_latency::total 111086.017764 # average ReadReq miss latency 2823system.l2c.WriteInvalidateReq_avg_miss_latency::cpu0.data 120.015595 # average WriteInvalidateReq miss latency 2824system.l2c.WriteInvalidateReq_avg_miss_latency::cpu1.data 301.255542 # average WriteInvalidateReq miss latency 2825system.l2c.WriteInvalidateReq_avg_miss_latency::total 163.625772 # average WriteInvalidateReq miss latency 2826system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 5283.569375 # average UpgradeReq miss latency 2827system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6186.755050 # average UpgradeReq miss latency 2828system.l2c.UpgradeReq_avg_miss_latency::total 5733.762632 # average UpgradeReq miss latency 2829system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 5336.396019 # average SCUpgradeReq miss latency 2830system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 5098.456826 # average SCUpgradeReq miss latency 2831system.l2c.SCUpgradeReq_avg_miss_latency::total 5209.613425 # average SCUpgradeReq miss latency 2832system.l2c.ReadExReq_avg_miss_latency::cpu0.data 87675.131621 # average ReadExReq miss latency 2833system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83319.571373 # average ReadExReq miss latency 2834system.l2c.ReadExReq_avg_miss_latency::total 85904.289510 # average ReadExReq miss latency 2835system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average overall miss latency 2836system.l2c.demand_avg_miss_latency::cpu0.itb.walker 91538.082902 # average overall miss latency 2837system.l2c.demand_avg_miss_latency::cpu0.inst 85005.570726 # average overall miss latency 2838system.l2c.demand_avg_miss_latency::cpu0.data 89560.467616 # average overall miss latency 2839system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average overall miss latency 2840system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average overall miss latency 2841system.l2c.demand_avg_miss_latency::cpu1.itb.walker 89935.367601 # average overall miss latency 2842system.l2c.demand_avg_miss_latency::cpu1.inst 84398.553855 # average overall miss latency 2843system.l2c.demand_avg_miss_latency::cpu1.data 88282.260103 # average overall miss latency 2844system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average overall miss latency 2845system.l2c.demand_avg_miss_latency::total 107567.835323 # average overall miss latency 2846system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 90410.667020 # average overall miss latency 2847system.l2c.overall_avg_miss_latency::cpu0.itb.walker 91538.082902 # average overall miss latency 2848system.l2c.overall_avg_miss_latency::cpu0.inst 85005.570726 # average overall miss latency 2849system.l2c.overall_avg_miss_latency::cpu0.data 89560.467616 # average overall miss latency 2850system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 128642.897993 # average overall miss latency 2851system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 88182.503890 # average overall miss latency 2852system.l2c.overall_avg_miss_latency::cpu1.itb.walker 89935.367601 # average overall miss latency 2853system.l2c.overall_avg_miss_latency::cpu1.inst 84398.553855 # average overall miss latency 2854system.l2c.overall_avg_miss_latency::cpu1.data 88282.260103 # average overall miss latency 2855system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 128419.580825 # average overall miss latency 2856system.l2c.overall_avg_miss_latency::total 107567.835323 # average overall miss latency 2857system.l2c.blocked_cycles::no_mshrs 328 # number of cycles access was blocked 2858system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 2859system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked 2860system.l2c.blocked::no_targets 0 # number of cycles access was blocked 2861system.l2c.avg_blocked_cycles::no_mshrs 23.428571 # average number of cycles each access was blocked 2862system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2863system.l2c.fast_writes 0 # number of fast writes performed 2864system.l2c.cache_copies 0 # number of cache copies performed 2865system.l2c.writebacks::writebacks 1121159 # number of writebacks 2866system.l2c.writebacks::total 1121159 # number of writebacks 2867system.l2c.ReadReq_mshr_hits::cpu0.inst 120 # number of ReadReq MSHR hits 2868system.l2c.ReadReq_mshr_hits::cpu0.data 25 # number of ReadReq MSHR hits 2869system.l2c.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits 2870system.l2c.ReadReq_mshr_hits::cpu1.inst 120 # number of ReadReq MSHR hits 2871system.l2c.ReadReq_mshr_hits::cpu1.data 30 # number of ReadReq MSHR hits 2872system.l2c.ReadReq_mshr_hits::total 296 # number of ReadReq MSHR hits 2873system.l2c.demand_mshr_hits::cpu0.inst 120 # number of demand (read+write) MSHR hits 2874system.l2c.demand_mshr_hits::cpu0.data 25 # number of demand (read+write) MSHR hits 2875system.l2c.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits 2876system.l2c.demand_mshr_hits::cpu1.inst 120 # number of demand (read+write) MSHR hits 2877system.l2c.demand_mshr_hits::cpu1.data 30 # number of demand (read+write) MSHR hits 2878system.l2c.demand_mshr_hits::total 296 # number of demand (read+write) MSHR hits 2879system.l2c.overall_mshr_hits::cpu0.inst 120 # number of overall MSHR hits 2880system.l2c.overall_mshr_hits::cpu0.data 25 # number of overall MSHR hits 2881system.l2c.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits 2882system.l2c.overall_mshr_hits::cpu1.inst 120 # number of overall MSHR hits 2883system.l2c.overall_mshr_hits::cpu1.data 30 # number of overall MSHR hits 2884system.l2c.overall_mshr_hits::total 296 # number of overall MSHR hits 2885system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 1889 # number of ReadReq MSHR misses 2886system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1930 # number of ReadReq MSHR misses 2887system.l2c.ReadReq_mshr_misses::cpu0.inst 50477 # number of ReadReq MSHR misses 2888system.l2c.ReadReq_mshr_misses::cpu0.data 131269 # number of ReadReq MSHR misses 2889system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of ReadReq MSHR misses 2890system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 2184 # number of ReadReq MSHR misses 2891system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 2247 # number of ReadReq MSHR misses 2892system.l2c.ReadReq_mshr_misses::cpu1.inst 47517 # number of ReadReq MSHR misses 2893system.l2c.ReadReq_mshr_misses::cpu1.data 122218 # number of ReadReq MSHR misses 2894system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of ReadReq MSHR misses 2895system.l2c.ReadReq_mshr_misses::total 816349 # number of ReadReq MSHR misses 2896system.l2c.WriteInvalidateReq_mshr_misses::cpu0.data 431801 # number of WriteInvalidateReq MSHR misses 2897system.l2c.WriteInvalidateReq_mshr_misses::cpu1.data 136823 # number of WriteInvalidateReq MSHR misses 2898system.l2c.WriteInvalidateReq_mshr_misses::total 568624 # number of WriteInvalidateReq MSHR misses 2899system.l2c.UpgradeReq_mshr_misses::cpu0.data 44180 # number of UpgradeReq MSHR misses 2900system.l2c.UpgradeReq_mshr_misses::cpu1.data 43907 # number of UpgradeReq MSHR misses 2901system.l2c.UpgradeReq_mshr_misses::total 88087 # number of UpgradeReq MSHR misses 2902system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 9646 # number of SCUpgradeReq MSHR misses 2903system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 11002 # number of SCUpgradeReq MSHR misses 2904system.l2c.SCUpgradeReq_mshr_misses::total 20648 # number of SCUpgradeReq MSHR misses 2905system.l2c.ReadExReq_mshr_misses::cpu0.data 78703 # number of ReadExReq MSHR misses 2906system.l2c.ReadExReq_mshr_misses::cpu1.data 53921 # number of ReadExReq MSHR misses 2907system.l2c.ReadExReq_mshr_misses::total 132624 # number of ReadExReq MSHR misses 2908system.l2c.demand_mshr_misses::cpu0.dtb.walker 1889 # number of demand (read+write) MSHR misses 2909system.l2c.demand_mshr_misses::cpu0.itb.walker 1930 # number of demand (read+write) MSHR misses 2910system.l2c.demand_mshr_misses::cpu0.inst 50477 # number of demand (read+write) MSHR misses 2911system.l2c.demand_mshr_misses::cpu0.data 209972 # number of demand (read+write) MSHR misses 2912system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of demand (read+write) MSHR misses 2913system.l2c.demand_mshr_misses::cpu1.dtb.walker 2184 # number of demand (read+write) MSHR misses 2914system.l2c.demand_mshr_misses::cpu1.itb.walker 2247 # number of demand (read+write) MSHR misses 2915system.l2c.demand_mshr_misses::cpu1.inst 47517 # number of demand (read+write) MSHR misses 2916system.l2c.demand_mshr_misses::cpu1.data 176139 # number of demand (read+write) MSHR misses 2917system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of demand (read+write) MSHR misses 2918system.l2c.demand_mshr_misses::total 948973 # number of demand (read+write) MSHR misses 2919system.l2c.overall_mshr_misses::cpu0.dtb.walker 1889 # number of overall MSHR misses 2920system.l2c.overall_mshr_misses::cpu0.itb.walker 1930 # number of overall MSHR misses 2921system.l2c.overall_mshr_misses::cpu0.inst 50477 # number of overall MSHR misses 2922system.l2c.overall_mshr_misses::cpu0.data 209972 # number of overall MSHR misses 2923system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 216525 # number of overall MSHR misses 2924system.l2c.overall_mshr_misses::cpu1.dtb.walker 2184 # number of overall MSHR misses 2925system.l2c.overall_mshr_misses::cpu1.itb.walker 2247 # number of overall MSHR misses 2926system.l2c.overall_mshr_misses::cpu1.inst 47517 # number of overall MSHR misses 2927system.l2c.overall_mshr_misses::cpu1.data 176139 # number of overall MSHR misses 2928system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 240093 # number of overall MSHR misses 2929system.l2c.overall_mshr_misses::total 948973 # number of overall MSHR misses 2930system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 43125 # number of ReadReq MSHR uncacheable 2931system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16584 # number of ReadReq MSHR uncacheable 2932system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 110 # number of ReadReq MSHR uncacheable 2933system.l2c.ReadReq_mshr_uncacheable::cpu1.data 21723 # number of ReadReq MSHR uncacheable 2934system.l2c.ReadReq_mshr_uncacheable::total 81542 # number of ReadReq MSHR uncacheable 2935system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18033 # number of WriteReq MSHR uncacheable 2936system.l2c.WriteReq_mshr_uncacheable::cpu1.data 20113 # number of WriteReq MSHR uncacheable 2937system.l2c.WriteReq_mshr_uncacheable::total 38146 # number of WriteReq MSHR uncacheable 2938system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 43125 # number of overall MSHR uncacheable misses 2939system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34617 # number of overall MSHR uncacheable misses 2940system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 110 # number of overall MSHR uncacheable misses 2941system.l2c.overall_mshr_uncacheable_misses::cpu1.data 41836 # number of overall MSHR uncacheable misses 2942system.l2c.overall_mshr_uncacheable_misses::total 119688 # number of overall MSHR uncacheable misses 2943system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of ReadReq MSHR miss cycles 2944system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 152273500 # number of ReadReq MSHR miss cycles 2945system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 3658828888 # number of ReadReq MSHR miss cycles 2946system.l2c.ReadReq_mshr_miss_latency::cpu0.data 10259837116 # number of ReadReq MSHR miss cycles 2947system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of ReadReq MSHR miss cycles 2948system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of ReadReq MSHR miss cycles 2949system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 173733729 # number of ReadReq MSHR miss cycles 2950system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3415229090 # number of ReadReq MSHR miss cycles 2951system.l2c.ReadReq_mshr_miss_latency::cpu1.data 9525126628 # number of ReadReq MSHR miss cycles 2952system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of ReadReq MSHR miss cycles 2953system.l2c.ReadReq_mshr_miss_latency::total 80569024173 # number of ReadReq MSHR miss cycles 2954system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu0.data 13996588148 # number of WriteInvalidateReq MSHR miss cycles 2955system.l2c.WriteInvalidateReq_mshr_miss_latency::cpu1.data 4310102313 # number of WriteInvalidateReq MSHR miss cycles 2956system.l2c.WriteInvalidateReq_mshr_miss_latency::total 18306690461 # number of WriteInvalidateReq MSHR miss cycles 2957system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 786063539 # number of UpgradeReq MSHR miss cycles 2958system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 780665261 # number of UpgradeReq MSHR miss cycles 2959system.l2c.UpgradeReq_mshr_miss_latency::total 1566728800 # number of UpgradeReq MSHR miss cycles 2960system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 172133111 # number of SCUpgradeReq MSHR miss cycles 2961system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 196209961 # number of SCUpgradeReq MSHR miss cycles 2962system.l2c.SCUpgradeReq_mshr_miss_latency::total 368343072 # number of SCUpgradeReq MSHR miss cycles 2963system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 5916837616 # number of ReadExReq MSHR miss cycles 2964system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3817995892 # number of ReadExReq MSHR miss cycles 2965system.l2c.ReadExReq_mshr_miss_latency::total 9734833508 # number of ReadExReq MSHR miss cycles 2966system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of demand (read+write) MSHR miss cycles 2967system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 152273500 # number of demand (read+write) MSHR miss cycles 2968system.l2c.demand_mshr_miss_latency::cpu0.inst 3658828888 # number of demand (read+write) MSHR miss cycles 2969system.l2c.demand_mshr_miss_latency::cpu0.data 16176674732 # number of demand (read+write) MSHR miss cycles 2970system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of demand (read+write) MSHR miss cycles 2971system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of demand (read+write) MSHR miss cycles 2972system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 173733729 # number of demand (read+write) MSHR miss cycles 2973system.l2c.demand_mshr_miss_latency::cpu1.inst 3415229090 # number of demand (read+write) MSHR miss cycles 2974system.l2c.demand_mshr_miss_latency::cpu1.data 13343122520 # number of demand (read+write) MSHR miss cycles 2975system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of demand (read+write) MSHR miss cycles 2976system.l2c.demand_mshr_miss_latency::total 90303857681 # number of demand (read+write) MSHR miss cycles 2977system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 146937750 # number of overall MSHR miss cycles 2978system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 152273500 # number of overall MSHR miss cycles 2979system.l2c.overall_mshr_miss_latency::cpu0.inst 3658828888 # number of overall MSHR miss cycles 2980system.l2c.overall_mshr_miss_latency::cpu0.data 16176674732 # number of overall MSHR miss cycles 2981system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 25193281260 # number of overall MSHR miss cycles 2982system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 165099729 # number of overall MSHR miss cycles 2983system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 173733729 # number of overall MSHR miss cycles 2984system.l2c.overall_mshr_miss_latency::cpu1.inst 3415229090 # number of overall MSHR miss cycles 2985system.l2c.overall_mshr_miss_latency::cpu1.data 13343122520 # number of overall MSHR miss cycles 2986system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 27878676483 # number of overall MSHR miss cycles 2987system.l2c.overall_mshr_miss_latency::total 90303857681 # number of overall MSHR miss cycles 2988system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of ReadReq MSHR uncacheable cycles 2989system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2243809000 # number of ReadReq MSHR uncacheable cycles 2990system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 7049250 # number of ReadReq MSHR uncacheable cycles 2991system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3129187250 # number of ReadReq MSHR uncacheable cycles 2992system.l2c.ReadReq_mshr_uncacheable_latency::total 7985805000 # number of ReadReq MSHR uncacheable cycles 2993system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2322501000 # number of WriteReq MSHR uncacheable cycles 2994system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2942063000 # number of WriteReq MSHR uncacheable cycles 2995system.l2c.WriteReq_mshr_uncacheable_latency::total 5264564000 # number of WriteReq MSHR uncacheable cycles 2996system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 2605759500 # number of overall MSHR uncacheable cycles 2997system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4566310000 # number of overall MSHR uncacheable cycles 2998system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 7049250 # number of overall MSHR uncacheable cycles 2999system.l2c.overall_mshr_uncacheable_latency::cpu1.data 6071250250 # number of overall MSHR uncacheable cycles 3000system.l2c.overall_mshr_uncacheable_latency::total 13250369000 # number of overall MSHR uncacheable cycles 3001system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for ReadReq accesses 3002system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for ReadReq accesses 3003system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for ReadReq accesses 3004system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.196488 # mshr miss rate for ReadReq accesses 3005system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for ReadReq accesses 3006system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for ReadReq accesses 3007system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for ReadReq accesses 3008system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for ReadReq accesses 3009system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.180067 # mshr miss rate for ReadReq accesses 3010system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for ReadReq accesses 3011system.l2c.ReadReq_mshr_miss_rate::total 0.238002 # mshr miss rate for ReadReq accesses 3012system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu0.data 0.777649 # mshr miss rate for WriteInvalidateReq accesses 3013system.l2c.WriteInvalidateReq_mshr_miss_rate::cpu1.data 0.529400 # mshr miss rate for WriteInvalidateReq accesses 3014system.l2c.WriteInvalidateReq_mshr_miss_rate::total 0.698801 # mshr miss rate for WriteInvalidateReq accesses 3015system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.644851 # mshr miss rate for UpgradeReq accesses 3016system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.586052 # mshr miss rate for UpgradeReq accesses 3017system.l2c.UpgradeReq_mshr_miss_rate::total 0.614138 # mshr miss rate for UpgradeReq accesses 3018system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.636112 # mshr miss rate for SCUpgradeReq accesses 3019system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.639465 # mshr miss rate for SCUpgradeReq accesses 3020system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.637894 # mshr miss rate for SCUpgradeReq accesses 3021system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.590429 # mshr miss rate for ReadExReq accesses 3022system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.520327 # mshr miss rate for ReadExReq accesses 3023system.l2c.ReadExReq_mshr_miss_rate::total 0.559767 # mshr miss rate for ReadExReq accesses 3024system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for demand accesses 3025system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for demand accesses 3026system.l2c.demand_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for demand accesses 3027system.l2c.demand_mshr_miss_rate::cpu0.data 0.262014 # mshr miss rate for demand accesses 3028system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for demand accesses 3029system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for demand accesses 3030system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for demand accesses 3031system.l2c.demand_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for demand accesses 3032system.l2c.demand_mshr_miss_rate::cpu1.data 0.225137 # mshr miss rate for demand accesses 3033system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for demand accesses 3034system.l2c.demand_mshr_miss_rate::total 0.258792 # mshr miss rate for demand accesses 3035system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.256170 # mshr miss rate for overall accesses 3036system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.309543 # mshr miss rate for overall accesses 3037system.l2c.overall_mshr_miss_rate::cpu0.inst 0.097879 # mshr miss rate for overall accesses 3038system.l2c.overall_mshr_miss_rate::cpu0.data 0.262014 # mshr miss rate for overall accesses 3039system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.449341 # mshr miss rate for overall accesses 3040system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.293469 # mshr miss rate for overall accesses 3041system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.367037 # mshr miss rate for overall accesses 3042system.l2c.overall_mshr_miss_rate::cpu1.inst 0.089199 # mshr miss rate for overall accesses 3043system.l2c.overall_mshr_miss_rate::cpu1.data 0.225137 # mshr miss rate for overall accesses 3044system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456682 # mshr miss rate for overall accesses 3045system.l2c.overall_mshr_miss_rate::total 0.258792 # mshr miss rate for overall accesses 3046system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average ReadReq mshr miss latency 3047system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average ReadReq mshr miss latency 3048system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average ReadReq mshr miss latency 3049system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78158.873123 # average ReadReq mshr miss latency 3050system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average ReadReq mshr miss latency 3051system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average ReadReq mshr miss latency 3052system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average ReadReq mshr miss latency 3053system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average ReadReq mshr miss latency 3054system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 77935.546548 # average ReadReq mshr miss latency 3055system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average ReadReq mshr miss latency 3056system.l2c.ReadReq_avg_mshr_miss_latency::total 98694.338050 # average ReadReq mshr miss latency 3057system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data 32414.441254 # average WriteInvalidateReq mshr miss latency 3058system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data 31501.299584 # average WriteInvalidateReq mshr miss latency 3059system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total 32194.719992 # average WriteInvalidateReq mshr miss latency 3060system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17792.293775 # average UpgradeReq mshr miss latency 3061system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17779.972692 # average UpgradeReq mshr miss latency 3062system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17786.152327 # average UpgradeReq mshr miss latency 3063system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17845.024984 # average SCUpgradeReq mshr miss latency 3064system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17834.026632 # average SCUpgradeReq mshr miss latency 3065system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17839.164665 # average SCUpgradeReq mshr miss latency 3066system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 75179.314842 # average ReadExReq mshr miss latency 3067system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70807.215964 # average ReadExReq mshr miss latency 3068system.l2c.ReadExReq_avg_mshr_miss_latency::total 73401.748613 # average ReadExReq mshr miss latency 3069system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average overall mshr miss latency 3070system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average overall mshr miss latency 3071system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average overall mshr miss latency 3072system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77042.056712 # average overall mshr miss latency 3073system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average overall mshr miss latency 3074system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average overall mshr miss latency 3075system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average overall mshr miss latency 3076system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average overall mshr miss latency 3077system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75753.368192 # average overall mshr miss latency 3078system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average overall mshr miss latency 3079system.l2c.demand_avg_mshr_miss_latency::total 95159.564794 # average overall mshr miss latency 3080system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 77785.997882 # average overall mshr miss latency 3081system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 78898.186528 # average overall mshr miss latency 3082system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72485.070190 # average overall mshr miss latency 3083system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77042.056712 # average overall mshr miss latency 3084system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 116352.759543 # average overall mshr miss latency 3085system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75595.114011 # average overall mshr miss latency 3086system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77318.081442 # average overall mshr miss latency 3087system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71873.836522 # average overall mshr miss latency 3088system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75753.368192 # average overall mshr miss latency 3089system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 116116.157002 # average overall mshr miss latency 3090system.l2c.overall_avg_mshr_miss_latency::total 95159.564794 # average overall mshr miss latency 3091system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696 # average ReadReq mshr uncacheable latency 3092system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 135299.626146 # average ReadReq mshr uncacheable latency 3093system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909 # average ReadReq mshr uncacheable latency 3094system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 144049.498228 # average ReadReq mshr uncacheable latency 3095system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 97934.867921 # average ReadReq mshr uncacheable latency 3096system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 128791.715189 # average WriteReq mshr uncacheable latency 3097system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146276.686720 # average WriteReq mshr uncacheable latency 3098system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138010.905468 # average WriteReq mshr uncacheable latency 3099system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60423.408696 # average overall mshr uncacheable latency 3100system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 131909.466447 # average overall mshr uncacheable latency 3101system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64084.090909 # average overall mshr uncacheable latency 3102system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 145120.237355 # average overall mshr uncacheable latency 3103system.l2c.overall_avg_mshr_uncacheable_latency::total 110707.581378 # average overall mshr uncacheable latency 3104system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 3105system.membus.trans_dist::ReadReq 906809 # Transaction distribution 3106system.membus.trans_dist::ReadResp 906809 # Transaction distribution 3107system.membus.trans_dist::WriteReq 38146 # Transaction distribution 3108system.membus.trans_dist::WriteResp 38146 # Transaction distribution 3109system.membus.trans_dist::Writeback 1227861 # Transaction distribution 3110system.membus.trans_dist::WriteInvalidateReq 672387 # Transaction distribution 3111system.membus.trans_dist::WriteInvalidateResp 672387 # Transaction distribution 3112system.membus.trans_dist::UpgradeReq 370275 # Transaction distribution 3113system.membus.trans_dist::SCUpgradeReq 320224 # Transaction distribution 3114system.membus.trans_dist::UpgradeResp 115346 # Transaction distribution 3115system.membus.trans_dist::SCUpgradeFailReq 24 # Transaction distribution 3116system.membus.trans_dist::ReadExReq 145002 # Transaction distribution 3117system.membus.trans_dist::ReadExResp 128981 # Transaction distribution 3118system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122716 # Packet count per connected master and slave (bytes) 3119system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes) 3120system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24970 # Packet count per connected master and slave (bytes) 3121system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5055890 # Packet count per connected master and slave (bytes) 3122system.membus.pkt_count_system.l2c.mem_side::total 5203668 # Packet count per connected master and slave (bytes) 3123system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 335590 # Packet count per connected master and slave (bytes) 3124system.membus.pkt_count_system.iocache.mem_side::total 335590 # Packet count per connected master and slave (bytes) 3125system.membus.pkt_count::total 5539258 # Packet count per connected master and slave (bytes) 3126system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155823 # Cumulative packet size per connected master and slave (bytes) 3127system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes) 3128system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 49940 # Cumulative packet size per connected master and slave (bytes) 3129system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 168605292 # Cumulative packet size per connected master and slave (bytes) 3130system.membus.pkt_size_system.l2c.mem_side::total 168811259 # Cumulative packet size per connected master and slave (bytes) 3131system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 14076224 # Cumulative packet size per connected master and slave (bytes) 3132system.membus.pkt_size_system.iocache.mem_side::total 14076224 # Cumulative packet size per connected master and slave (bytes) 3133system.membus.pkt_size::total 182887483 # Cumulative packet size per connected master and slave (bytes) 3134system.membus.snoops 594337 # Total snoops (count) 3135system.membus.snoop_fanout::samples 3681134 # Request fanout histogram 3136system.membus.snoop_fanout::mean 1 # Request fanout histogram 3137system.membus.snoop_fanout::stdev 0 # Request fanout histogram 3138system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3139system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3140system.membus.snoop_fanout::1 3681134 100.00% 100.00% # Request fanout histogram 3141system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3142system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3143system.membus.snoop_fanout::min_value 1 # Request fanout histogram 3144system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3145system.membus.snoop_fanout::total 3681134 # Request fanout histogram 3146system.membus.reqLayer0.occupancy 100790999 # Layer occupancy (ticks) 3147system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3148system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks) 3149system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3150system.membus.reqLayer2.occupancy 21573500 # Layer occupancy (ticks) 3151system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3152system.membus.reqLayer5.occupancy 11112792344 # Layer occupancy (ticks) 3153system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3154system.membus.respLayer2.occupancy 5991933811 # Layer occupancy (ticks) 3155system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3156system.membus.respLayer3.occupancy 151912879 # Layer occupancy (ticks) 3157system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3158system.realview.ethernet.txBytes 966 # Bytes Transmitted 3159system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3160system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3161system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3162system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3163system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3164system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3165system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3166system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3167system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3168system.realview.ethernet.totPackets 3 # Total Packets 3169system.realview.ethernet.totBytes 966 # Total Bytes 3170system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3171system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3172system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3173system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3174system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3175system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3176system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3177system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3178system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3179system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3180system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3181system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3182system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3183system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3184system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3185system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3186system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3187system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3188system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3189system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3190system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3191system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3192system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3193system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3194system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3195system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3196system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3197system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3198system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3199system.realview.ethernet.droppedPackets 0 # number of packets dropped 3200system.toL2Bus.trans_dist::ReadReq 4327568 # Transaction distribution 3201system.toL2Bus.trans_dist::ReadResp 4320333 # Transaction distribution 3202system.toL2Bus.trans_dist::WriteReq 38146 # Transaction distribution 3203system.toL2Bus.trans_dist::WriteResp 38146 # Transaction distribution 3204system.toL2Bus.trans_dist::Writeback 2374848 # Transaction distribution 3205system.toL2Bus.trans_dist::WriteInvalidateReq 920665 # Transaction distribution 3206system.toL2Bus.trans_dist::WriteInvalidateResp 813714 # Transaction distribution 3207system.toL2Bus.trans_dist::UpgradeReq 419012 # Transaction distribution 3208system.toL2Bus.trans_dist::SCUpgradeReq 331945 # Transaction distribution 3209system.toL2Bus.trans_dist::UpgradeResp 750957 # Transaction distribution 3210system.toL2Bus.trans_dist::SCUpgradeFailReq 86 # Transaction distribution 3211system.toL2Bus.trans_dist::UpgradeFailResp 86 # Transaction distribution 3212system.toL2Bus.trans_dist::ReadExReq 292509 # Transaction distribution 3213system.toL2Bus.trans_dist::ReadExResp 292509 # Transaction distribution 3214system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 7096014 # Packet count per connected master and slave (bytes) 3215system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6270717 # Packet count per connected master and slave (bytes) 3216system.toL2Bus.pkt_count::total 13366731 # Packet count per connected master and slave (bytes) 3217system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 236480377 # Cumulative packet size per connected master and slave (bytes) 3218system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 202778754 # Cumulative packet size per connected master and slave (bytes) 3219system.toL2Bus.pkt_size::total 439259131 # Cumulative packet size per connected master and slave (bytes) 3220system.toL2Bus.snoops 1555479 # Total snoops (count) 3221system.toL2Bus.snoop_fanout::samples 8704899 # Request fanout histogram 3222system.toL2Bus.snoop_fanout::mean 1.013311 # Request fanout histogram 3223system.toL2Bus.snoop_fanout::stdev 0.114603 # Request fanout histogram 3224system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3225system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 3226system.toL2Bus.snoop_fanout::1 8589027 98.67% 98.67% # Request fanout histogram 3227system.toL2Bus.snoop_fanout::2 115872 1.33% 100.00% # Request fanout histogram 3228system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3229system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 3230system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3231system.toL2Bus.snoop_fanout::total 8704899 # Request fanout histogram 3232system.toL2Bus.reqLayer0.occupancy 7795939791 # Layer occupancy (ticks) 3233system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3234system.toL2Bus.snoopLayer0.occupancy 2526000 # Layer occupancy (ticks) 3235system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3236system.toL2Bus.respLayer0.occupancy 3978610795 # Layer occupancy (ticks) 3237system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3238system.toL2Bus.respLayer1.occupancy 3846379763 # Layer occupancy (ticks) 3239system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3240 3241---------- End Simulation Statistics ---------- 3242