xref: /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview64-o3-dual/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                 47.384943                       # Number of seconds simulated
sim_ticks                                47384942719000                       # Number of ticks simulated
final_tick                               47384942719000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 146603                       # Simulator instruction rate (inst/s)
host_op_rate                                   172405                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                             7419029838                       # Simulator tick rate (ticks/s)
host_mem_usage                                 776468                       # Number of bytes of host memory used
host_seconds                                  6386.95                       # Real time elapsed on the host
sim_insts                                   936348150                       # Number of instructions simulated
sim_ops                                    1101141201                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.physmem.bytes_read::cpu0.dtb.walker       225984                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker       211072                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst          4210272                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data         17875336                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.l2cache.prefetcher     22288384                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker       132032                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker        98944                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst          3431264                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data         10538960                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.l2cache.prefetcher     15414592                       # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide        437696                       # Number of bytes read from this memory
system.physmem.bytes_read::total             74864536                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst      4210272                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst      3431264                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total         7641536                       # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks     90448704                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data         20580                       # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data             4                       # Number of bytes written to this memory
system.physmem.bytes_written::total          90469288                       # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker         3531                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker         3298                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst             81738                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data            279315                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.l2cache.prefetcher       348256                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker         2063                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker         1546                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst             53657                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data            164684                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.l2cache.prefetcher       240853                       # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide           6839                       # Number of read requests responded to by this memory
system.physmem.num_reads::total               1185780                       # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks         1413261                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data             2573                       # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data                1                       # Number of write requests responded to by this memory
system.physmem.num_writes::total              1415835                       # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker          4769                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker          4454                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst               88853                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data              377237                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.l2cache.prefetcher       470368                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker          2786                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker          2088                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst               72413                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data              222412                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.l2cache.prefetcher       325306                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide             9237                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 1579922                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst          88853                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst          72413                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total             161265                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks           1908807                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data                434                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data                  0                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total                1909241                       # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks           1908807                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker         4769                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker         4454                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst              88853                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data             377671                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.l2cache.prefetcher       470368                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker         2786                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker         2088                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst              72413                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data             222412                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.l2cache.prefetcher       325306                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide            9237                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                3489164                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                       1185780                       # Number of read requests accepted
system.physmem.writeReqs                      1415835                       # Number of write requests accepted
system.physmem.readBursts                     1185780                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                    1415835                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                 75867200                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                     22720                       # Total number of bytes read from write queue
system.physmem.bytesWritten                  90467840                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                  74864536                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys               90469288                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                      355                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                    2247                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0               74918                       # Per bank write bursts
system.physmem.perBankRdBursts::1               82946                       # Per bank write bursts
system.physmem.perBankRdBursts::2               75146                       # Per bank write bursts
system.physmem.perBankRdBursts::3               74319                       # Per bank write bursts
system.physmem.perBankRdBursts::4               73960                       # Per bank write bursts
system.physmem.perBankRdBursts::5               83356                       # Per bank write bursts
system.physmem.perBankRdBursts::6               71088                       # Per bank write bursts
system.physmem.perBankRdBursts::7               75076                       # Per bank write bursts
system.physmem.perBankRdBursts::8               69225                       # Per bank write bursts
system.physmem.perBankRdBursts::9               91582                       # Per bank write bursts
system.physmem.perBankRdBursts::10              63014                       # Per bank write bursts
system.physmem.perBankRdBursts::11              68676                       # Per bank write bursts
system.physmem.perBankRdBursts::12              68042                       # Per bank write bursts
system.physmem.perBankRdBursts::13              71091                       # Per bank write bursts
system.physmem.perBankRdBursts::14              73017                       # Per bank write bursts
system.physmem.perBankRdBursts::15              69969                       # Per bank write bursts
system.physmem.perBankWrBursts::0               88621                       # Per bank write bursts
system.physmem.perBankWrBursts::1               92960                       # Per bank write bursts
system.physmem.perBankWrBursts::2               88280                       # Per bank write bursts
system.physmem.perBankWrBursts::3               90026                       # Per bank write bursts
system.physmem.perBankWrBursts::4               89701                       # Per bank write bursts
system.physmem.perBankWrBursts::5               97248                       # Per bank write bursts
system.physmem.perBankWrBursts::6               87218                       # Per bank write bursts
system.physmem.perBankWrBursts::7               89230                       # Per bank write bursts
system.physmem.perBankWrBursts::8               86326                       # Per bank write bursts
system.physmem.perBankWrBursts::9               88636                       # Per bank write bursts
system.physmem.perBankWrBursts::10              82100                       # Per bank write bursts
system.physmem.perBankWrBursts::11              87622                       # Per bank write bursts
system.physmem.perBankWrBursts::12              86001                       # Per bank write bursts
system.physmem.perBankWrBursts::13              87485                       # Per bank write bursts
system.physmem.perBankWrBursts::14              85741                       # Per bank write bursts
system.physmem.perBankWrBursts::15              86365                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                       51113                       # Number of times write queue was full causing retry
system.physmem.totGap                    47384941205500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                      25                       # Read request sizes (log2)
system.physmem.readPktSize::4                   21333                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                 1164422                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      2                       # Write request sizes (log2)
system.physmem.writePktSize::3                   2572                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                1413261                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                    492558                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                    272193                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                    123866                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                     77106                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                     49827                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                     41505                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                     37948                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                     35214                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                     31591                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                      9310                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                     5210                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                     3059                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                     1824                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                     1397                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                      811                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                      674                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                      576                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                      471                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                      162                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                      110                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                       10                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        3                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        1                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                    22656                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                    26213                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                    37414                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                    43560                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                    48703                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                    53588                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                    59870                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                    65839                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                    71191                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                    73927                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                    78606                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                    82389                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                    81499                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                    83906                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                    89741                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                    97285                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                    86545                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                    80600                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                     8679                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                     5080                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                     3802                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                     2902                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                     2352                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                     2103                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                     1842                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                     1736                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                     1672                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                     1659                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                     1715                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                     1682                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                     1630                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                     1838                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                     1694                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                     1790                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                     1915                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                     1936                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                     2089                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                     2158                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                     2578                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                     2909                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                     3105                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                     3321                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                     3357                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                     3394                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                     4009                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                     5197                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                     6401                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                    25051                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                   120445                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples      1083045                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      153.580618                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean     102.695829                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     199.684011                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127         694535     64.13%     64.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255       223527     20.64%     84.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383        61545      5.68%     90.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511        27125      2.50%     92.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639        21919      2.02%     94.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767        12312      1.14%     96.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895         8465      0.78%     96.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023         6818      0.63%     97.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151        26799      2.47%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total        1083045                       # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples         67614                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean        17.532168                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev       68.484066                       # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-511           67610     99.99%     99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::512-1023            2      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::10240-10751            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::13824-14335            1      0.00%    100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total           67614                       # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples         67614                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean        20.906321                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean       17.453992                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev      533.973047                       # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-2047          67611    100.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12288-14335            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::43008-45055            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::129024-131071            1      0.00%    100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total           67614                       # Writes before turning the bus around for reads
system.physmem.totQLat                    72498378118                       # Total ticks spent queuing
system.physmem.totMemAccLat               94725096868                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                   5927125000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       61158.13                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  79908.13                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           1.60                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           1.91                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        1.58                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        1.91                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.03                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.01                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.01                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.24                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                        24.94                       # Average write queue length when enqueuing
system.physmem.readRowHits                     894792                       # Number of row buffer hits during reads
system.physmem.writeRowHits                    621147                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   75.48                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                  43.94                       # Row buffer hit rate for writes
system.physmem.avgGap                     18213663.90                       # Average gap between requests
system.physmem.pageHitRate                      58.33                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                 4041154320                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                 2147920665                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                4361176260                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy               3775542480                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy           33222521280.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            42262106220                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy             1577144160                       # Energy for precharge background per rank (pJ)
system.physmem_0.actPowerDownEnergy       67404809070                       # Energy for active power-down per rank (pJ)
system.physmem_0.prePowerDownEnergy       44351104800                       # Energy for precharge power-down per rank (pJ)
system.physmem_0.selfRefreshEnergy       11290594038405                       # Energy for self refresh per rank (pJ)
system.physmem_0.totalEnergy             11493753562350                       # Total energy per rank (pJ)
system.physmem_0.averagePower              242.561305                       # Core power per rank (mW)
system.physmem_0.totalIdleTime           47288119152834                       # Total Idle time Per DRAM Rank
system.physmem_0.memoryStateTime::IDLE     2641670410                       # Time in different power states
system.physmem_0.memoryStateTime::REF     14105156000                       # Time in different power states
system.physmem_0.memoryStateTime::SREF   47024804557250                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 115497548988                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     80076687506                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 147817098846                       # Time in different power states
system.physmem_1.actEnergy                 3691794120                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                 1962235110                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                4102758240                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy               3603240720                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy           31839581280.000008                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy            42875044890                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy             1564584000                       # Energy for precharge background per rank (pJ)
system.physmem_1.actPowerDownEnergy       59886050220                       # Energy for active power-down per rank (pJ)
system.physmem_1.prePowerDownEnergy       43118785440                       # Energy for precharge power-down per rank (pJ)
system.physmem_1.selfRefreshEnergy       11295073117425                       # Energy for self refresh per rank (pJ)
system.physmem_1.totalEnergy             11487733544595                       # Total energy per rank (pJ)
system.physmem_1.averagePower              242.434260                       # Core power per rank (mW)
system.physmem_1.totalIdleTime           47286801320918                       # Total Idle time Per DRAM Rank
system.physmem_1.memoryStateTime::IDLE     2657158504                       # Time in different power states
system.physmem_1.memoryStateTime::REF     13520630000                       # Time in different power states
system.physmem_1.memoryStateTime::SREF   47043190241000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 112288389331                       # Time in different power states
system.physmem_1.memoryStateTime::ACT     81956603828                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 131329696337                       # Time in different power states
system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.nvmem.bytes_read::cpu0.inst          368                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data           36                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst          144                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.data            8                       # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total           556                       # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst          368                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu1.inst          144                       # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total          512                       # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst           23                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu0.data            5                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.inst            9                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::cpu1.data            1                       # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total             38                       # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst            8                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu0.data            1                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.inst            3                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::cpu1.data            0                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total               12                       # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst            8                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu1.inst            3                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total           11                       # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst            8                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.data            1                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst            3                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data            0                       # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total              12                       # Total bandwidth to/from this memory (bytes/s)
system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.bridge.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cf0.dma_read_full_pages                    122                       # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes                      499712                       # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs                           122                       # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages                  1667                       # Number of full page size DMA writes.
system.cf0.dma_write_bytes                    6830592                       # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs                         1670                       # Number of DMA write transactions.
system.cpu0.branchPred.lookups              139745078                       # Number of BP lookups
system.cpu0.branchPred.condPredicted         92256746                       # Number of conditional branches predicted
system.cpu0.branchPred.condIncorrect          6767345                       # Number of conditional branches incorrect
system.cpu0.branchPred.BTBLookups            98774130                       # Number of BTB lookups
system.cpu0.branchPred.BTBHits               61692324                       # Number of BTB hits
system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu0.branchPred.BTBHitPct            62.457978                       # BTB Hit Percentage
system.cpu0.branchPred.usedRAS               19130272                       # Number of times the RAS was used to get a target.
system.cpu0.branchPred.RASInCorrect            187780                       # Number of incorrect RAS predictions.
system.cpu0.branchPred.indirectLookups        4236971                       # Number of indirect predictor lookups.
system.cpu0.branchPred.indirectHits           2716946                       # Number of indirect target hits.
system.cpu0.branchPred.indirectMisses         1520025                       # Number of indirect misses.
system.cpu0.branchPredindirectMispredicted       386103                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.dtb.walker.walks                   642249                       # Table walker walks requested
system.cpu0.dtb.walker.walksLong               642249                       # Table walker walks initiated with long descriptors
system.cpu0.dtb.walker.walksLongTerminationLevel::Level2        14371                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksLongTerminationLevel::Level3       105891                       # Level at which table walker walks with long descriptors terminate
system.cpu0.dtb.walker.walksSquashedBefore       311173                       # Table walks squashed before starting
system.cpu0.dtb.walker.walkWaitTime::samples       331076                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::mean  2394.451727                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::stdev 14284.464178                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::0-65535       328283     99.16%     99.16% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::65536-131071         2041      0.62%     99.77% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::131072-196607          492      0.15%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::196608-262143          140      0.04%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::262144-327679           44      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::327680-393215           49      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::393216-458751            5      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::458752-524287            3      0.00%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::524288-589823            3      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::589824-655359           15      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::655360-720895            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkWaitTime::total       331076                       # Table walker wait (enqueue to first request) latency
system.cpu0.dtb.walker.walkCompletionTime::samples       352054                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::mean 21918.096372                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::gmean 18874.221671                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::stdev 17893.290078                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::0-65535       347548     98.72%     98.72% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::65536-131071         2975      0.85%     99.57% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::131072-196607          632      0.18%     99.74% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::196608-262143          594      0.17%     99.91% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::262144-327679          153      0.04%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::327680-393215          118      0.03%     99.99% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::393216-458751           25      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::458752-524287            5      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::524288-589823            4      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walkCompletionTime::total       352054                       # Table walker service (enqueue to completion) latency
system.cpu0.dtb.walker.walksPending::samples 539733877528                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::mean     0.599244                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::stdev     0.552867                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::0-1 538149503028     99.71%     99.71% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::2-3    904434000      0.17%     99.87% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::4-5    320975500      0.06%     99.93% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::6-7    139201000      0.03%     99.96% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::8-9    110066000      0.02%     99.98% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::10-11     60836000      0.01%     99.99% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::12-13     22060500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::14-15     25840500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::16-17       959500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::18-19         1500      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.dtb.walker.walksPending::total 539733877528                       # Table walker pending requests distribution
system.cpu0.dtb.walker.walkPageSizes::4K       105891     88.05%     88.05% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::2M        14371     11.95%    100.00% # Table walker page sizes translated
system.cpu0.dtb.walker.walkPageSizes::total       120262                       # Table walker page sizes translated
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data       642249                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::total       642249                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data       120262                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::total       120262                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin::total       762511                       # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
system.cpu0.dtb.read_hits                   102850435                       # DTB read hits
system.cpu0.dtb.read_misses                    467880                       # DTB read misses
system.cpu0.dtb.write_hits                   83320332                       # DTB write hits
system.cpu0.dtb.write_misses                   174369                       # DTB write misses
system.cpu0.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid              45792                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid                   1079                       # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries                   42516                       # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults                      599                       # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults                  7036                       # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults                    38961                       # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses               103318315                       # DTB read accesses
system.cpu0.dtb.write_accesses               83494701                       # DTB write accesses
system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu0.dtb.hits                        186170767                       # DTB hits
system.cpu0.dtb.misses                         642249                       # DTB misses
system.cpu0.dtb.accesses                    186813016                       # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.itb.walker.walks                    84160                       # Table walker walks requested
system.cpu0.itb.walker.walksLong                84160                       # Table walker walks initiated with long descriptors
system.cpu0.itb.walker.walksLongTerminationLevel::Level2         1044                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksLongTerminationLevel::Level3        58792                       # Level at which table walker walks with long descriptors terminate
system.cpu0.itb.walker.walksSquashedBefore        10193                       # Table walks squashed before starting
system.cpu0.itb.walker.walkWaitTime::samples        73967                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::mean  1726.006192                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::stdev 15527.215020                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::0-65535        73402     99.24%     99.24% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::65536-131071          457      0.62%     99.85% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::131072-196607           56      0.08%     99.93% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::196608-262143           12      0.02%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::262144-327679            7      0.01%     99.96% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::327680-393215            9      0.01%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::393216-458751            1      0.00%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::524288-589823            1      0.00%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::589824-655359           22      0.03%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkWaitTime::total        73967                       # Table walker wait (enqueue to first request) latency
system.cpu0.itb.walker.walkCompletionTime::samples        70029                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::mean 27234.188693                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::gmean 23423.171681                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::stdev 26401.977199                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::0-65535        67612     96.55%     96.55% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::65536-131071         1634      2.33%     98.88% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::131072-196607          479      0.68%     99.57% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::196608-262143          184      0.26%     99.83% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::262144-327679           51      0.07%     99.90% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::327680-393215           27      0.04%     99.94% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::393216-458751           16      0.02%     99.96% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::524288-589823            4      0.01%     99.97% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::589824-655359           21      0.03%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::720896-786431            1      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walkCompletionTime::total        70029                       # Table walker service (enqueue to completion) latency
system.cpu0.itb.walker.walksPending::samples 423766533036                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::mean     0.875739                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::stdev     0.330248                       # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::0    52705402108     12.44%     12.44% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::1   371016436928     87.55%     99.99% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::2       42131000      0.01%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::3        1939000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::4         624000      0.00%    100.00% # Table walker pending requests distribution
system.cpu0.itb.walker.walksPending::total 423766533036                       # Table walker pending requests distribution
system.cpu0.itb.walker.walkPageSizes::4K        58792     98.26%     98.26% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::2M         1044      1.74%    100.00% # Table walker page sizes translated
system.cpu0.itb.walker.walkPageSizes::total        59836                       # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst        84160                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Requested::total        84160                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst        59836                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::total        59836                       # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin::total       143996                       # Table walker requests started/completed, data/inst
system.cpu0.itb.inst_hits                   220066677                       # ITB inst hits
system.cpu0.itb.inst_misses                     84160                       # ITB inst misses
system.cpu0.itb.read_hits                           0                       # DTB read hits
system.cpu0.itb.read_misses                         0                       # DTB read misses
system.cpu0.itb.write_hits                          0                       # DTB write hits
system.cpu0.itb.write_misses                        0                       # DTB write misses
system.cpu0.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid              45792                       # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid                   1079                       # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries                   30584                       # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults                   203568                       # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses                       0                       # DTB read accesses
system.cpu0.itb.write_accesses                      0                       # DTB write accesses
system.cpu0.itb.inst_accesses               220150837                       # ITB inst accesses
system.cpu0.itb.hits                        220066677                       # DTB hits
system.cpu0.itb.misses                          84160                       # DTB misses
system.cpu0.itb.accesses                    220150837                       # DTB accesses
system.cpu0.numPwrStateTransitions              10070                       # Number of power state transitions
system.cpu0.pwrStateClkGateDist::samples         5035                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::mean    9333517887.918768                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::stdev   154504325024.809692                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::underflows         3827     76.01%     76.01% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1000-5e+10         1181     23.46%     99.46% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::5e+10-1e+11            7      0.14%     99.60% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11            1      0.02%     99.62% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11            3      0.06%     99.68% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11            1      0.02%     99.70% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11            1      0.02%     99.72% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11            1      0.02%     99.74% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::overflows           13      0.26%    100.00% # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::max_value 6914082505000                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateClkGateDist::total           5035                       # Distribution of time spent in the clock gated state
system.cpu0.pwrStateResidencyTicks::ON   390680153329                       # Cumulative time (in ticks) in various power states
system.cpu0.pwrStateResidencyTicks::CLK_GATED 46994262565671                       # Cumulative time (in ticks) in various power states
system.cpu0.numCycles                       781361530                       # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu0.fetch.icacheStallCycles          89977379                       # Number of cycles fetch is stalled on an Icache miss
system.cpu0.fetch.Insts                     618690334                       # Number of instructions fetch has processed
system.cpu0.fetch.Branches                  139745078                       # Number of branches that fetch encountered
system.cpu0.fetch.predictedBranches          83539542                       # Number of branches that fetch has predicted taken
system.cpu0.fetch.Cycles                    647313928                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu0.fetch.SquashCycles               14578052                       # Number of cycles fetch has spent squashing
system.cpu0.fetch.TlbCycles                   1993554                       # Number of cycles fetch has spent waiting for tlb
system.cpu0.fetch.MiscStallCycles              302966                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu0.fetch.PendingTrapStallCycles      5990682                       # Number of stall cycles due to pending traps
system.cpu0.fetch.PendingQuiesceStallCycles       771527                       # Number of stall cycles due to pending quiesce instructions
system.cpu0.fetch.IcacheWaitRetryStallCycles       852599                       # Number of stall cycles due to full MSHR
system.cpu0.fetch.CacheLines                219863904                       # Number of cache lines fetched
system.cpu0.fetch.IcacheSquashes              1701332                       # Number of outstanding Icache misses that were squashed
system.cpu0.fetch.ItlbSquashes                  27447                       # Number of outstanding ITLB misses that were squashed
system.cpu0.fetch.rateDist::samples         754491661                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::mean             0.959990                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::stdev            1.215112                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::0               407421945     54.00%     54.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::1               135112889     17.91%     71.91% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::2                46679176      6.19%     78.09% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::3               165277651     21.91%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::total           754491661                       # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate                 0.178848                       # Number of branch fetches per cycle
system.cpu0.fetch.rate                       0.791811                       # Number of inst fetches per cycle
system.cpu0.decode.IdleCycles               107863691                       # Number of cycles decode is idle
system.cpu0.decode.BlockedCycles            373653702                       # Number of cycles decode is blocked
system.cpu0.decode.RunCycles                228590583                       # Number of cycles decode is running
system.cpu0.decode.UnblockCycles             39162463                       # Number of cycles decode is unblocking
system.cpu0.decode.SquashCycles               5221222                       # Number of cycles decode is squashing
system.cpu0.decode.BranchResolved            20030707                       # Number of times decode resolved a branch
system.cpu0.decode.BranchMispred              2107727                       # Number of times decode detected a branch misprediction
system.cpu0.decode.DecodedInsts             640747867                       # Number of instructions handled by decode
system.cpu0.decode.SquashedInsts             23352656                       # Number of squashed instructions handled by decode
system.cpu0.rename.SquashCycles               5221222                       # Number of cycles rename is squashing
system.cpu0.rename.IdleCycles               144093047                       # Number of cycles rename is idle
system.cpu0.rename.BlockCycles               59069591                       # Number of cycles rename is blocking
system.cpu0.rename.serializeStallCycles     244366962                       # count of cycles rename stalled for serializing inst
system.cpu0.rename.RunCycles                230957488                       # Number of cycles rename is running
system.cpu0.rename.UnblockCycles             70783351                       # Number of cycles rename is unblocking
system.cpu0.rename.RenamedInsts             623359263                       # Number of instructions processed by rename
system.cpu0.rename.SquashedInsts              6158447                       # Number of squashed instructions processed by rename
system.cpu0.rename.ROBFullEvents             11021555                       # Number of times rename has blocked due to ROB full
system.cpu0.rename.IQFullEvents                440656                       # Number of times rename has blocked due to IQ full
system.cpu0.rename.LQFullEvents                940490                       # Number of times rename has blocked due to LQ full
system.cpu0.rename.SQFullEvents              33921586                       # Number of times rename has blocked due to SQ full
system.cpu0.rename.FullRegisterEvents           11494                       # Number of times there has been no free registers
system.cpu0.rename.RenamedOperands          594689945                       # Number of destination operands rename has renamed
system.cpu0.rename.RenameLookups            962815337                       # Number of register rename lookups that rename has made
system.cpu0.rename.int_rename_lookups       736259751                       # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups           682623                       # Number of floating rename lookups
system.cpu0.rename.CommittedMaps            536299590                       # Number of HB maps that are committed
system.cpu0.rename.UndoneMaps                58390349                       # Number of HB maps that are undone due to squashing
system.cpu0.rename.serializingInsts          16178274                       # count of serializing insts renamed
system.cpu0.rename.tempSerializingInsts      14135285                       # count of temporary serializing insts renamed
system.cpu0.rename.skidInsts                 78489785                       # count of insts added to the skid buffer
system.cpu0.memDep0.insertedLoads           102915286                       # Number of loads inserted to the mem dependence unit.
system.cpu0.memDep0.insertedStores           86617273                       # Number of stores inserted to the mem dependence unit.
system.cpu0.memDep0.conflictingLoads          9593817                       # Number of conflicting loads.
system.cpu0.memDep0.conflictingStores         8133429                       # Number of conflicting stores.
system.cpu0.iq.iqInstsAdded                 600294247                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu0.iq.iqNonSpecInstsAdded           16347683                       # Number of non-speculative instructions added to the IQ
system.cpu0.iq.iqInstsIssued                605471525                       # Number of instructions issued
system.cpu0.iq.iqSquashedInstsIssued          2720884                       # Number of squashed instructions issued
system.cpu0.iq.iqSquashedInstsExamined       54918264                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu0.iq.iqSquashedOperandsExamined     35662191                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu0.iq.iqSquashedNonSpecRemoved        285806                       # Number of squashed non-spec instructions that were removed
system.cpu0.iq.issued_per_cycle::samples    754491661                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::mean        0.802489                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::stdev       1.061507                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::0          423297632     56.10%     56.10% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::1          139867580     18.54%     74.64% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::2          116427415     15.43%     90.07% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::3           66852551      8.86%     98.93% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::4            8040953      1.07%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::5               5530      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::total      754491661                       # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntAlu               62202700     45.10%     45.10% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntMult                 65869      0.05%     45.14% # attempts to use FU when none available
system.cpu0.iq.fu_full::IntDiv                  12866      0.01%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatAdd                    0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCmp                    0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatCvt                    0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatMult                   0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatDiv                    0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::FloatSqrt                   0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAdd                     0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAddAcc                  0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdAlu                     0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCmp                     0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdCvt                     0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMisc                    0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMult                    0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdMultAcc                 0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShift                   0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdShiftAcc                0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdSqrt                    0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAdd                0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatAlu                0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCmp                0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatCvt                0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatDiv                0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMisc              27      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMult               0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatMultAcc            0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::SimdFloatSqrt               0      0.00%     45.15% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemRead              36951420     26.79%     71.94% # attempts to use FU when none available
system.cpu0.iq.fu_full::MemWrite             38701650     28.06%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass               51      0.00%      0.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IntAlu            413123878     68.23%     68.23% # Type of FU issued
system.cpu0.iq.FU_type_0::IntMult             1535668      0.25%     68.49% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv                80204      0.01%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd                  6      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCvt                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatMult                 0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatDiv                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatSqrt                 0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAdd                   0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAddAcc                1      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdAlu                   1      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCmp                   0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdCvt                   0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMisc                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMult                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdMultAcc               0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShift                 0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdSqrt                  0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAdd              0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp              0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt              0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.50% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMisc         45354      0.01%     68.51% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult             0      0.00%     68.51% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.51% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.51% # Type of FU issued
system.cpu0.iq.FU_type_0::MemRead           106103331     17.52%     86.03% # Type of FU issued
system.cpu0.iq.FU_type_0::MemWrite           84583031     13.97%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::total             605471525                       # Type of FU issued
system.cpu0.iq.rate                          0.774893                       # Inst issue rate
system.cpu0.iq.fu_busy_cnt                  137934532                       # FU busy when requested
system.cpu0.iq.fu_busy_rate                  0.227813                       # FU busy rate (busy events/executed inst)
system.cpu0.iq.int_inst_queue_reads        2104985611                       # Number of integer instruction queue reads
system.cpu0.iq.int_inst_queue_writes        671273361                       # Number of integer instruction queue writes
system.cpu0.iq.int_inst_queue_wakeup_accesses    587796479                       # Number of integer instruction queue wakeup accesses
system.cpu0.iq.fp_inst_queue_reads            1104514                       # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes            436534                       # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses       408765                       # Number of floating instruction queue wakeup accesses
system.cpu0.iq.int_alu_accesses             742719141                       # Number of integer alu accesses
system.cpu0.iq.fp_alu_accesses                 686865                       # Number of floating point alu accesses
system.cpu0.iew.lsq.thread0.forwLoads         2818576                       # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu0.iew.lsq.thread0.squashedLoads     12827708                       # Number of loads squashed
system.cpu0.iew.lsq.thread0.ignoredResponses        17934                       # Number of memory responses ignored because the instruction is squashed
system.cpu0.iew.lsq.thread0.memOrderViolation       150945                       # Number of memory ordering violations
system.cpu0.iew.lsq.thread0.squashedStores      5597965                       # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu0.iew.lsq.thread0.rescheduledLoads      2832815                       # Number of loads that were rescheduled
system.cpu0.iew.lsq.thread0.cacheBlocked      4794177                       # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu0.iew.iewSquashCycles               5221222                       # Number of cycles IEW is squashing
system.cpu0.iew.iewBlockCycles                8523162                       # Number of cycles IEW is blocking
system.cpu0.iew.iewUnblockCycles              2018525                       # Number of cycles IEW is unblocking
system.cpu0.iew.iewDispatchedInsts          616773219                       # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu0.iew.iewDispLoadInsts            102915286                       # Number of dispatched load instructions
system.cpu0.iew.iewDispStoreInsts            86617273                       # Number of dispatched store instructions
system.cpu0.iew.iewDispNonSpecInsts          13889545                       # Number of dispatched non-speculative instructions
system.cpu0.iew.iewIQFullEvents                 69101                       # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents              1866975                       # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents        150945                       # Number of memory order violations
system.cpu0.iew.predictedTakenIncorrect       1955799                       # Number of branches that were predicted taken incorrectly
system.cpu0.iew.predictedNotTakenIncorrect      3092868                       # Number of branches that were predicted not taken incorrectly
system.cpu0.iew.branchMispredicts             5048667                       # Number of branch mispredicts detected at execute
system.cpu0.iew.iewExecutedInsts            597424685                       # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts            102845914                       # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts          7413191                       # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp                            0                       # number of swp insts executed
system.cpu0.iew.exec_nop                       131289                       # number of nop insts executed
system.cpu0.iew.exec_refs                   186166471                       # number of memory reference insts executed
system.cpu0.iew.exec_branches               112308682                       # Number of branches executed
system.cpu0.iew.exec_stores                  83320557                       # Number of stores executed
system.cpu0.iew.exec_rate                    0.764594                       # Inst execution rate
system.cpu0.iew.wb_sent                     588977240                       # cumulative count of insts sent to commit
system.cpu0.iew.wb_count                    588205244                       # cumulative count of insts written-back
system.cpu0.iew.wb_producers                286222957                       # num instructions producing a value
system.cpu0.iew.wb_consumers                469478170                       # num instructions consuming a value
system.cpu0.iew.wb_rate                      0.752795                       # insts written-back per cycle
system.cpu0.iew.wb_fanout                    0.609662                       # average fanout of values written-back
system.cpu0.commit.commitSquashedInsts       48006701                       # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls       16061877                       # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts          4699541                       # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::samples    745382545                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::mean     0.753605                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::stdev     1.560188                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::0    499589625     67.02%     67.02% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::1    127846284     17.15%     84.18% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::2     54154407      7.27%     91.44% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::3     18022208      2.42%     93.86% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::4     12958039      1.74%     95.60% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::5      8991225      1.21%     96.80% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::6      6101110      0.82%     97.62% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::7      3650180      0.49%     98.11% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::8     14069467      1.89%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total    745382545                       # Number of insts commited each cycle
system.cpu0.commit.committedInsts           478330111                       # Number of instructions committed
system.cpu0.commit.committedOps             561723659                       # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu0.commit.refs                     171106885                       # Number of memory references committed
system.cpu0.commit.loads                     90087577                       # Number of loads committed
system.cpu0.commit.membars                    3940521                       # Number of memory barriers committed
system.cpu0.commit.branches                 106744395                       # Number of branches committed
system.cpu0.commit.fp_insts                    400838                       # Number of committed floating point instructions.
system.cpu0.commit.int_insts                515553500                       # Number of committed integer instructions.
system.cpu0.commit.function_calls            14275050                       # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IntAlu       389225467     69.29%     69.29% # Class of committed instruction
system.cpu0.commit.op_class_0::IntMult        1288146      0.23%     69.52% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv           63590      0.01%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd             0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp             0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCvt             0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatMult            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatDiv             0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatSqrt            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAdd              0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAddAcc            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdAlu              0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCmp              0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdCvt              0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMisc             0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMult             0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdMultAcc            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShift            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdShiftAcc            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdSqrt             0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAdd            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatAlu            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv            0      0.00%     69.53% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMisc        39571      0.01%     69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult            0      0.00%     69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.54% # Class of committed instruction
system.cpu0.commit.op_class_0::MemRead       90087577     16.04%     85.58% # Class of committed instruction
system.cpu0.commit.op_class_0::MemWrite      81019308     14.42%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::total        561723659                       # Class of committed instruction
system.cpu0.commit.bw_lim_events             14069467                       # number cycles where commit BW limit reached
system.cpu0.rob.rob_reads                  1336864700                       # The number of ROB reads
system.cpu0.rob.rob_writes                 1228532736                       # The number of ROB writes
system.cpu0.timesIdled                        1001309                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles                       26869869                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles                 93988523944                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts                  478330111                       # Number of Instructions Simulated
system.cpu0.committedOps                    561723659                       # Number of Ops (including micro ops) Simulated
system.cpu0.cpi                              1.633519                       # CPI: Cycles Per Instruction
system.cpu0.cpi_total                        1.633519                       # CPI: Total CPI of All Threads
system.cpu0.ipc                              0.612175                       # IPC: Instructions Per Cycle
system.cpu0.ipc_total                        0.612175                       # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads               705719528                       # number of integer regfile reads
system.cpu0.int_regfile_writes              419138035                       # number of integer regfile writes
system.cpu0.fp_regfile_reads                   669802                       # number of floating regfile reads
system.cpu0.fp_regfile_writes                  321532                       # number of floating regfile writes
system.cpu0.cc_regfile_reads                129631161                       # number of cc regfile reads
system.cpu0.cc_regfile_writes               130314957                       # number of cc regfile writes
system.cpu0.misc_regfile_reads             1341639409                       # number of misc regfile reads
system.cpu0.misc_regfile_writes              16172326                       # number of misc regfile writes
system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.tags.replacements          6359267                       # number of replacements
system.cpu0.dcache.tags.tagsinuse          478.495579                       # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs          158196405                       # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs          6359779                       # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs            24.874513                       # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle       2049282000                       # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data   478.495579                       # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data     0.934562                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total     0.934562                       # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0           93                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1          386                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2           32                       # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses        355337560                       # Number of tag accesses
system.cpu0.dcache.tags.data_accesses       355337560                       # Number of data accesses
system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.dcache.ReadReq_hits::cpu0.data     83119639                       # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total       83119639                       # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data     70042361                       # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total      70042361                       # number of WriteReq hits
system.cpu0.dcache.SoftPFReq_hits::cpu0.data       205739                       # number of SoftPFReq hits
system.cpu0.dcache.SoftPFReq_hits::total       205739                       # number of SoftPFReq hits
system.cpu0.dcache.WriteLineReq_hits::cpu0.data       143941                       # number of WriteLineReq hits
system.cpu0.dcache.WriteLineReq_hits::total       143941                       # number of WriteLineReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data      1893040                       # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total      1893040                       # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data      1948071                       # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total      1948071                       # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data    153305941                       # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total       153305941                       # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data    153511680                       # number of overall hits
system.cpu0.dcache.overall_hits::total      153511680                       # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data      7167523                       # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total      7167523                       # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data      7883078                       # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total      7883078                       # number of WriteReq misses
system.cpu0.dcache.SoftPFReq_misses::cpu0.data       755741                       # number of SoftPFReq misses
system.cpu0.dcache.SoftPFReq_misses::total       755741                       # number of SoftPFReq misses
system.cpu0.dcache.WriteLineReq_misses::cpu0.data       796292                       # number of WriteLineReq misses
system.cpu0.dcache.WriteLineReq_misses::total       796292                       # number of WriteLineReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data       289192                       # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total       289192                       # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu0.data       197314                       # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total       197314                       # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data     15846893                       # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total      15846893                       # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data     16602634                       # number of overall misses
system.cpu0.dcache.overall_misses::total     16602634                       # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 116616484000                       # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 116616484000                       # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 160918615442                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 160918615442                       # number of WriteReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data  30600076090                       # number of WriteLineReq miss cycles
system.cpu0.dcache.WriteLineReq_miss_latency::total  30600076090                       # number of WriteLineReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data   4458676000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total   4458676000                       # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data   4713253000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total   4713253000                       # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data      2519000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.StoreCondFailReq_miss_latency::total      2519000                       # number of StoreCondFailReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu0.data 308135175532                       # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 308135175532                       # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu0.data 308135175532                       # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 308135175532                       # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data     90287162                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total     90287162                       # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data     77925439                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total     77925439                       # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data       961480                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.SoftPFReq_accesses::total       961480                       # number of SoftPFReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::cpu0.data       940233                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.WriteLineReq_accesses::total       940233                       # number of WriteLineReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data      2182232                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total      2182232                       # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data      2145385                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total      2145385                       # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data    169152834                       # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total    169152834                       # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data    170114314                       # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total    170114314                       # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.079386                       # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total     0.079386                       # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.101162                       # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total     0.101162                       # miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data     0.786018                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_miss_rate::total     0.786018                       # miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data     0.846909                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_miss_rate::total     0.846909                       # miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.132521                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total     0.132521                       # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.091971                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total     0.091971                       # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data     0.093684                       # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total     0.093684                       # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data     0.097597                       # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total     0.097597                       # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16270.123444                       # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 16270.123444                       # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20413.170521                       # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 20413.170521                       # average WriteReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 38428.209865                       # average WriteLineReq miss latency
system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 38428.209865                       # average WriteLineReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.701734                       # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.701734                       # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23887.068328                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23887.068328                       # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19444.516697                       # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 19444.516697                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18559.415062                       # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 18559.415062                       # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs      9297521                       # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets     24817691                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs           744023                       # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets         779199                       # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs    12.496282                       # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets    31.850260                       # average number of cycles each access was blocked
system.cpu0.dcache.writebacks::writebacks      6359403                       # number of writebacks
system.cpu0.dcache.writebacks::total          6359403                       # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data      3686639                       # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total      3686639                       # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      6327255                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total      6327255                       # number of WriteReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data         4271                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.WriteLineReq_mshr_hits::total         4271                       # number of WriteLineReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data       148971                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total       148971                       # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu0.data     10018165                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total     10018165                       # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu0.data     10018165                       # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total     10018165                       # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      3480884                       # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total      3480884                       # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data      1555823                       # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total      1555823                       # number of WriteReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data       748893                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.SoftPFReq_mshr_misses::total       748893                       # number of SoftPFReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data       792021                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.WriteLineReq_mshr_misses::total       792021                       # number of WriteLineReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data       140221                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total       140221                       # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data       197311                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total       197311                       # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu0.data      5828728                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total      5828728                       # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu0.data      6577621                       # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total      6577621                       # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data        16980                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.ReadReq_mshr_uncacheable::total        16980                       # number of ReadReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data        18801                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.WriteReq_mshr_uncacheable::total        18801                       # number of WriteReq MSHR uncacheable
system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data        35781                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.overall_mshr_uncacheable_misses::total        35781                       # number of overall MSHR uncacheable misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  53164892500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total  53164892500                       # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data  34944889021                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total  34944889021                       # number of WriteReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data  18458336500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total  18458336500                       # number of SoftPFReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data  29638184090                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total  29638184090                       # number of WriteLineReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data   1982757000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total   1982757000                       # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data   4516003000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total   4516003000                       # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data      2458000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total      2458000                       # number of StoreCondFailReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 117747965611                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 117747965611                       # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136206302111                       # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 136206302111                       # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   3133590500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   3133590500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   3133590500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total   3133590500                       # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.038553                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total     0.038553                       # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.019966                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total     0.019966                       # mshr miss rate for WriteReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data     0.778896                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total     0.778896                       # mshr miss rate for SoftPFReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data     0.842367                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total     0.842367                       # mshr miss rate for WriteLineReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.064256                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total     0.064256                       # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.091970                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total     0.091970                       # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.034458                       # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total     0.034458                       # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.038666                       # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total     0.038666                       # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15273.388168                       # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15273.388168                       # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22460.709876                       # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22460.709876                       # average WriteReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24647.495036                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24647.495036                       # average SoftPFReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 37420.957386                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 37420.957386                       # average WriteLineReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14140.228639                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14140.228639                       # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22887.740673                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22887.740673                       # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20201.314182                       # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20201.314182                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20707.532725                       # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20707.532725                       # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184545.965842                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184545.965842                       # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87576.940276                       # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87576.940276                       # average overall mshr uncacheable latency
system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.tags.replacements          6086800                       # number of replacements
system.cpu0.icache.tags.tagsinuse          511.960315                       # Cycle average of tags in use
system.cpu0.icache.tags.total_refs          213393241                       # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs          6087312                       # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs            35.055414                       # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle      13476237000                       # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.960315                       # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst     0.999922                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total     0.999922                       # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0          113                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1          315                       # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2           84                       # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses        445759262                       # Number of tag accesses
system.cpu0.icache.tags.data_accesses       445759262                       # Number of data accesses
system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.icache.ReadReq_hits::cpu0.inst    213393241                       # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total      213393241                       # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst    213393241                       # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total       213393241                       # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst    213393241                       # number of overall hits
system.cpu0.icache.overall_hits::total      213393241                       # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst      6442715                       # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total      6442715                       # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst      6442715                       # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total       6442715                       # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst      6442715                       # number of overall misses
system.cpu0.icache.overall_misses::total      6442715                       # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  71477790896                       # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total  71477790896                       # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu0.inst  71477790896                       # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total  71477790896                       # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu0.inst  71477790896                       # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total  71477790896                       # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst    219835956                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total    219835956                       # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst    219835956                       # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total    219835956                       # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst    219835956                       # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total    219835956                       # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.029307                       # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total     0.029307                       # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst     0.029307                       # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total     0.029307                       # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst     0.029307                       # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total     0.029307                       # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11094.358651                       # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 11094.358651                       # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11094.358651                       # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 11094.358651                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11094.358651                       # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 11094.358651                       # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs     10557387                       # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets         2753                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs           752829                       # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets             14                       # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs    14.023619                       # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets   196.642857                       # average number of cycles each access was blocked
system.cpu0.icache.writebacks::writebacks      6086800                       # number of writebacks
system.cpu0.icache.writebacks::total          6086800                       # number of writebacks
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst       355365                       # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total       355365                       # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu0.inst       355365                       # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total       355365                       # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu0.inst       355365                       # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total       355365                       # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst      6087350                       # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total      6087350                       # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu0.inst      6087350                       # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total      6087350                       # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu0.inst      6087350                       # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total      6087350                       # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.ReadReq_mshr_uncacheable::total        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.cpu0.icache.overall_mshr_uncacheable_misses::total        21293                       # number of overall MSHR uncacheable misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  64448796094                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total  64448796094                       # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  64448796094                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total  64448796094                       # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  64448796094                       # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total  64448796094                       # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst   2027158498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total   2027158498                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst   2027158498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total   2027158498                       # number of overall MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.027690                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total     0.027690                       # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.027690                       # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total     0.027690                       # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.027690                       # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total     0.027690                       # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10587.332106                       # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10587.332106                       # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10587.332106                       # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 10587.332106                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10587.332106                       # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 10587.332106                       # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856                       # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856                       # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856                       # average overall mshr uncacheable latency
system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.prefetcher.num_hwpf_issued      8595677                       # number of hwpf issued
system.cpu0.l2cache.prefetcher.pfIdentified      8603285                       # number of prefetch candidates identified
system.cpu0.l2cache.prefetcher.pfBufferHit         6909                       # number of redundant prefetches already in prefetch queue
system.cpu0.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu0.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu0.l2cache.prefetcher.pfSpanPage      1123339                       # number of prefetches not generated due to page crossing
system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.tags.replacements         2781248                       # number of replacements
system.cpu0.l2cache.tags.tagsinuse       15839.093178                       # Cycle average of tags in use
system.cpu0.l2cache.tags.total_refs          10966307                       # Total number of references to valid blocks.
system.cpu0.l2cache.tags.sampled_refs         2797118                       # Sample count of references to valid blocks.
system.cpu0.l2cache.tags.avg_refs            3.920574                       # Average number of references to valid blocks.
system.cpu0.l2cache.tags.warmup_cycle      2357977000                       # Cycle when the warmup percentage was hit.
system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.164563                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker    33.011471                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker    18.049668                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.data     0.000001                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher   268.867475                       # Average occupied blocks per requestor
system.cpu0.l2cache.tags.occ_percent::writebacks     0.947215                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker     0.002015                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker     0.001102                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.data     0.000000                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher     0.016410                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::total     0.966742                       # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_task_id_blocks::1022          337                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1023           83                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_blocks::1024        15450                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::1            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::2          131                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::3          116                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1022::4           88                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::0            1                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::1            2                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::2           44                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::4           20                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::0          205                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::1         1708                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::2         7197                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::3         4776                       # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1024::4         1564                       # Occupied blocks per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1022     0.020569                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1023     0.005066                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.occ_task_id_percent::1024     0.942993                       # Percentage of cache occupancy per task id
system.cpu0.l2cache.tags.tag_accesses       434183760                       # Number of tag accesses
system.cpu0.l2cache.tags.data_accesses      434183760                       # Number of data accesses
system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker       639992                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker       185315                       # number of ReadReq hits
system.cpu0.l2cache.ReadReq_hits::total        825307                       # number of ReadReq hits
system.cpu0.l2cache.WritebackDirty_hits::writebacks      4159646                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackDirty_hits::total      4159646                       # number of WritebackDirty hits
system.cpu0.l2cache.WritebackClean_hits::writebacks      8284827                       # number of WritebackClean hits
system.cpu0.l2cache.WritebackClean_hits::total      8284827                       # number of WritebackClean hits
system.cpu0.l2cache.UpgradeReq_hits::cpu0.data           23                       # number of UpgradeReq hits
system.cpu0.l2cache.UpgradeReq_hits::total           23                       # number of UpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data            2                       # number of SCUpgradeReq hits
system.cpu0.l2cache.SCUpgradeReq_hits::total            2                       # number of SCUpgradeReq hits
system.cpu0.l2cache.ReadExReq_hits::cpu0.data       995756                       # number of ReadExReq hits
system.cpu0.l2cache.ReadExReq_hits::total       995756                       # number of ReadExReq hits
system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst      5493946                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadCleanReq_hits::total      5493946                       # number of ReadCleanReq hits
system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data      3273779                       # number of ReadSharedReq hits
system.cpu0.l2cache.ReadSharedReq_hits::total      3273779                       # number of ReadSharedReq hits
system.cpu0.l2cache.InvalidateReq_hits::cpu0.data       166627                       # number of InvalidateReq hits
system.cpu0.l2cache.InvalidateReq_hits::total       166627                       # number of InvalidateReq hits
system.cpu0.l2cache.demand_hits::cpu0.dtb.walker       639992                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.itb.walker       185315                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.inst      5493946                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::cpu0.data      4269535                       # number of demand (read+write) hits
system.cpu0.l2cache.demand_hits::total       10588788                       # number of demand (read+write) hits
system.cpu0.l2cache.overall_hits::cpu0.dtb.walker       639992                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.itb.walker       185315                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.inst      5493946                       # number of overall hits
system.cpu0.l2cache.overall_hits::cpu0.data      4269535                       # number of overall hits
system.cpu0.l2cache.overall_hits::total      10588788                       # number of overall hits
system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker        23429                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker        11592                       # number of ReadReq misses
system.cpu0.l2cache.ReadReq_misses::total        35021                       # number of ReadReq misses
system.cpu0.l2cache.UpgradeReq_misses::cpu0.data       269158                       # number of UpgradeReq misses
system.cpu0.l2cache.UpgradeReq_misses::total       269158                       # number of UpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data       197304                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeReq_misses::total       197304                       # number of SCUpgradeReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.SCUpgradeFailReq_misses::total            5                       # number of SCUpgradeFailReq misses
system.cpu0.l2cache.ReadExReq_misses::cpu0.data       301043                       # number of ReadExReq misses
system.cpu0.l2cache.ReadExReq_misses::total       301043                       # number of ReadExReq misses
system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst       593373                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadCleanReq_misses::total       593373                       # number of ReadCleanReq misses
system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data      1093007                       # number of ReadSharedReq misses
system.cpu0.l2cache.ReadSharedReq_misses::total      1093007                       # number of ReadSharedReq misses
system.cpu0.l2cache.InvalidateReq_misses::cpu0.data       623543                       # number of InvalidateReq misses
system.cpu0.l2cache.InvalidateReq_misses::total       623543                       # number of InvalidateReq misses
system.cpu0.l2cache.demand_misses::cpu0.dtb.walker        23429                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.itb.walker        11592                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.inst       593373                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::cpu0.data      1394050                       # number of demand (read+write) misses
system.cpu0.l2cache.demand_misses::total      2022444                       # number of demand (read+write) misses
system.cpu0.l2cache.overall_misses::cpu0.dtb.walker        23429                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.itb.walker        11592                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.inst       593373                       # number of overall misses
system.cpu0.l2cache.overall_misses::cpu0.data      1394050                       # number of overall misses
system.cpu0.l2cache.overall_misses::total      2022444                       # number of overall misses
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker    862921500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker    562577500                       # number of ReadReq miss cycles
system.cpu0.l2cache.ReadReq_miss_latency::total   1425499000                       # number of ReadReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data    983366500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.UpgradeReq_miss_latency::total    983366500                       # number of UpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data    308777000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeReq_miss_latency::total    308777000                       # number of SCUpgradeReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data      2366500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total      2366500                       # number of SCUpgradeFailReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data  18857416997                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadExReq_miss_latency::total  18857416997                       # number of ReadExReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst  22027267000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadCleanReq_miss_latency::total  22027267000                       # number of ReadCleanReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data  45190340989                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.ReadSharedReq_miss_latency::total  45190340989                       # number of ReadSharedReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data    290057500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.InvalidateReq_miss_latency::total    290057500                       # number of InvalidateReq miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker    862921500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker    562577500                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.inst  22027267000                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::cpu0.data  64047757986                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.demand_miss_latency::total  87500523986                       # number of demand (read+write) miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker    862921500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker    562577500                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.inst  22027267000                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::cpu0.data  64047757986                       # number of overall miss cycles
system.cpu0.l2cache.overall_miss_latency::total  87500523986                       # number of overall miss cycles
system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker       663421                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker       196907                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.ReadReq_accesses::total       860328                       # number of ReadReq accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::writebacks      4159646                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackDirty_accesses::total      4159646                       # number of WritebackDirty accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::writebacks      8284827                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.WritebackClean_accesses::total      8284827                       # number of WritebackClean accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data       269181                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.UpgradeReq_accesses::total       269181                       # number of UpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data       197306                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeReq_accesses::total       197306                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.SCUpgradeFailReq_accesses::total            5                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::cpu0.data      1296799                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadExReq_accesses::total      1296799                       # number of ReadExReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst      6087319                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadCleanReq_accesses::total      6087319                       # number of ReadCleanReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data      4366786                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.ReadSharedReq_accesses::total      4366786                       # number of ReadSharedReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data       790170                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.InvalidateReq_accesses::total       790170                       # number of InvalidateReq accesses(hits+misses)
system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker       663421                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.itb.walker       196907                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.inst      6087319                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::cpu0.data      5663585                       # number of demand (read+write) accesses
system.cpu0.l2cache.demand_accesses::total     12611232                       # number of demand (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker       663421                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.itb.walker       196907                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.inst      6087319                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::cpu0.data      5663585                       # number of overall (read+write) accesses
system.cpu0.l2cache.overall_accesses::total     12611232                       # number of overall (read+write) accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker     0.035315                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker     0.058870                       # miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_miss_rate::total     0.040707                       # miss rate for ReadReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data     0.999915                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_miss_rate::total     0.999915                       # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data     0.999990                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total     0.999990                       # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data     0.232143                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_miss_rate::total     0.232143                       # miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst     0.097477                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_miss_rate::total     0.097477                       # miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data     0.250300                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_miss_rate::total     0.250300                       # miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data     0.789125                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_miss_rate::total     0.789125                       # miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker     0.035315                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker     0.058870                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.inst     0.097477                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::cpu0.data     0.246143                       # miss rate for demand accesses
system.cpu0.l2cache.demand_miss_rate::total     0.160368                       # miss rate for demand accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker     0.035315                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker     0.058870                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.inst     0.097477                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::cpu0.data     0.246143                       # miss rate for overall accesses
system.cpu0.l2cache.overall_miss_rate::total     0.160368                       # miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36831.341500                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48531.530366                       # average ReadReq miss latency
system.cpu0.l2cache.ReadReq_avg_miss_latency::total 40704.120385                       # average ReadReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data  3653.491629                       # average UpgradeReq miss latency
system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total  3653.491629                       # average UpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data  1564.980943                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total  1564.980943                       # average SCUpgradeReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data       473300                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total       473300                       # average SCUpgradeFailReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62640.277293                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62640.277293                       # average ReadExReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37122.125543                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37122.125543                       # average ReadCleanReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41344.969418                       # average ReadSharedReq miss latency
system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41344.969418                       # average ReadSharedReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data   465.176419                       # average InvalidateReq miss latency
system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total   465.176419                       # average InvalidateReq miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36831.341500                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48531.530366                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37122.125543                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45943.659113                       # average overall miss latency
system.cpu0.l2cache.demand_avg_miss_latency::total 43264.745024                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36831.341500                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48531.530366                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37122.125543                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45943.659113                       # average overall miss latency
system.cpu0.l2cache.overall_avg_miss_latency::total 43264.745024                       # average overall miss latency
system.cpu0.l2cache.blocked_cycles::no_mshrs         1347                       # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs              28                       # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_mshrs    48.107143                       # average number of cycles each access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu0.l2cache.unused_prefetches           49330                       # number of HardPF blocks evicted w/o reference
system.cpu0.l2cache.writebacks::writebacks      1802209                       # number of writebacks
system.cpu0.l2cache.writebacks::total         1802209                       # number of writebacks
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker          136                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker          303                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadReq_mshr_hits::total          439                       # number of ReadReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data        20845                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadExReq_mshr_hits::total        20845                       # number of ReadExReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst            2                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadCleanReq_mshr_hits::total            2                       # number of ReadCleanReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data         4784                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.ReadSharedReq_mshr_hits::total         4784                       # number of ReadSharedReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data            6                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.InvalidateReq_mshr_hits::total            6                       # number of InvalidateReq MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker          136                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker          303                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.inst            2                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::cpu0.data        25629                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.demand_mshr_hits::total        26070                       # number of demand (read+write) MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker          136                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker          303                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.inst            2                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::cpu0.data        25629                       # number of overall MSHR hits
system.cpu0.l2cache.overall_mshr_hits::total        26070                       # number of overall MSHR hits
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker        23293                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker        11289                       # number of ReadReq MSHR misses
system.cpu0.l2cache.ReadReq_mshr_misses::total        34582                       # number of ReadReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher       895757                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.HardPFReq_mshr_misses::total       895757                       # number of HardPFReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data       269158                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.UpgradeReq_mshr_misses::total       269158                       # number of UpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data       197304                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total       197304                       # number of SCUpgradeReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total            5                       # number of SCUpgradeFailReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data       280198                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadExReq_mshr_misses::total       280198                       # number of ReadExReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst       593371                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadCleanReq_mshr_misses::total       593371                       # number of ReadCleanReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data      1088223                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.ReadSharedReq_mshr_misses::total      1088223                       # number of ReadSharedReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data       623537                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.InvalidateReq_mshr_misses::total       623537                       # number of InvalidateReq MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker        23293                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker        11289                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.inst       593371                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::cpu0.data      1368421                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.demand_mshr_misses::total      1996374                       # number of demand (read+write) MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker        23293                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker        11289                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.inst       593371                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.data      1368421                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher       895757                       # number of overall MSHR misses
system.cpu0.l2cache.overall_mshr_misses::total      2892131                       # number of overall MSHR misses
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data        16980                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.ReadReq_mshr_uncacheable::total        38273                       # number of ReadReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data        18801                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.WriteReq_mshr_uncacheable::total        18801                       # number of WriteReq MSHR uncacheable
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data        35781                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.overall_mshr_uncacheable_misses::total        57074                       # number of overall MSHR uncacheable misses
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker    720471000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker    489799000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_miss_latency::total   1210270000                       # number of ReadReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher  58575065392                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total  58575065392                       # number of HardPFReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data   4984780995                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total   4984780995                       # number of UpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data   3032798496                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total   3032798496                       # number of SCUpgradeReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data      2000500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2000500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data  14111841497                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total  14111841497                       # number of ReadExReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst  18467014500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total  18467014500                       # number of ReadCleanReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data  38294410989                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total  38294410989                       # number of ReadSharedReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data  22764184995                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total  22764184995                       # number of InvalidateReq MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker    720471000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker    489799000                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst  18467014500                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data  52406252486                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.demand_mshr_miss_latency::total  72083536986                       # number of demand (read+write) MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker    720471000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker    489799000                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst  18467014500                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data  52406252486                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  58575065392                       # number of overall MSHR miss cycles
system.cpu0.l2cache.overall_mshr_miss_latency::total 130658602378                       # number of overall MSHR miss cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst   1867460000                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data   2997239500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total   4864699500                       # number of ReadReq MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst   1867460000                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data   2997239500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.overall_mshr_uncacheable_latency::total   4864699500                       # number of overall MSHR uncacheable cycles
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.035110                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.057332                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.ReadReq_mshr_miss_rate::total     0.040196                       # mshr miss rate for ReadReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data     0.999915                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total     0.999915                       # mshr miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.999990                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999990                       # mshr miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data     0.216069                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total     0.216069                       # mshr miss rate for ReadExReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst     0.097477                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total     0.097477                       # mshr miss rate for ReadCleanReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data     0.249205                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total     0.249205                       # mshr miss rate for ReadSharedReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data     0.789118                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total     0.789118                       # mshr miss rate for InvalidateReq accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker     0.035110                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker     0.057332                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst     0.097477                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data     0.241617                       # mshr miss rate for demand accesses
system.cpu0.l2cache.demand_mshr_miss_rate::total     0.158301                       # mshr miss rate for demand accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker     0.035110                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker     0.057332                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst     0.097477                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data     0.241617                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::total     0.229330                       # mshr miss rate for overall accesses
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653                       # average ReadReq mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34997.108322                       # average ReadReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65391.691488                       # average HardPFReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18519.906505                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18519.906505                       # average UpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15371.196205                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15371.196205                       # average SCUpgradeReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data       400100                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       400100                       # average SCUpgradeFailReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50363.819503                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50363.819503                       # average ReadExReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31122.206006                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31122.206006                       # average ReadCleanReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35189.856297                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35189.856297                       # average ReadSharedReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36508.154280                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36508.154280                       # average InvalidateReq mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31122.206006                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38296.878290                       # average overall mshr miss latency
system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36107.230903                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31122.206006                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38296.878290                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488                       # average overall mshr miss latency
system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45177.276679                       # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176515.871614                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127105.256970                       # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83766.230681                       # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85234.949364                       # average overall mshr uncacheable latency
system.cpu0.toL2Bus.snoop_filter.tot_requests     25828303                       # Total number of requests made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_requests     13287358                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_requests         1712                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.snoop_filter.tot_snoops       676521                       # Total number of snoops made to the snoop filter.
system.cpu0.toL2Bus.snoop_filter.hit_single_snoops       676518                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops            3                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu0.toL2Bus.trans_dist::ReadReq        990165                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp     11537181                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate            1                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq        18801                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp        18801                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackDirty      5966642                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WritebackClean      8286555                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::CleanEvict      1378403                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFReq      1136481                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::HardPFResp           14                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeReq       480580                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeReq       352407                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeResp       530357                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq           77                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq      1327096                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp      1303956                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadCleanReq      6087350                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadSharedReq      5339261                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateReq       842479                       # Transaction distribution
system.cpu0.toL2Bus.trans_dist::InvalidateResp       790170                       # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side     18304055                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side     20435509                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side       413815                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      1398403                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count::total         40551782                       # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side    779484304                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side    775974521                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side      1575256                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side      5307368                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size::total        1562341449                       # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.snoops                    5999180                       # Total snoops (count)
system.cpu0.toL2Bus.snoopTraffic            122789024                       # Total snoop traffic (bytes)
system.cpu0.toL2Bus.snoop_fanout::samples     19760108                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::mean       0.053277                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::stdev      0.224586                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0          18707349     94.67%     94.67% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1           1052756      5.33%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2                 3      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::total      19760108                       # Request fanout histogram
system.cpu0.toL2Bus.reqLayer0.occupancy   25687014453                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu0.toL2Bus.snoopLayer0.occupancy    182391125                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer0.occupancy   9158694684                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer1.occupancy   9158841551                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer2.occupancy    217386526                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu0.toL2Bus.respLayer3.occupancy    735766915                       # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.cpu1.branchPred.lookups              134369829                       # Number of BP lookups
system.cpu1.branchPred.condPredicted         89463085                       # Number of conditional branches predicted
system.cpu1.branchPred.condIncorrect          6609561                       # Number of conditional branches incorrect
system.cpu1.branchPred.BTBLookups            94230263                       # Number of BTB lookups
system.cpu1.branchPred.BTBHits               58109960                       # Number of BTB hits
system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu1.branchPred.BTBHitPct            61.668044                       # BTB Hit Percentage
system.cpu1.branchPred.usedRAS               17839939                       # Number of times the RAS was used to get a target.
system.cpu1.branchPred.RASInCorrect            183627                       # Number of incorrect RAS predictions.
system.cpu1.branchPred.indirectLookups        4347444                       # Number of indirect predictor lookups.
system.cpu1.branchPred.indirectHits           2695405                       # Number of indirect target hits.
system.cpu1.branchPred.indirectMisses         1652039                       # Number of indirect misses.
system.cpu1.branchPredindirectMispredicted       417102                       # Number of mispredicted indirect branches.
system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.dtb.walker.walks                   561952                       # Table walker walks requested
system.cpu1.dtb.walker.walksLong               561952                       # Table walker walks initiated with long descriptors
system.cpu1.dtb.walker.walksLongTerminationLevel::Level2        11814                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksLongTerminationLevel::Level3        88087                       # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore       261651                       # Table walks squashed before starting
system.cpu1.dtb.walker.walkWaitTime::samples       300301                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::mean  2363.057399                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::stdev 13317.227915                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::0-65535       298048     99.25%     99.25% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::65536-131071         1567      0.52%     99.77% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::131072-196607          436      0.15%     99.92% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::196608-262143          167      0.06%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::262144-327679           36      0.01%     99.98% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::327680-393215           40      0.01%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::393216-458751            4      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::458752-524287            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkWaitTime::total       300301                       # Table walker wait (enqueue to first request) latency
system.cpu1.dtb.walker.walkCompletionTime::samples       287935                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::mean 21029.369476                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::gmean 18280.568505                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::stdev 15111.837725                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::0-65535       285795     99.26%     99.26% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::65536-131071         1436      0.50%     99.76% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::131072-196607          377      0.13%     99.89% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::196608-262143          181      0.06%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::262144-327679           86      0.03%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::327680-393215           29      0.01%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::393216-458751           11      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::458752-524287            3      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::524288-589823            1      0.00%     99.99% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::589824-655359           16      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walkCompletionTime::total       287935                       # Table walker service (enqueue to completion) latency
system.cpu1.dtb.walker.walksPending::samples 466714959496                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::mean     0.597643                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::stdev     0.555516                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::0-1 465490623496     99.74%     99.74% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::2-3    621983000      0.13%     99.87% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::4-5    266845500      0.06%     99.93% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::6-7    131382500      0.03%     99.96% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::8-9     96036000      0.02%     99.98% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::10-11     60845000      0.01%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::12-13     18797500      0.00%     99.99% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::14-15     27878000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::16-17       546500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::18-19        22000      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.dtb.walker.walksPending::total 466714959496                       # Table walker pending requests distribution
system.cpu1.dtb.walker.walkPageSizes::4K        88088     88.17%     88.17% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::2M        11814     11.83%    100.00% # Table walker page sizes translated
system.cpu1.dtb.walker.walkPageSizes::total        99902                       # Table walker page sizes translated
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data       561952                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::total       561952                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data        99902                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::total        99902                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin::total       661854                       # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
system.cpu1.dtb.read_hits                    97791245                       # DTB read hits
system.cpu1.dtb.read_misses                    385118                       # DTB read misses
system.cpu1.dtb.write_hits                   81245431                       # DTB write hits
system.cpu1.dtb.write_misses                   176834                       # DTB write misses
system.cpu1.dtb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid              45792                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid                   1079                       # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries                   36850                       # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults                      268                       # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults                  6109                       # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults                    40755                       # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses                98176363                       # DTB read accesses
system.cpu1.dtb.write_accesses               81422265                       # DTB write accesses
system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
system.cpu1.dtb.hits                        179036676                       # DTB hits
system.cpu1.dtb.misses                         561952                       # DTB misses
system.cpu1.dtb.accesses                    179598628                       # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits             0                       # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.itb.walker.walks                    84407                       # Table walker walks requested
system.cpu1.itb.walker.walksLong                84407                       # Table walker walks initiated with long descriptors
system.cpu1.itb.walker.walksLongTerminationLevel::Level2         1027                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksLongTerminationLevel::Level3        60740                       # Level at which table walker walks with long descriptors terminate
system.cpu1.itb.walker.walksSquashedBefore        10156                       # Table walks squashed before starting
system.cpu1.itb.walker.walkWaitTime::samples        74251                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::mean  1057.238286                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::stdev  8622.114888                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::0-65535        74015     99.68%     99.68% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::65536-131071          199      0.27%     99.95% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::131072-196607           18      0.02%     99.97% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::196608-262143           10      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::262144-327679            5      0.01%     99.99% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::327680-393215            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::524288-589823            1      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::589824-655359            2      0.00%    100.00% # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkWaitTime::total        74251                       # Table walker wait (enqueue to first request) latency
system.cpu1.itb.walker.walkCompletionTime::samples        71923                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::mean 24988.821378                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::gmean 22597.090075                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::stdev 18666.984039                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::0-65535        70820     98.47%     98.47% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::65536-131071          715      0.99%     99.46% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::131072-196607          265      0.37%     99.83% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::196608-262143           63      0.09%     99.92% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::262144-327679           24      0.03%     99.95% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::327680-393215           16      0.02%     99.97% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::393216-458751            3      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::458752-524287            3      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::524288-589823            2      0.00%     99.98% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::589824-655359           10      0.01%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::655360-720895            2      0.00%    100.00% # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walkCompletionTime::total        71923                       # Table walker service (enqueue to completion) latency
system.cpu1.itb.walker.walksPending::samples 410850107648                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::mean     0.878728                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::stdev     0.326631                       # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::0    49848543788     12.13%     12.13% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::1   360979116860     87.86%     99.99% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::2       21177000      0.01%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::3        1227500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::4          42500      0.00%    100.00% # Table walker pending requests distribution
system.cpu1.itb.walker.walksPending::total 410850107648                       # Table walker pending requests distribution
system.cpu1.itb.walker.walkPageSizes::4K        60740     98.34%     98.34% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::2M         1027      1.66%    100.00% # Table walker page sizes translated
system.cpu1.itb.walker.walkPageSizes::total        61767                       # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst        84407                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Requested::total        84407                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst        61767                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::total        61767                       # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin::total       146174                       # Table walker requests started/completed, data/inst
system.cpu1.itb.inst_hits                   210802915                       # ITB inst hits
system.cpu1.itb.inst_misses                     84407                       # ITB inst misses
system.cpu1.itb.read_hits                           0                       # DTB read hits
system.cpu1.itb.read_misses                         0                       # DTB read misses
system.cpu1.itb.write_hits                          0                       # DTB write hits
system.cpu1.itb.write_misses                        0                       # DTB write misses
system.cpu1.itb.flush_tlb                          16                       # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid              45792                       # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid                   1079                       # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries                   26222                       # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults                   208943                       # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses                       0                       # DTB read accesses
system.cpu1.itb.write_accesses                      0                       # DTB write accesses
system.cpu1.itb.inst_accesses               210887322                       # ITB inst accesses
system.cpu1.itb.hits                        210802915                       # DTB hits
system.cpu1.itb.misses                          84407                       # DTB misses
system.cpu1.itb.accesses                    210887322                       # DTB accesses
system.cpu1.numPwrStateTransitions              27667                       # Number of power state transitions
system.cpu1.pwrStateClkGateDist::samples        13834                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::mean    3399006591.183533                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::stdev   87524078188.715500                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::underflows         3453     24.96%     24.96% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1000-5e+10        10352     74.83%     99.79% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::5e+10-1e+11            5      0.04%     99.83% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11            2      0.01%     99.84% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11            3      0.02%     99.86% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11            2      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11            1      0.01%     99.88% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11            1      0.01%     99.89% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11            1      0.01%     99.90% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::overflows           14      0.10%    100.00% # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::min_value          501                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::max_value 7390880477084                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateClkGateDist::total          13834                       # Distribution of time spent in the clock gated state
system.cpu1.pwrStateResidencyTicks::ON   363085536567                       # Cumulative time (in ticks) in various power states
system.cpu1.pwrStateResidencyTicks::CLK_GATED 47021857182433                       # Cumulative time (in ticks) in various power states
system.cpu1.numCycles                       726181462                       # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
system.cpu1.fetch.icacheStallCycles          86390303                       # Number of cycles fetch is stalled on an Icache miss
system.cpu1.fetch.Insts                     594062843                       # Number of instructions fetch has processed
system.cpu1.fetch.Branches                  134369829                       # Number of branches that fetch encountered
system.cpu1.fetch.predictedBranches          78645304                       # Number of branches that fetch has predicted taken
system.cpu1.fetch.Cycles                    601498232                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu1.fetch.SquashCycles               14253482                       # Number of cycles fetch has spent squashing
system.cpu1.fetch.TlbCycles                   1820697                       # Number of cycles fetch has spent waiting for tlb
system.cpu1.fetch.MiscStallCycles              287238                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu1.fetch.PendingTrapStallCycles      5988786                       # Number of stall cycles due to pending traps
system.cpu1.fetch.PendingQuiesceStallCycles       713679                       # Number of stall cycles due to pending quiesce instructions
system.cpu1.fetch.IcacheWaitRetryStallCycles       819715                       # Number of stall cycles due to full MSHR
system.cpu1.fetch.CacheLines                210572695                       # Number of cache lines fetched
system.cpu1.fetch.IcacheSquashes              1658938                       # Number of outstanding Icache misses that were squashed
system.cpu1.fetch.ItlbSquashes                  27666                       # Number of outstanding ITLB misses that were squashed
system.cpu1.fetch.rateDist::samples         704645391                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::mean             0.988963                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::stdev            1.222689                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows              0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::0               370929364     52.64%     52.64% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::1               130277469     18.49%     71.13% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::2                43725033      6.21%     77.33% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::3               159713525     22.67%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows               0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value               0                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value               3                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::total           704645391                       # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.branchRate                 0.185036                       # Number of branch fetches per cycle
system.cpu1.fetch.rate                       0.818064                       # Number of inst fetches per cycle
system.cpu1.decode.IdleCycles               103020673                       # Number of cycles decode is idle
system.cpu1.decode.BlockedCycles            337373962                       # Number of cycles decode is blocked
system.cpu1.decode.RunCycles                222407115                       # Number of cycles decode is running
system.cpu1.decode.UnblockCycles             36734416                       # Number of cycles decode is unblocking
system.cpu1.decode.SquashCycles               5109225                       # Number of cycles decode is squashing
system.cpu1.decode.BranchResolved            18739170                       # Number of times decode resolved a branch
system.cpu1.decode.BranchMispred              2055775                       # Number of times decode detected a branch misprediction
system.cpu1.decode.DecodedInsts             616426802                       # Number of instructions handled by decode
system.cpu1.decode.SquashedInsts             23026844                       # Number of squashed instructions handled by decode
system.cpu1.rename.SquashCycles               5109225                       # Number of cycles rename is squashing
system.cpu1.rename.IdleCycles               137867421                       # Number of cycles rename is idle
system.cpu1.rename.BlockCycles               45074504                       # Number of cycles rename is blocking
system.cpu1.rename.serializeStallCycles     232811775                       # count of cycles rename stalled for serializing inst
system.cpu1.rename.RunCycles                223900939                       # Number of cycles rename is running
system.cpu1.rename.UnblockCycles             59881527                       # Number of cycles rename is unblocking
system.cpu1.rename.RenamedInsts             599411621                       # Number of instructions processed by rename
system.cpu1.rename.SquashedInsts              6042296                       # Number of squashed instructions processed by rename
system.cpu1.rename.ROBFullEvents              9969882                       # Number of times rename has blocked due to ROB full
system.cpu1.rename.IQFullEvents                242190                       # Number of times rename has blocked due to IQ full
system.cpu1.rename.LQFullEvents                299313                       # Number of times rename has blocked due to LQ full
system.cpu1.rename.SQFullEvents              25537080                       # Number of times rename has blocked due to SQ full
system.cpu1.rename.FullRegisterEvents           11262                       # Number of times there has been no free registers
system.cpu1.rename.RenamedOperands          571214843                       # Number of destination operands rename has renamed
system.cpu1.rename.RenameLookups            926423560                       # Number of register rename lookups that rename has made
system.cpu1.rename.int_rename_lookups       707359605                       # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups           805393                       # Number of floating rename lookups
system.cpu1.rename.CommittedMaps            514629531                       # Number of HB maps that are committed
system.cpu1.rename.UndoneMaps                56585312                       # Number of HB maps that are undone due to squashing
system.cpu1.rename.serializingInsts          15957043                       # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts      14048251                       # count of temporary serializing insts renamed
system.cpu1.rename.skidInsts                 73992297                       # count of insts added to the skid buffer
system.cpu1.memDep0.insertedLoads            98060208                       # Number of loads inserted to the mem dependence unit.
system.cpu1.memDep0.insertedStores           84478655                       # Number of stores inserted to the mem dependence unit.
system.cpu1.memDep0.conflictingLoads          8950565                       # Number of conflicting loads.
system.cpu1.memDep0.conflictingStores         7675207                       # Number of conflicting stores.
system.cpu1.iq.iqInstsAdded                 576680308                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu1.iq.iqNonSpecInstsAdded           16104006                       # Number of non-speculative instructions added to the IQ
system.cpu1.iq.iqInstsIssued                581772484                       # Number of instructions issued
system.cpu1.iq.iqSquashedInstsIssued          2680133                       # Number of squashed instructions issued
system.cpu1.iq.iqSquashedInstsExamined       53366771                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu1.iq.iqSquashedOperandsExamined     34273904                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu1.iq.iqSquashedNonSpecRemoved        266458                       # Number of squashed non-spec instructions that were removed
system.cpu1.iq.issued_per_cycle::samples    704645391                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::mean        0.825624                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::stdev       1.067009                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::0          385934490     54.77%     54.77% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::1          135280434     19.20%     73.97% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::2          111501247     15.82%     89.79% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::3           64231431      9.12%     98.91% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::4            7693682      1.09%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5               4107      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::8                  0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value            5                       # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::total      704645391                       # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass                  0      0.00%      0.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntAlu               58591735     44.23%     44.23% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntMult                 49305      0.04%     44.27% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv                  21310      0.02%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCvt                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatMult                   0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatDiv                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatSqrt                   0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAdd                     0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAddAcc                  0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdAlu                     0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCmp                     0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdCvt                     0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMisc                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMult                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdMultAcc                 0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShift                   0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdShiftAcc                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdSqrt                    0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAdd                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatAlu                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCmp                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatCvt                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatDiv                0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMisc              60      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult               0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc            0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt               0      0.00%     44.29% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemRead              35005485     26.43%     70.71% # attempts to use FU when none available
system.cpu1.iq.fu_full::MemWrite             38791699     29.29%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess                   0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch                0      0.00%    100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass               36      0.00%      0.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IntAlu            397008075     68.24%     68.24% # Type of FU issued
system.cpu1.iq.FU_type_0::IntMult             1247296      0.21%     68.46% # Type of FU issued
system.cpu1.iq.FU_type_0::IntDiv                70487      0.01%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatAdd                  0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCmp                  0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatCvt                  0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatMult                 0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv                  0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt                 0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd                   0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAddAcc                0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAlu                   0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCmp                   0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdCvt                   0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMisc                  0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMult                  0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdMultAcc               0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShift                 0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdShiftAcc              0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdSqrt                  0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAdd              8      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatAlu              0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCmp             15      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatCvt             24      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatDiv              0      0.00%     68.47% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc         78078      0.01%     68.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult             0      0.00%     68.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc            0      0.00%     68.48% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt             0      0.00%     68.48% # Type of FU issued
system.cpu1.iq.FU_type_0::MemRead           100884939     17.34%     85.82% # Type of FU issued
system.cpu1.iq.FU_type_0::MemWrite           82483526     14.18%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess                 0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch              0      0.00%    100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::total             581772484                       # Type of FU issued
system.cpu1.iq.rate                          0.801139                       # Inst issue rate
system.cpu1.iq.fu_busy_cnt                  132459594                       # FU busy when requested
system.cpu1.iq.fu_busy_rate                  0.227683                       # FU busy rate (busy events/executed inst)
system.cpu1.iq.int_inst_queue_reads        2001993843                       # Number of integer instruction queue reads
system.cpu1.iq.int_inst_queue_writes        645760406                       # Number of integer instruction queue writes
system.cpu1.iq.int_inst_queue_wakeup_accesses    564750025                       # Number of integer instruction queue wakeup accesses
system.cpu1.iq.fp_inst_queue_reads            1336243                       # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes            531893                       # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses       495883                       # Number of floating instruction queue wakeup accesses
system.cpu1.iq.int_alu_accesses             713403384                       # Number of integer alu accesses
system.cpu1.iq.fp_alu_accesses                 828658                       # Number of floating point alu accesses
system.cpu1.iew.lsq.thread0.forwLoads         2572358                       # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads            0                       # Number of loads ignored due to an invalid address
system.cpu1.iew.lsq.thread0.squashedLoads     12226985                       # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses        16460                       # Number of memory responses ignored because the instruction is squashed
system.cpu1.iew.lsq.thread0.memOrderViolation       142391                       # Number of memory ordering violations
system.cpu1.iew.lsq.thread0.squashedStores      5497757                       # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs            0                       # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads            0                       # Number of blocked loads due to partial load-store forwarding
system.cpu1.iew.lsq.thread0.rescheduledLoads      2564544                       # Number of loads that were rescheduled
system.cpu1.iew.lsq.thread0.cacheBlocked      4190277                       # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles                       0                       # Number of cycles IEW is idle
system.cpu1.iew.iewSquashCycles               5109225                       # Number of cycles IEW is squashing
system.cpu1.iew.iewBlockCycles                6111838                       # Number of cycles IEW is blocking
system.cpu1.iew.iewUnblockCycles              1648605                       # Number of cycles IEW is unblocking
system.cpu1.iew.iewDispatchedInsts          592918318                       # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts                0                       # Number of squashed instructions skipped by dispatch
system.cpu1.iew.iewDispLoadInsts             98060208                       # Number of dispatched load instructions
system.cpu1.iew.iewDispStoreInsts            84478655                       # Number of dispatched store instructions
system.cpu1.iew.iewDispNonSpecInsts          13792326                       # Number of dispatched non-speculative instructions
system.cpu1.iew.iewIQFullEvents                 62841                       # Number of times the IQ has become full, causing a stall
system.cpu1.iew.iewLSQFullEvents              1527139                       # Number of times the LSQ has become full, causing a stall
system.cpu1.iew.memOrderViolationEvents        142391                       # Number of memory order violations
system.cpu1.iew.predictedTakenIncorrect       1885740                       # Number of branches that were predicted taken incorrectly
system.cpu1.iew.predictedNotTakenIncorrect      3046567                       # Number of branches that were predicted not taken incorrectly
system.cpu1.iew.branchMispredicts             4932307                       # Number of branch mispredicts detected at execute
system.cpu1.iew.iewExecutedInsts            573876367                       # Number of executed instructions
system.cpu1.iew.iewExecLoadInsts             97784309                       # Number of load instructions executed
system.cpu1.iew.iewExecSquashedInsts          7346483                       # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp                            0                       # number of swp insts executed
system.cpu1.iew.exec_nop                       134004                       # number of nop insts executed
system.cpu1.iew.exec_refs                   179029158                       # number of memory reference insts executed
system.cpu1.iew.exec_branches               107707763                       # Number of branches executed
system.cpu1.iew.exec_stores                  81244849                       # Number of stores executed
system.cpu1.iew.exec_rate                    0.790266                       # Inst execution rate
system.cpu1.iew.wb_sent                     565995055                       # cumulative count of insts sent to commit
system.cpu1.iew.wb_count                    565245908                       # cumulative count of insts written-back
system.cpu1.iew.wb_producers                273023556                       # num instructions producing a value
system.cpu1.iew.wb_consumers                448078183                       # num instructions consuming a value
system.cpu1.iew.wb_rate                      0.778381                       # insts written-back per cycle
system.cpu1.iew.wb_fanout                    0.609321                       # average fanout of values written-back
system.cpu1.commit.commitSquashedInsts       46535716                       # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls       15837548                       # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts          4592045                       # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::samples    695790390                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::mean     0.775259                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::stdev     1.568649                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::0    457970279     65.82%     65.82% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::1    124243355     17.86%     83.68% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::2     52434114      7.54%     91.21% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::3     17645088      2.54%     93.75% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::4     12549968      1.80%     95.55% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::5      8433891      1.21%     96.76% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::6      5802471      0.83%     97.60% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::7      3503250      0.50%     98.10% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::8     13207974      1.90%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total    695790390                       # Number of insts commited each cycle
system.cpu1.commit.committedInsts           458018039                       # Number of instructions committed
system.cpu1.commit.committedOps             539417542                       # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
system.cpu1.commit.refs                     164814121                       # Number of memory references committed
system.cpu1.commit.loads                     85833223                       # Number of loads committed
system.cpu1.commit.membars                    3719425                       # Number of memory barriers committed
system.cpu1.commit.branches                 102343051                       # Number of branches committed
system.cpu1.commit.fp_insts                    486729                       # Number of committed floating point instructions.
system.cpu1.commit.int_insts                494686776                       # Number of committed integer instructions.
system.cpu1.commit.function_calls            13237013                       # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IntAlu       373462182     69.23%     69.23% # Class of committed instruction
system.cpu1.commit.op_class_0::IntMult        1014464      0.19%     69.42% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv           55738      0.01%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCvt             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatMult            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatDiv             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatSqrt            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAdd              0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAddAcc            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdAlu              0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCmp              0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdCvt              0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMisc             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMult             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdMultAcc            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShift            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdShiftAcc            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdSqrt             0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAdd            8      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatAlu            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp           13      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt           21      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv            0      0.00%     69.43% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMisc        70995      0.01%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt            0      0.00%     69.45% # Class of committed instruction
system.cpu1.commit.op_class_0::MemRead       85833223     15.91%     85.36% # Class of committed instruction
system.cpu1.commit.op_class_0::MemWrite      78980898     14.64%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::total        539417542                       # Class of committed instruction
system.cpu1.commit.bw_lim_events             13207974                       # number cycles where commit BW limit reached
system.cpu1.rob.rob_reads                  1264391907                       # The number of ROB reads
system.cpu1.rob.rob_writes                 1180722952                       # The number of ROB writes
system.cpu1.timesIdled                         944459                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles                       21536071                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles                 94043695657                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts                  458018039                       # Number of Instructions Simulated
system.cpu1.committedOps                    539417542                       # Number of Ops (including micro ops) Simulated
system.cpu1.cpi                              1.585487                       # CPI: Cycles Per Instruction
system.cpu1.cpi_total                        1.585487                       # CPI: Total CPI of All Threads
system.cpu1.ipc                              0.630721                       # IPC: Instructions Per Cycle
system.cpu1.ipc_total                        0.630721                       # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads               677403787                       # number of integer regfile reads
system.cpu1.int_regfile_writes              401367044                       # number of integer regfile writes
system.cpu1.fp_regfile_reads                   791707                       # number of floating regfile reads
system.cpu1.fp_regfile_writes                  438600                       # number of floating regfile writes
system.cpu1.cc_regfile_reads                124889457                       # number of cc regfile reads
system.cpu1.cc_regfile_writes               125620500                       # number of cc regfile writes
system.cpu1.misc_regfile_reads             1260290191                       # number of misc regfile reads
system.cpu1.misc_regfile_writes              15974322                       # number of misc regfile writes
system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.tags.replacements          5362331                       # number of replacements
system.cpu1.dcache.tags.tagsinuse          456.510727                       # Cycle average of tags in use
system.cpu1.dcache.tags.total_refs          153804268                       # Total number of references to valid blocks.
system.cpu1.dcache.tags.sampled_refs          5362842                       # Sample count of references to valid blocks.
system.cpu1.dcache.tags.avg_refs            28.679620                       # Average number of references to valid blocks.
system.cpu1.dcache.tags.warmup_cycle     8517840775000                       # Cycle when the warmup percentage was hit.
system.cpu1.dcache.tags.occ_blocks::cpu1.data   456.510727                       # Average occupied blocks per requestor
system.cpu1.dcache.tags.occ_percent::cpu1.data     0.891623                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_percent::total     0.891623                       # Average percentage of cache occupancy
system.cpu1.dcache.tags.occ_task_id_blocks::1024          511                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::0           95                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::1          382                       # Occupied blocks per task id
system.cpu1.dcache.tags.age_task_id_blocks_1024::2           34                       # Occupied blocks per task id
system.cpu1.dcache.tags.occ_task_id_percent::1024     0.998047                       # Percentage of cache occupancy per task id
system.cpu1.dcache.tags.tag_accesses        341608540                       # Number of tag accesses
system.cpu1.dcache.tags.data_accesses       341608540                       # Number of data accesses
system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.dcache.ReadReq_hits::cpu1.data     79940930                       # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total       79940930                       # number of ReadReq hits
system.cpu1.dcache.WriteReq_hits::cpu1.data     69078558                       # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total      69078558                       # number of WriteReq hits
system.cpu1.dcache.SoftPFReq_hits::cpu1.data       191831                       # number of SoftPFReq hits
system.cpu1.dcache.SoftPFReq_hits::total       191831                       # number of SoftPFReq hits
system.cpu1.dcache.WriteLineReq_hits::cpu1.data       170764                       # number of WriteLineReq hits
system.cpu1.dcache.WriteLineReq_hits::total       170764                       # number of WriteLineReq hits
system.cpu1.dcache.LoadLockedReq_hits::cpu1.data      1820637                       # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total      1820637                       # number of LoadLockedReq hits
system.cpu1.dcache.StoreCondReq_hits::cpu1.data      1828950                       # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total      1828950                       # number of StoreCondReq hits
system.cpu1.dcache.demand_hits::cpu1.data    149190252                       # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total       149190252                       # number of demand (read+write) hits
system.cpu1.dcache.overall_hits::cpu1.data    149382083                       # number of overall hits
system.cpu1.dcache.overall_hits::total      149382083                       # number of overall hits
system.cpu1.dcache.ReadReq_misses::cpu1.data      6220385                       # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total      6220385                       # number of ReadReq misses
system.cpu1.dcache.WriteReq_misses::cpu1.data      7237581                       # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total      7237581                       # number of WriteReq misses
system.cpu1.dcache.SoftPFReq_misses::cpu1.data       689658                       # number of SoftPFReq misses
system.cpu1.dcache.SoftPFReq_misses::total       689658                       # number of SoftPFReq misses
system.cpu1.dcache.WriteLineReq_misses::cpu1.data       463987                       # number of WriteLineReq misses
system.cpu1.dcache.WriteLineReq_misses::total       463987                       # number of WriteLineReq misses
system.cpu1.dcache.LoadLockedReq_misses::cpu1.data       244543                       # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total       244543                       # number of LoadLockedReq misses
system.cpu1.dcache.StoreCondReq_misses::cpu1.data       192296                       # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total       192296                       # number of StoreCondReq misses
system.cpu1.dcache.demand_misses::cpu1.data     13921953                       # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total      13921953                       # number of demand (read+write) misses
system.cpu1.dcache.overall_misses::cpu1.data     14611611                       # number of overall misses
system.cpu1.dcache.overall_misses::total     14611611                       # number of overall misses
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data  96362388500                       # number of ReadReq miss cycles
system.cpu1.dcache.ReadReq_miss_latency::total  96362388500                       # number of ReadReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 134833660621                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteReq_miss_latency::total 134833660621                       # number of WriteReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data  11613680644                       # number of WriteLineReq miss cycles
system.cpu1.dcache.WriteLineReq_miss_latency::total  11613680644                       # number of WriteLineReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data   3499456000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.LoadLockedReq_miss_latency::total   3499456000                       # number of LoadLockedReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data   4567503000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondReq_miss_latency::total   4567503000                       # number of StoreCondReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data      3019500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.StoreCondFailReq_miss_latency::total      3019500                       # number of StoreCondFailReq miss cycles
system.cpu1.dcache.demand_miss_latency::cpu1.data 242809729765                       # number of demand (read+write) miss cycles
system.cpu1.dcache.demand_miss_latency::total 242809729765                       # number of demand (read+write) miss cycles
system.cpu1.dcache.overall_miss_latency::cpu1.data 242809729765                       # number of overall miss cycles
system.cpu1.dcache.overall_miss_latency::total 242809729765                       # number of overall miss cycles
system.cpu1.dcache.ReadReq_accesses::cpu1.data     86161315                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total     86161315                       # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::cpu1.data     76316139                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total     76316139                       # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::cpu1.data       881489                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.SoftPFReq_accesses::total       881489                       # number of SoftPFReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::cpu1.data       634751                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.WriteLineReq_accesses::total       634751                       # number of WriteLineReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data      2065180                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total      2065180                       # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::cpu1.data      2021246                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total      2021246                       # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.demand_accesses::cpu1.data    163112205                       # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total    163112205                       # number of demand (read+write) accesses
system.cpu1.dcache.overall_accesses::cpu1.data    163993694                       # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total    163993694                       # number of overall (read+write) accesses
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.072195                       # miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_miss_rate::total     0.072195                       # miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.094837                       # miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_miss_rate::total     0.094837                       # miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data     0.782378                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_miss_rate::total     0.782378                       # miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data     0.730975                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_miss_rate::total     0.730975                       # miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.118412                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_miss_rate::total     0.118412                       # miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.095137                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_miss_rate::total     0.095137                       # miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_miss_rate::cpu1.data     0.085352                       # miss rate for demand accesses
system.cpu1.dcache.demand_miss_rate::total     0.085352                       # miss rate for demand accesses
system.cpu1.dcache.overall_miss_rate::cpu1.data     0.089099                       # miss rate for overall accesses
system.cpu1.dcache.overall_miss_rate::total     0.089099                       # miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15491.386546                       # average ReadReq miss latency
system.cpu1.dcache.ReadReq_avg_miss_latency::total 15491.386546                       # average ReadReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18629.658255                       # average WriteReq miss latency
system.cpu1.dcache.WriteReq_avg_miss_latency::total 18629.658255                       # average WriteReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25030.185423                       # average WriteLineReq miss latency
system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25030.185423                       # average WriteLineReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14310.186757                       # average LoadLockedReq miss latency
system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14310.186757                       # average LoadLockedReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23752.459750                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23752.459750                       # average StoreCondReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total          inf                       # average StoreCondFailReq miss latency
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17440.780741                       # average overall miss latency
system.cpu1.dcache.demand_avg_miss_latency::total 17440.780741                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16617.587873                       # average overall miss latency
system.cpu1.dcache.overall_avg_miss_latency::total 16617.587873                       # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs      3018250                       # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets     21738633                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs           378529                       # number of cycles access was blocked
system.cpu1.dcache.blocked::no_targets         731712                       # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_mshrs     7.973629                       # average number of cycles each access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets    29.709275                       # average number of cycles each access was blocked
system.cpu1.dcache.writebacks::writebacks      5362354                       # number of writebacks
system.cpu1.dcache.writebacks::total          5362354                       # number of writebacks
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data      3187456                       # number of ReadReq MSHR hits
system.cpu1.dcache.ReadReq_mshr_hits::total      3187456                       # number of ReadReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      5861363                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteReq_mshr_hits::total      5861363                       # number of WriteReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data         3594                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.WriteLineReq_mshr_hits::total         3594                       # number of WriteLineReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data       128092                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.LoadLockedReq_mshr_hits::total       128092                       # number of LoadLockedReq MSHR hits
system.cpu1.dcache.demand_mshr_hits::cpu1.data      9052413                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.demand_mshr_hits::total      9052413                       # number of demand (read+write) MSHR hits
system.cpu1.dcache.overall_mshr_hits::cpu1.data      9052413                       # number of overall MSHR hits
system.cpu1.dcache.overall_mshr_hits::total      9052413                       # number of overall MSHR hits
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data      3032929                       # number of ReadReq MSHR misses
system.cpu1.dcache.ReadReq_mshr_misses::total      3032929                       # number of ReadReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data      1376218                       # number of WriteReq MSHR misses
system.cpu1.dcache.WriteReq_mshr_misses::total      1376218                       # number of WriteReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data       689576                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.SoftPFReq_mshr_misses::total       689576                       # number of SoftPFReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data       460393                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.WriteLineReq_mshr_misses::total       460393                       # number of WriteLineReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data       116451                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.LoadLockedReq_mshr_misses::total       116451                       # number of LoadLockedReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data       192288                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.StoreCondReq_mshr_misses::total       192288                       # number of StoreCondReq MSHR misses
system.cpu1.dcache.demand_mshr_misses::cpu1.data      4869540                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.demand_mshr_misses::total      4869540                       # number of demand (read+write) MSHR misses
system.cpu1.dcache.overall_mshr_misses::cpu1.data      5559116                       # number of overall MSHR misses
system.cpu1.dcache.overall_mshr_misses::total      5559116                       # number of overall MSHR misses
system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data        21291                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.ReadReq_mshr_uncacheable::total        21291                       # number of ReadReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data        19410                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.WriteReq_mshr_uncacheable::total        19410                       # number of WriteReq MSHR uncacheable
system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data        40701                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.overall_mshr_uncacheable_misses::total        40701                       # number of overall MSHR uncacheable misses
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data  42726170500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_miss_latency::total  42726170500                       # number of ReadReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data  26732145261                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.WriteReq_mshr_miss_latency::total  26732145261                       # number of WriteReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data  16635879000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total  16635879000                       # number of SoftPFReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data  11021618644                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total  11021618644                       # number of WriteLineReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data   1587191500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total   1587191500                       # number of LoadLockedReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data   4375287000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total   4375287000                       # number of StoreCondReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data      2947500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total      2947500                       # number of StoreCondFailReq MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data  80479934405                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.demand_mshr_miss_latency::total  80479934405                       # number of demand (read+write) MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data  97115813405                       # number of overall MSHR miss cycles
system.cpu1.dcache.overall_mshr_miss_latency::total  97115813405                       # number of overall MSHR miss cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   3797634000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   3797634000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data   3797634000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.overall_mshr_uncacheable_latency::total   3797634000                       # number of overall MSHR uncacheable cycles
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035201                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.ReadReq_mshr_miss_rate::total     0.035201                       # mshr miss rate for ReadReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.018033                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.WriteReq_mshr_miss_rate::total     0.018033                       # mshr miss rate for WriteReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data     0.782285                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total     0.782285                       # mshr miss rate for SoftPFReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data     0.725313                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total     0.725313                       # mshr miss rate for WriteLineReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.056388                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total     0.056388                       # mshr miss rate for LoadLockedReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.095133                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total     0.095133                       # mshr miss rate for StoreCondReq accesses
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.029854                       # mshr miss rate for demand accesses
system.cpu1.dcache.demand_mshr_miss_rate::total     0.029854                       # mshr miss rate for demand accesses
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.033898                       # mshr miss rate for overall accesses
system.cpu1.dcache.overall_mshr_miss_rate::total     0.033898                       # mshr miss rate for overall accesses
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14087.428522                       # average ReadReq mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14087.428522                       # average ReadReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19424.353744                       # average WriteReq mshr miss latency
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19424.353744                       # average WriteReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24124.794076                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.794076                       # average SoftPFReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23939.587796                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23939.587796                       # average WriteLineReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13629.694034                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13629.694034                       # average LoadLockedReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22753.822391                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22753.822391                       # average StoreCondReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total          inf                       # average StoreCondFailReq mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16527.214974                       # average overall mshr miss latency
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16527.214974                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17469.650463                       # average overall mshr miss latency
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17469.650463                       # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178368.042835                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178368.042835                       # average ReadReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 93305.668165                       # average overall mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 93305.668165                       # average overall mshr uncacheable latency
system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.tags.replacements          5902862                       # number of replacements
system.cpu1.icache.tags.tagsinuse          501.529159                       # Cycle average of tags in use
system.cpu1.icache.tags.total_refs          204324856                       # Total number of references to valid blocks.
system.cpu1.icache.tags.sampled_refs          5903374                       # Sample count of references to valid blocks.
system.cpu1.icache.tags.avg_refs            34.611538                       # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle     8518180301500                       # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst   501.529159                       # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst     0.979549                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total     0.979549                       # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::0          175                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::1          243                       # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2           94                       # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu1.icache.tags.tag_accesses        427035149                       # Number of tag accesses
system.cpu1.icache.tags.data_accesses       427035149                       # Number of data accesses
system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.icache.ReadReq_hits::cpu1.inst    204324856                       # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total      204324856                       # number of ReadReq hits
system.cpu1.icache.demand_hits::cpu1.inst    204324856                       # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total       204324856                       # number of demand (read+write) hits
system.cpu1.icache.overall_hits::cpu1.inst    204324856                       # number of overall hits
system.cpu1.icache.overall_hits::total      204324856                       # number of overall hits
system.cpu1.icache.ReadReq_misses::cpu1.inst      6241016                       # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total      6241016                       # number of ReadReq misses
system.cpu1.icache.demand_misses::cpu1.inst      6241016                       # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total       6241016                       # number of demand (read+write) misses
system.cpu1.icache.overall_misses::cpu1.inst      6241016                       # number of overall misses
system.cpu1.icache.overall_misses::total      6241016                       # number of overall misses
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst  68483006769                       # number of ReadReq miss cycles
system.cpu1.icache.ReadReq_miss_latency::total  68483006769                       # number of ReadReq miss cycles
system.cpu1.icache.demand_miss_latency::cpu1.inst  68483006769                       # number of demand (read+write) miss cycles
system.cpu1.icache.demand_miss_latency::total  68483006769                       # number of demand (read+write) miss cycles
system.cpu1.icache.overall_miss_latency::cpu1.inst  68483006769                       # number of overall miss cycles
system.cpu1.icache.overall_miss_latency::total  68483006769                       # number of overall miss cycles
system.cpu1.icache.ReadReq_accesses::cpu1.inst    210565872                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total    210565872                       # number of ReadReq accesses(hits+misses)
system.cpu1.icache.demand_accesses::cpu1.inst    210565872                       # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total    210565872                       # number of demand (read+write) accesses
system.cpu1.icache.overall_accesses::cpu1.inst    210565872                       # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total    210565872                       # number of overall (read+write) accesses
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.029639                       # miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_miss_rate::total     0.029639                       # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst     0.029639                       # miss rate for demand accesses
system.cpu1.icache.demand_miss_rate::total     0.029639                       # miss rate for demand accesses
system.cpu1.icache.overall_miss_rate::cpu1.inst     0.029639                       # miss rate for overall accesses
system.cpu1.icache.overall_miss_rate::total     0.029639                       # miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10973.054190                       # average ReadReq miss latency
system.cpu1.icache.ReadReq_avg_miss_latency::total 10973.054190                       # average ReadReq miss latency
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10973.054190                       # average overall miss latency
system.cpu1.icache.demand_avg_miss_latency::total 10973.054190                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10973.054190                       # average overall miss latency
system.cpu1.icache.overall_avg_miss_latency::total 10973.054190                       # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs     10089385                       # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets          780                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs           729550                       # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets              2                       # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_mshrs    13.829600                       # average number of cycles each access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets          390                       # average number of cycles each access was blocked
system.cpu1.icache.writebacks::writebacks      5902862                       # number of writebacks
system.cpu1.icache.writebacks::total          5902862                       # number of writebacks
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst       337611                       # number of ReadReq MSHR hits
system.cpu1.icache.ReadReq_mshr_hits::total       337611                       # number of ReadReq MSHR hits
system.cpu1.icache.demand_mshr_hits::cpu1.inst       337611                       # number of demand (read+write) MSHR hits
system.cpu1.icache.demand_mshr_hits::total       337611                       # number of demand (read+write) MSHR hits
system.cpu1.icache.overall_mshr_hits::cpu1.inst       337611                       # number of overall MSHR hits
system.cpu1.icache.overall_mshr_hits::total       337611                       # number of overall MSHR hits
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst      5903405                       # number of ReadReq MSHR misses
system.cpu1.icache.ReadReq_mshr_misses::total      5903405                       # number of ReadReq MSHR misses
system.cpu1.icache.demand_mshr_misses::cpu1.inst      5903405                       # number of demand (read+write) MSHR misses
system.cpu1.icache.demand_mshr_misses::total      5903405                       # number of demand (read+write) MSHR misses
system.cpu1.icache.overall_mshr_misses::cpu1.inst      5903405                       # number of overall MSHR misses
system.cpu1.icache.overall_mshr_misses::total      5903405                       # number of overall MSHR misses
system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.ReadReq_mshr_uncacheable::total           67                       # number of ReadReq MSHR uncacheable
system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.overall_mshr_uncacheable_misses::total           67                       # number of overall MSHR uncacheable misses
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst  61792345334                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_miss_latency::total  61792345334                       # number of ReadReq MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst  61792345334                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.demand_mshr_miss_latency::total  61792345334                       # number of demand (read+write) MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst  61792345334                       # number of overall MSHR miss cycles
system.cpu1.icache.overall_mshr_miss_latency::total  61792345334                       # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      7079498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      7079498                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      7079498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total      7079498                       # number of overall MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.028036                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.ReadReq_mshr_miss_rate::total     0.028036                       # mshr miss rate for ReadReq accesses
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.028036                       # mshr miss rate for demand accesses
system.cpu1.icache.demand_mshr_miss_rate::total     0.028036                       # mshr miss rate for demand accesses
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.028036                       # mshr miss rate for overall accesses
system.cpu1.icache.overall_mshr_miss_rate::total     0.028036                       # mshr miss rate for overall accesses
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10467.238032                       # average ReadReq mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10467.238032                       # average ReadReq mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10467.238032                       # average overall mshr miss latency
system.cpu1.icache.demand_avg_mshr_miss_latency::total 10467.238032                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10467.238032                       # average overall mshr miss latency
system.cpu1.icache.overall_avg_mshr_miss_latency::total 10467.238032                       # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 105664.149254                       # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254                       # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 105664.149254                       # average overall mshr uncacheable latency
system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.prefetcher.num_hwpf_issued      7372835                       # number of hwpf issued
system.cpu1.l2cache.prefetcher.pfIdentified      7380898                       # number of prefetch candidates identified
system.cpu1.l2cache.prefetcher.pfBufferHit         7290                       # number of redundant prefetches already in prefetch queue
system.cpu1.l2cache.prefetcher.pfInCache            0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu1.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu1.l2cache.prefetcher.pfSpanPage       895622                       # number of prefetches not generated due to page crossing
system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.tags.replacements         2111480                       # number of replacements
system.cpu1.l2cache.tags.tagsinuse       12950.875249                       # Cycle average of tags in use
system.cpu1.l2cache.tags.total_refs          10279593                       # Total number of references to valid blocks.
system.cpu1.l2cache.tags.sampled_refs         2126904                       # Sample count of references to valid blocks.
system.cpu1.l2cache.tags.avg_refs            4.833125                       # Average number of references to valid blocks.
system.cpu1.l2cache.tags.warmup_cycle               0                       # Cycle when the warmup percentage was hit.
system.cpu1.l2cache.tags.occ_blocks::writebacks 12615.195694                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker    33.253837                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker    24.384299                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher   278.041418                       # Average occupied blocks per requestor
system.cpu1.l2cache.tags.occ_percent::writebacks     0.769970                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker     0.002030                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker     0.001488                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher     0.016970                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_percent::total     0.790459                       # Average percentage of cache occupancy
system.cpu1.l2cache.tags.occ_task_id_blocks::1022          414                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1023          111                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_blocks::1024        14899                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::1           65                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::2          128                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::3          114                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1022::4          107                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::1            7                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::2           89                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::3            6                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1023::4            9                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::0          279                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::1         1377                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::2         5586                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::3         5487                       # Occupied blocks per task id
system.cpu1.l2cache.tags.age_task_id_blocks_1024::4         2170                       # Occupied blocks per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1022     0.025269                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1023     0.006775                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.occ_task_id_percent::1024     0.909363                       # Percentage of cache occupancy per task id
system.cpu1.l2cache.tags.tag_accesses       393006433                       # Number of tag accesses
system.cpu1.l2cache.tags.data_accesses      393006433                       # Number of data accesses
system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker       563217                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker       188120                       # number of ReadReq hits
system.cpu1.l2cache.ReadReq_hits::total        751337                       # number of ReadReq hits
system.cpu1.l2cache.WritebackDirty_hits::writebacks      3404083                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackDirty_hits::total      3404083                       # number of WritebackDirty hits
system.cpu1.l2cache.WritebackClean_hits::writebacks      7859423                       # number of WritebackClean hits
system.cpu1.l2cache.WritebackClean_hits::total      7859423                       # number of WritebackClean hits
system.cpu1.l2cache.UpgradeReq_hits::cpu1.data           37                       # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total           37                       # number of UpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data            1                       # number of SCUpgradeReq hits
system.cpu1.l2cache.SCUpgradeReq_hits::total            1                       # number of SCUpgradeReq hits
system.cpu1.l2cache.ReadExReq_hits::cpu1.data       897837                       # number of ReadExReq hits
system.cpu1.l2cache.ReadExReq_hits::total       897837                       # number of ReadExReq hits
system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst      5343474                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadCleanReq_hits::total      5343474                       # number of ReadCleanReq hits
system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data      2865962                       # number of ReadSharedReq hits
system.cpu1.l2cache.ReadSharedReq_hits::total      2865962                       # number of ReadSharedReq hits
system.cpu1.l2cache.InvalidateReq_hits::cpu1.data       200218                       # number of InvalidateReq hits
system.cpu1.l2cache.InvalidateReq_hits::total       200218                       # number of InvalidateReq hits
system.cpu1.l2cache.demand_hits::cpu1.dtb.walker       563217                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.itb.walker       188120                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.inst      5343474                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::cpu1.data      3763799                       # number of demand (read+write) hits
system.cpu1.l2cache.demand_hits::total        9858610                       # number of demand (read+write) hits
system.cpu1.l2cache.overall_hits::cpu1.dtb.walker       563217                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.itb.walker       188120                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.inst      5343474                       # number of overall hits
system.cpu1.l2cache.overall_hits::cpu1.data      3763799                       # number of overall hits
system.cpu1.l2cache.overall_hits::total       9858610                       # number of overall hits
system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker        20588                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker         9811                       # number of ReadReq misses
system.cpu1.l2cache.ReadReq_misses::total        30399                       # number of ReadReq misses
system.cpu1.l2cache.UpgradeReq_misses::cpu1.data       230170                       # number of UpgradeReq misses
system.cpu1.l2cache.UpgradeReq_misses::total       230170                       # number of UpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data       192283                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeReq_misses::total       192283                       # number of SCUpgradeReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data            4                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.SCUpgradeFailReq_misses::total            4                       # number of SCUpgradeFailReq misses
system.cpu1.l2cache.ReadExReq_misses::cpu1.data       257129                       # number of ReadExReq misses
system.cpu1.l2cache.ReadExReq_misses::total       257129                       # number of ReadExReq misses
system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst       559914                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadCleanReq_misses::total       559914                       # number of ReadCleanReq misses
system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data       968987                       # number of ReadSharedReq misses
system.cpu1.l2cache.ReadSharedReq_misses::total       968987                       # number of ReadSharedReq misses
system.cpu1.l2cache.InvalidateReq_misses::cpu1.data       258105                       # number of InvalidateReq misses
system.cpu1.l2cache.InvalidateReq_misses::total       258105                       # number of InvalidateReq misses
system.cpu1.l2cache.demand_misses::cpu1.dtb.walker        20588                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.itb.walker         9811                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.inst       559914                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::cpu1.data      1226116                       # number of demand (read+write) misses
system.cpu1.l2cache.demand_misses::total      1816429                       # number of demand (read+write) misses
system.cpu1.l2cache.overall_misses::cpu1.dtb.walker        20588                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.itb.walker         9811                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.inst       559914                       # number of overall misses
system.cpu1.l2cache.overall_misses::cpu1.data      1226116                       # number of overall misses
system.cpu1.l2cache.overall_misses::total      1816429                       # number of overall misses
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker    677842000                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker    364880500                       # number of ReadReq miss cycles
system.cpu1.l2cache.ReadReq_miss_latency::total   1042722500                       # number of ReadReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data    983294000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.UpgradeReq_miss_latency::total    983294000                       # number of UpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data    271676000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeReq_miss_latency::total    271676000                       # number of SCUpgradeReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data      2839500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total      2839500                       # number of SCUpgradeFailReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data  12532259990                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadExReq_miss_latency::total  12532259990                       # number of ReadExReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst  20571950500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadCleanReq_miss_latency::total  20571950500                       # number of ReadCleanReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data  36061918479                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.ReadSharedReq_miss_latency::total  36061918479                       # number of ReadSharedReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data    340389000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.InvalidateReq_miss_latency::total    340389000                       # number of InvalidateReq miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker    677842000                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker    364880500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.inst  20571950500                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::cpu1.data  48594178469                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.demand_miss_latency::total  70208851469                       # number of demand (read+write) miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker    677842000                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker    364880500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.inst  20571950500                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::cpu1.data  48594178469                       # number of overall miss cycles
system.cpu1.l2cache.overall_miss_latency::total  70208851469                       # number of overall miss cycles
system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker       583805                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker       197931                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.ReadReq_accesses::total       781736                       # number of ReadReq accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::writebacks      3404083                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackDirty_accesses::total      3404083                       # number of WritebackDirty accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::writebacks      7859423                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.WritebackClean_accesses::total      7859423                       # number of WritebackClean accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data       230207                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.UpgradeReq_accesses::total       230207                       # number of UpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data       192284                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeReq_accesses::total       192284                       # number of SCUpgradeReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.SCUpgradeFailReq_accesses::total            4                       # number of SCUpgradeFailReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::cpu1.data      1154966                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadExReq_accesses::total      1154966                       # number of ReadExReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst      5903388                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadCleanReq_accesses::total      5903388                       # number of ReadCleanReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data      3834949                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.ReadSharedReq_accesses::total      3834949                       # number of ReadSharedReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data       458323                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.InvalidateReq_accesses::total       458323                       # number of InvalidateReq accesses(hits+misses)
system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker       583805                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.itb.walker       197931                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.inst      5903388                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::cpu1.data      4989915                       # number of demand (read+write) accesses
system.cpu1.l2cache.demand_accesses::total     11675039                       # number of demand (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker       583805                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.itb.walker       197931                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.inst      5903388                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::cpu1.data      4989915                       # number of overall (read+write) accesses
system.cpu1.l2cache.overall_accesses::total     11675039                       # number of overall (read+write) accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker     0.035265                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker     0.049568                       # miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_miss_rate::total     0.038887                       # miss rate for ReadReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data     0.999839                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total     0.999839                       # miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data     0.999995                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_miss_rate::total     0.999995                       # miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total            1                       # miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data     0.222629                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_miss_rate::total     0.222629                       # miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst     0.094846                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_miss_rate::total     0.094846                       # miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data     0.252673                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_miss_rate::total     0.252673                       # miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data     0.563151                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_miss_rate::total     0.563151                       # miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker     0.035265                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker     0.049568                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.inst     0.094846                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::cpu1.data     0.245719                       # miss rate for demand accesses
system.cpu1.l2cache.demand_miss_rate::total     0.155582                       # miss rate for demand accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker     0.035265                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker     0.049568                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.inst     0.094846                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::cpu1.data     0.245719                       # miss rate for overall accesses
system.cpu1.l2cache.overall_miss_rate::total     0.155582                       # miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32924.130561                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37190.959128                       # average ReadReq miss latency
system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34301.210566                       # average ReadReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data  4272.033714                       # average UpgradeReq miss latency
system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total  4272.033714                       # average UpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data  1412.896616                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total  1412.896616                       # average SCUpgradeReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data       709875                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total       709875                       # average SCUpgradeFailReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48739.193129                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48739.193129                       # average ReadExReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36741.268302                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36741.268302                       # average ReadCleanReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37216.101433                       # average ReadSharedReq miss latency
system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37216.101433                       # average ReadSharedReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data  1318.800488                       # average InvalidateReq miss latency
system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total  1318.800488                       # average InvalidateReq miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32924.130561                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37190.959128                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36741.268302                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39632.611000                       # average overall miss latency
system.cpu1.l2cache.demand_avg_miss_latency::total 38652.130895                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32924.130561                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37190.959128                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36741.268302                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39632.611000                       # average overall miss latency
system.cpu1.l2cache.overall_avg_miss_latency::total 38652.130895                       # average overall miss latency
system.cpu1.l2cache.blocked_cycles::no_mshrs          308                       # number of cycles access was blocked
system.cpu1.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_mshrs              11                       # number of cycles access was blocked
system.cpu1.l2cache.blocked::no_targets             0                       # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_mshrs           28                       # average number of cycles each access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu1.l2cache.unused_prefetches           42085                       # number of HardPF blocks evicted w/o reference
system.cpu1.l2cache.writebacks::writebacks      1170856                       # number of writebacks
system.cpu1.l2cache.writebacks::total         1170856                       # number of writebacks
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker           68                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker          195                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadReq_mshr_hits::total          263                       # number of ReadReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data        13529                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadExReq_mshr_hits::total        13529                       # number of ReadExReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst            3                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadCleanReq_mshr_hits::total            3                       # number of ReadCleanReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data         4671                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.ReadSharedReq_mshr_hits::total         4671                       # number of ReadSharedReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data            5                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.InvalidateReq_mshr_hits::total            5                       # number of InvalidateReq MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker           68                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker          195                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.inst            3                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::cpu1.data        18200                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.demand_mshr_hits::total        18466                       # number of demand (read+write) MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker           68                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker          195                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.inst            3                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::cpu1.data        18200                       # number of overall MSHR hits
system.cpu1.l2cache.overall_mshr_hits::total        18466                       # number of overall MSHR hits
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker        20520                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker         9616                       # number of ReadReq MSHR misses
system.cpu1.l2cache.ReadReq_mshr_misses::total        30136                       # number of ReadReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher       763352                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.HardPFReq_mshr_misses::total       763352                       # number of HardPFReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data       230170                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.UpgradeReq_mshr_misses::total       230170                       # number of UpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data       192283                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total       192283                       # number of SCUpgradeReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total            4                       # number of SCUpgradeFailReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data       243600                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadExReq_mshr_misses::total       243600                       # number of ReadExReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst       559911                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadCleanReq_mshr_misses::total       559911                       # number of ReadCleanReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data       964316                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.ReadSharedReq_mshr_misses::total       964316                       # number of ReadSharedReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data       258100                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.InvalidateReq_mshr_misses::total       258100                       # number of InvalidateReq MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker        20520                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker         9616                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.inst       559911                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::cpu1.data      1207916                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.demand_mshr_misses::total      1797963                       # number of demand (read+write) MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker        20520                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker         9616                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.inst       559911                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.data      1207916                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher       763352                       # number of overall MSHR misses
system.cpu1.l2cache.overall_mshr_misses::total      2561315                       # number of overall MSHR misses
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data        21291                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.ReadReq_mshr_uncacheable::total        21358                       # number of ReadReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data        19410                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.WriteReq_mshr_uncacheable::total        19410                       # number of WriteReq MSHR uncacheable
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data        40701                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.overall_mshr_uncacheable_misses::total        40768                       # number of overall MSHR uncacheable misses
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker    553404000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker    304119000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_miss_latency::total    857523000                       # number of ReadReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher  42319154022                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total  42319154022                       # number of HardPFReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data   4307815491                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total   4307815491                       # number of UpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data   2930523994                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total   2930523994                       # number of SCUpgradeReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data      2407500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total      2407500                       # number of SCUpgradeFailReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data   8988147495                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total   8988147495                       # number of ReadExReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst  17212365000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total  17212365000                       # number of ReadCleanReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data  29935787486                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total  29935787486                       # number of ReadSharedReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data   6963364497                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total   6963364497                       # number of InvalidateReq MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker    553404000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker    304119000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst  17212365000                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data  38923934981                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.demand_mshr_miss_latency::total  56993822981                       # number of demand (read+write) MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker    553404000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker    304119000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst  17212365000                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data  38923934981                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  42319154022                       # number of overall MSHR miss cycles
system.cpu1.l2cache.overall_mshr_miss_latency::total  99312977003                       # number of overall MSHR miss cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst      6576000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data   3627092000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total   3633668000                       # number of ReadReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst      6576000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data   3627092000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::total   3633668000                       # number of overall MSHR uncacheable cycles
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.035149                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.048583                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.ReadReq_mshr_miss_rate::total     0.038550                       # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data     0.999839                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total     0.999839                       # mshr miss rate for UpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.999995                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total     0.999995                       # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data     0.210915                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total     0.210915                       # mshr miss rate for ReadExReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst     0.094846                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total     0.094846                       # mshr miss rate for ReadCleanReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data     0.251455                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total     0.251455                       # mshr miss rate for ReadSharedReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data     0.563140                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total     0.563140                       # mshr miss rate for InvalidateReq accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker     0.035149                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker     0.048583                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst     0.094846                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data     0.242071                       # mshr miss rate for demand accesses
system.cpu1.l2cache.demand_mshr_miss_rate::total     0.154001                       # mshr miss rate for demand accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker     0.035149                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker     0.048583                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst     0.094846                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data     0.242071                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::total     0.219384                       # mshr miss rate for overall accesses
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913                       # average ReadReq mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28455.103531                       # average ReadReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55438.584063                       # average HardPFReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18715.799153                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18715.799153                       # average UpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15240.681672                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15240.681672                       # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data       601875                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total       601875                       # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36897.157204                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36897.157204                       # average ReadExReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30741.251735                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30741.251735                       # average ReadCleanReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31043.545359                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31043.545359                       # average ReadSharedReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26979.327768                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26979.327768                       # average InvalidateReq mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30741.251735                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32224.041226                       # average overall mshr miss latency
system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31699.107813                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30741.251735                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32224.041226                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063                       # average overall mshr miss latency
system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38774.214418                       # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170357.991640                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170131.472984                       # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 89115.549986                       # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 89130.396389                       # average overall mshr uncacheable latency
system.cpu1.toL2Bus.snoop_filter.tot_requests     23401917                       # Total number of requests made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_requests     12050394                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_requests         1685                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.snoop_filter.tot_snoops       583324                       # Total number of snoops made to the snoop filter.
system.cpu1.toL2Bus.snoop_filter.hit_single_snoops       583320                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops            4                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.cpu1.toL2Bus.trans_dist::ReadReq        895492                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp     10720388                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate            2                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq        19410                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp        19410                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackDirty      4582624                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WritebackClean      7861129                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::CleanEvict      1298468                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFReq       967756                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::HardPFResp           11                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeReq       436519                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeReq       348532                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeResp       480708                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq           65                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq      1183332                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp      1160512                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadCleanReq      5903405                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadSharedReq      4845353                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateReq       522418                       # Transaction distribution
system.cpu1.toL2Bus.trans_dist::InvalidateResp       458323                       # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side     17709789                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side     17335665                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side       416038                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      1239832                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count::total         36701324                       # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side    755601072                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side    668583302                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side      1583448                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side      4670440                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size::total        1430438262                       # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.snoops                    5153113                       # Total snoops (count)
system.cpu1.toL2Bus.snoopTraffic             82064432                       # Total snoop traffic (bytes)
system.cpu1.toL2Bus.snoop_fanout::samples     17599300                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::mean       0.053842                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::stdev      0.225707                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0          16651717     94.62%     94.62% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1            947579      5.38%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2                 4      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::total      17599300                       # Request fanout histogram
system.cpu1.toL2Bus.reqLayer0.occupancy   23252082447                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.snoopLayer0.occupancy    167523282                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer0.occupancy   8861086123                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer1.occupancy   7965231666                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer2.occupancy    218506693                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization          0.0                       # Layer utilization (%)
system.cpu1.toL2Bus.respLayer3.occupancy    656902733                       # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization          0.0                       # Layer utilization (%)
system.iobus.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.iobus.trans_dist::ReadReq                40332                       # Transaction distribution
system.iobus.trans_dist::ReadResp               40332                       # Transaction distribution
system.iobus.trans_dist::WriteReq              136631                       # Transaction distribution
system.iobus.trans_dist::WriteResp             136631                       # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio        47650                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio           14                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio          434                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio           24                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio           16                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio        29600                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio        44750                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total       122584                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side       231262                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ide.dma::total       231262                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total           80                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total                  353926                       # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio        47670                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio           28                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio          634                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio           48                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio           32                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio        17587                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio        89500                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total       155691                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side      7339064                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total      7339064                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total         2086                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total                  7496841                       # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy             36933004                       # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer1.occupancy                 9500                       # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer2.occupancy               324000                       # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer3.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer4.occupancy                10500                       # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization                0.0                       # Layer utilization (%)
system.iobus.reqLayer10.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer13.occupancy               10000                       # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer14.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer15.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer16.occupancy               13000                       # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer17.occupancy               10500                       # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer23.occupancy            24511500                       # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer24.occupancy            36406001                       # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization               0.0                       # Layer utilization (%)
system.iobus.reqLayer25.occupancy           569333352                       # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer0.occupancy            92684000                       # Layer occupancy (ticks)
system.iobus.respLayer0.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer3.occupancy           147958000                       # Layer occupancy (ticks)
system.iobus.respLayer3.utilization               0.0                       # Layer utilization (%)
system.iobus.respLayer4.occupancy              170000                       # Layer occupancy (ticks)
system.iobus.respLayer4.utilization               0.0                       # Layer utilization (%)
system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.iocache.tags.replacements               115627                       # number of replacements
system.iocache.tags.tagsinuse               11.209625                       # Cycle average of tags in use
system.iocache.tags.total_refs                      3                       # Total number of references to valid blocks.
system.iocache.tags.sampled_refs               115643                       # Sample count of references to valid blocks.
system.iocache.tags.avg_refs                 0.000026                       # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle         9156281985000                       # Cycle when the warmup percentage was hit.
system.iocache.tags.occ_blocks::realview.ethernet     7.417323                       # Average occupied blocks per requestor
system.iocache.tags.occ_blocks::realview.ide     3.792302                       # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ethernet     0.463583                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::realview.ide     0.237019                       # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total       0.700602                       # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023           16                       # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3           16                       # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023            1                       # Percentage of cache occupancy per task id
system.iocache.tags.tag_accesses              1041036                       # Number of tag accesses
system.iocache.tags.data_accesses             1041036                       # Number of data accesses
system.iocache.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.iocache.ReadReq_misses::realview.ethernet           37                       # number of ReadReq misses
system.iocache.ReadReq_misses::realview.ide         8903                       # number of ReadReq misses
system.iocache.ReadReq_misses::total             8940                       # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet            3                       # number of WriteReq misses
system.iocache.WriteReq_misses::total               3                       # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide       106728                       # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total       106728                       # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet           40                       # number of demand (read+write) misses
system.iocache.demand_misses::realview.ide       115631                       # number of demand (read+write) misses
system.iocache.demand_misses::total            115671                       # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet           40                       # number of overall misses
system.iocache.overall_misses::realview.ide       115631                       # number of overall misses
system.iocache.overall_misses::total           115671                       # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ethernet      5200000                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::realview.ide   1786499757                       # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total   1791699757                       # number of ReadReq miss cycles
system.iocache.WriteReq_miss_latency::realview.ethernet       369000                       # number of WriteReq miss cycles
system.iocache.WriteReq_miss_latency::total       369000                       # number of WriteReq miss cycles
system.iocache.WriteLineReq_miss_latency::realview.ide  13185420595                       # number of WriteLineReq miss cycles
system.iocache.WriteLineReq_miss_latency::total  13185420595                       # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ethernet      5569000                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::realview.ide  14971920352                       # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total  14977489352                       # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ethernet      5569000                       # number of overall miss cycles
system.iocache.overall_miss_latency::realview.ide  14971920352                       # number of overall miss cycles
system.iocache.overall_miss_latency::total  14977489352                       # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet           37                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::realview.ide         8903                       # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total           8940                       # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet            3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total             3                       # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total       106728                       # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet           40                       # number of demand (read+write) accesses
system.iocache.demand_accesses::realview.ide       115631                       # number of demand (read+write) accesses
system.iocache.demand_accesses::total          115671                       # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet           40                       # number of overall (read+write) accesses
system.iocache.overall_accesses::realview.ide       115631                       # number of overall (read+write) accesses
system.iocache.overall_accesses::total         115671                       # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide            1                       # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total             1                       # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::realview.ethernet            1                       # miss rate for WriteReq accesses
system.iocache.WriteReq_miss_rate::total            1                       # miss rate for WriteReq accesses
system.iocache.WriteLineReq_miss_rate::realview.ide            1                       # miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_miss_rate::total            1                       # miss rate for WriteLineReq accesses
system.iocache.demand_miss_rate::realview.ethernet            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::realview.ide            1                       # miss rate for demand accesses
system.iocache.demand_miss_rate::total              1                       # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ethernet            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide            1                       # miss rate for overall accesses
system.iocache.overall_miss_rate::total             1                       # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::realview.ide 200662.670673                       # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 200413.843065                       # average ReadReq miss latency
system.iocache.WriteReq_avg_miss_latency::realview.ethernet       123000                       # average WriteReq miss latency
system.iocache.WriteReq_avg_miss_latency::total       123000                       # average WriteReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123542.281266                       # average WriteLineReq miss latency
system.iocache.WriteLineReq_avg_miss_latency::total 123542.281266                       # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ethernet       139225                       # average overall miss latency
system.iocache.demand_avg_miss_latency::realview.ide 129480.159750                       # average overall miss latency
system.iocache.demand_avg_miss_latency::total 129483.529597                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ethernet       139225                       # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 129480.159750                       # average overall miss latency
system.iocache.overall_avg_miss_latency::total 129483.529597                       # average overall miss latency
system.iocache.blocked_cycles::no_mshrs         39692                       # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.iocache.blocked::no_mshrs                 3537                       # number of cycles access was blocked
system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs    11.221939                       # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.iocache.writebacks::writebacks          106694                       # number of writebacks
system.iocache.writebacks::total               106694                       # number of writebacks
system.iocache.ReadReq_mshr_misses::realview.ethernet           37                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::realview.ide         8903                       # number of ReadReq MSHR misses
system.iocache.ReadReq_mshr_misses::total         8940                       # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::realview.ethernet            3                       # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total            3                       # number of WriteReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::realview.ide       106728                       # number of WriteLineReq MSHR misses
system.iocache.WriteLineReq_mshr_misses::total       106728                       # number of WriteLineReq MSHR misses
system.iocache.demand_mshr_misses::realview.ethernet           40                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::realview.ide       115631                       # number of demand (read+write) MSHR misses
system.iocache.demand_mshr_misses::total       115671                       # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ethernet           40                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::realview.ide       115631                       # number of overall MSHR misses
system.iocache.overall_mshr_misses::total       115671                       # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ethernet      3350000                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::realview.ide   1341349757                       # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total   1344699757                       # number of ReadReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::realview.ethernet       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteReq_mshr_miss_latency::total       219000                       # number of WriteReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::realview.ide   7839860905                       # number of WriteLineReq MSHR miss cycles
system.iocache.WriteLineReq_mshr_miss_latency::total   7839860905                       # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ethernet      3569000                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide   9181210662                       # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total   9184779662                       # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ethernet      3569000                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide   9181210662                       # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_latency::total   9184779662                       # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::realview.ide            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.WriteLineReq_mshr_miss_rate::total            1                       # mshr miss rate for WriteLineReq accesses
system.iocache.demand_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::realview.ide            1                       # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total            1                       # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ethernet            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::realview.ide            1                       # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total            1                       # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150662.670673                       # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 150413.843065                       # average ReadReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet        73000                       # average WriteReq mshr miss latency
system.iocache.WriteReq_avg_mshr_miss_latency::total        73000                       # average WriteReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73456.458521                       # average WriteLineReq mshr miss latency
system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73456.458521                       # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ethernet        89225                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 79400.944920                       # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 79404.342160                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ethernet        89225                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 79400.944920                       # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 79404.342160                       # average overall mshr miss latency
system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.l2c.tags.replacements                  1712520                       # number of replacements
system.l2c.tags.tagsinuse                65207.555116                       # Cycle average of tags in use
system.l2c.tags.total_refs                    7020190                       # Total number of references to valid blocks.
system.l2c.tags.sampled_refs                  1774780                       # Sample count of references to valid blocks.
system.l2c.tags.avg_refs                     3.955527                       # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle               3083323500                       # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks   10815.100932                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker   305.602667                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker   366.195320                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst     3964.024216                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data    19638.791484                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14261.868883                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker   151.853339                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.itb.walker   181.379081                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst     3223.101636                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data     5938.767305                       # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher  6360.870252                       # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks      0.165025                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker     0.004663                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker     0.005588                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst       0.060486                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data       0.299664                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher     0.217619                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker     0.002317                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.itb.walker     0.002768                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst       0.049181                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data       0.090618                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher     0.097059                       # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total           0.994988                       # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1022        11498                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1023          249                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024        50513                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::1            1                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::2         1395                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::3          577                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1022::4         9525                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2            3                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4          246                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1          271                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2         2497                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3         4893                       # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4        42814                       # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1022     0.175446                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1023     0.003799                       # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024     0.770767                       # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses                 80570058                       # Number of tag accesses
system.l2c.tags.data_accesses                80570058                       # Number of data accesses
system.l2c.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.l2c.WritebackDirty_hits::writebacks      2973062                       # number of WritebackDirty hits
system.l2c.WritebackDirty_hits::total         2973062                       # number of WritebackDirty hits
system.l2c.UpgradeReq_hits::cpu0.data          212913                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data          179277                       # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total              392190                       # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu0.data         55777                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu1.data         49656                       # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total            105433                       # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data            53324                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data            56619                       # number of ReadExReq hits
system.l2c.ReadExReq_hits::total               109943                       # number of ReadExReq hits
system.l2c.ReadSharedReq_hits::cpu0.dtb.walker        12274                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.itb.walker         4633                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.inst       532793                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.data       642111                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher       285366                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.dtb.walker        12502                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.itb.walker         5292                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.inst       506134                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.data       588825                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher       298655                       # number of ReadSharedReq hits
system.l2c.ReadSharedReq_hits::total          2888585                       # number of ReadSharedReq hits
system.l2c.InvalidateReq_hits::cpu0.data       133712                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::cpu1.data       132940                       # number of InvalidateReq hits
system.l2c.InvalidateReq_hits::total           266652                       # number of InvalidateReq hits
system.l2c.demand_hits::cpu0.dtb.walker         12274                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker          4633                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst              532793                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data              695435                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.l2cache.prefetcher       285366                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker         12502                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker          5292                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst              506134                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data              645444                       # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.l2cache.prefetcher       298655                       # number of demand (read+write) hits
system.l2c.demand_hits::total                 2998528                       # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker        12274                       # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker         4633                       # number of overall hits
system.l2c.overall_hits::cpu0.inst             532793                       # number of overall hits
system.l2c.overall_hits::cpu0.data             695435                       # number of overall hits
system.l2c.overall_hits::cpu0.l2cache.prefetcher       285366                       # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker        12502                       # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker         5292                       # number of overall hits
system.l2c.overall_hits::cpu1.inst             506134                       # number of overall hits
system.l2c.overall_hits::cpu1.data             645444                       # number of overall hits
system.l2c.overall_hits::cpu1.l2cache.prefetcher       298655                       # number of overall hits
system.l2c.overall_hits::total                2998528                       # number of overall hits
system.l2c.UpgradeReq_misses::cpu0.data         25668                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data         25681                       # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total             51349                       # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu0.data          646                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu1.data          809                       # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total            1455                       # number of SCUpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data          94289                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data          48061                       # number of ReadExReq misses
system.l2c.ReadExReq_misses::total             142350                       # number of ReadExReq misses
system.l2c.ReadSharedReq_misses::cpu0.dtb.walker         3531                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.itb.walker         3298                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.inst        60576                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.data       185593                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher       348444                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.dtb.walker         2063                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.itb.walker         1546                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.inst        53773                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.data       117277                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher       240910                       # number of ReadSharedReq misses
system.l2c.ReadSharedReq_misses::total        1017011                       # number of ReadSharedReq misses
system.l2c.InvalidateReq_misses::cpu0.data       478287                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::cpu1.data       112149                       # number of InvalidateReq misses
system.l2c.InvalidateReq_misses::total         590436                       # number of InvalidateReq misses
system.l2c.demand_misses::cpu0.dtb.walker         3531                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker         3298                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst             60576                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data            279882                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.l2cache.prefetcher       348444                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker         2063                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.itb.walker         1546                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst             53773                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data            165338                       # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.l2cache.prefetcher       240910                       # number of demand (read+write) misses
system.l2c.demand_misses::total               1159361                       # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker         3531                       # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker         3298                       # number of overall misses
system.l2c.overall_misses::cpu0.inst            60576                       # number of overall misses
system.l2c.overall_misses::cpu0.data           279882                       # number of overall misses
system.l2c.overall_misses::cpu0.l2cache.prefetcher       348444                       # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker         2063                       # number of overall misses
system.l2c.overall_misses::cpu1.itb.walker         1546                       # number of overall misses
system.l2c.overall_misses::cpu1.inst            53773                       # number of overall misses
system.l2c.overall_misses::cpu1.data           165338                       # number of overall misses
system.l2c.overall_misses::cpu1.l2cache.prefetcher       240910                       # number of overall misses
system.l2c.overall_misses::total              1159361                       # number of overall misses
system.l2c.UpgradeReq_miss_latency::cpu0.data    172222000                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data    155225500                       # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total    327447500                       # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu0.data      9175000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu1.data      5803000                       # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total     14978000                       # number of SCUpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu0.data  10233917991                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data   5260660499                       # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total  15494578490                       # number of ReadExReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker    356299000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker    337167500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.inst   6654556500                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.data  20784674000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher  53218202875                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker    218154000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker    160424000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.inst   6046329000                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.data  13882177499                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher  36908535986                       # number of ReadSharedReq miss cycles
system.l2c.ReadSharedReq_miss_latency::total 138566520360                       # number of ReadSharedReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu0.data     31590000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::cpu1.data     32968000                       # number of InvalidateReq miss cycles
system.l2c.InvalidateReq_miss_latency::total     64558000                       # number of InvalidateReq miss cycles
system.l2c.demand_miss_latency::cpu0.dtb.walker    356299000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.itb.walker    337167500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.inst   6654556500                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.data  31018591991                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher  53218202875                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker    218154000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.itb.walker    160424000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst   6046329000                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data  19142837998                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher  36908535986                       # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total    154061098850                       # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu0.dtb.walker    356299000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.itb.walker    337167500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.inst   6654556500                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.data  31018591991                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher  53218202875                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker    218154000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.itb.walker    160424000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst   6046329000                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data  19142837998                       # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher  36908535986                       # number of overall miss cycles
system.l2c.overall_miss_latency::total   154061098850                       # number of overall miss cycles
system.l2c.WritebackDirty_accesses::writebacks      2973062                       # number of WritebackDirty accesses(hits+misses)
system.l2c.WritebackDirty_accesses::total      2973062                       # number of WritebackDirty accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data       238581                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data       204958                       # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total          443539                       # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu0.data        56423                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu1.data        50465                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total        106888                       # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data       147613                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data       104680                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total           252293                       # number of ReadExReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker        15805                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.itb.walker         7931                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.inst       593369                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.data       827704                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher       633810                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker        14565                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.itb.walker         6838                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.inst       559907                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.data       706102                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher       539565                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.ReadSharedReq_accesses::total      3905596                       # number of ReadSharedReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu0.data       611999                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::cpu1.data       245089                       # number of InvalidateReq accesses(hits+misses)
system.l2c.InvalidateReq_accesses::total       857088                       # number of InvalidateReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker        15805                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker         7931                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst          593369                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data          975317                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.l2cache.prefetcher       633810                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker        14565                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker         6838                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst          559907                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data          810782                       # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.l2cache.prefetcher       539565                       # number of demand (read+write) accesses
system.l2c.demand_accesses::total             4157889                       # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker        15805                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker         7931                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst         593369                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data         975317                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.l2cache.prefetcher       633810                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker        14565                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker         6838                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst         559907                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data         810782                       # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.l2cache.prefetcher       539565                       # number of overall (read+write) accesses
system.l2c.overall_accesses::total            4157889                       # number of overall (read+write) accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data     0.107586                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data     0.125299                       # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total       0.115771                       # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.011449                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.016031                       # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total     0.013612                       # miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data     0.638758                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data     0.459123                       # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total        0.564225                       # miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker     0.223410                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker     0.415837                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.inst     0.102088                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.data     0.224226                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker     0.141641                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker     0.226089                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.inst     0.096039                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.data     0.166091                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_miss_rate::total     0.260398                       # miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_miss_rate::cpu0.data     0.781516                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::cpu1.data     0.457585                       # miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_miss_rate::total     0.688886                       # miss rate for InvalidateReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker     0.223410                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker     0.415837                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst       0.102088                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data       0.286965                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker     0.141641                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.itb.walker     0.226089                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst       0.096039                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data       0.203924                       # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # miss rate for demand accesses
system.l2c.demand_miss_rate::total           0.278834                       # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker     0.223410                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker     0.415837                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst      0.102088                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data      0.286965                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker     0.141641                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.itb.walker     0.226089                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst      0.096039                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data      0.203924                       # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # miss rate for overall accesses
system.l2c.overall_miss_rate::total          0.278834                       # miss rate for overall accesses
system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  6709.599501                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  6044.371325                       # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total  6376.901205                       # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14202.786378                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  7173.053152                       # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 10294.158076                       # average SCUpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108537.772073                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109457.990866                       # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 108848.461468                       # average ReadExReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100905.975644                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 102233.929654                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109854.670166                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111990.613870                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 105746.000969                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103767.141009                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112441.727261                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 118370.844232                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585                       # average ReadSharedReq miss latency
system.l2c.ReadSharedReq_avg_miss_latency::total 136248.792157                       # average ReadSharedReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu0.data    66.048210                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::cpu1.data   293.966063                       # average InvalidateReq miss latency
system.l2c.InvalidateReq_avg_miss_latency::total   109.339539                       # average InvalidateReq miss latency
system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100905.975644                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.itb.walker 102233.929654                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.inst 109854.670166                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.data 110827.391511                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 105746.000969                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103767.141009                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 112441.727261                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 115780.026358                       # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585                       # average overall miss latency
system.l2c.demand_avg_miss_latency::total 132884.493139                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100905.975644                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.itb.walker 102233.929654                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.inst 109854.670166                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.data 110827.391511                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 105746.000969                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103767.141009                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 112441.727261                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 115780.026358                       # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585                       # average overall miss latency
system.l2c.overall_avg_miss_latency::total 132884.493139                       # average overall miss latency
system.l2c.blocked_cycles::no_mshrs             11042                       # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
system.l2c.blocked::no_mshrs                      109                       # number of cycles access was blocked
system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs    101.302752                       # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2c.writebacks::writebacks             1306567                       # number of writebacks
system.l2c.writebacks::total                  1306567                       # number of writebacks
system.l2c.ReadSharedReq_mshr_hits::cpu0.inst           94                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu0.data           23                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.inst          174                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu1.data           24                       # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::total          315                       # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu0.inst             94                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu0.data             23                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.inst            174                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu1.data             24                       # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total                315                       # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu0.inst            94                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu0.data            23                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.inst           174                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu1.data            24                       # number of overall MSHR hits
system.l2c.overall_mshr_hits::total               315                       # number of overall MSHR hits
system.l2c.CleanEvict_mshr_misses::writebacks        73117                       # number of CleanEvict MSHR misses
system.l2c.CleanEvict_mshr_misses::total        73117                       # number of CleanEvict MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu0.data        25668                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data        25681                       # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total        51349                       # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          646                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          809                       # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total         1455                       # number of SCUpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu0.data        94289                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data        48061                       # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total        142350                       # number of ReadExReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker         3531                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker         3298                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.inst        60482                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.data       185570                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher       348444                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker         2063                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker         1546                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.inst        53599                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.data       117253                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher       240910                       # number of ReadSharedReq MSHR misses
system.l2c.ReadSharedReq_mshr_misses::total      1016696                       # number of ReadSharedReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu0.data       478287                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::cpu1.data       112149                       # number of InvalidateReq MSHR misses
system.l2c.InvalidateReq_mshr_misses::total       590436                       # number of InvalidateReq MSHR misses
system.l2c.demand_mshr_misses::cpu0.dtb.walker         3531                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.itb.walker         3298                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.inst        60482                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.data       279859                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher       348444                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker         2063                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.itb.walker         1546                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst        53599                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data       165314                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher       240910                       # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total          1159046                       # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu0.dtb.walker         3531                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.itb.walker         3298                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.inst        60482                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.data       279859                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher       348444                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker         2063                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.itb.walker         1546                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst        53599                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data       165314                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher       240910                       # number of overall MSHR misses
system.l2c.overall_mshr_misses::total         1159046                       # number of overall MSHR misses
system.l2c.ReadReq_mshr_uncacheable::cpu0.inst        21293                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu0.data        16980                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.inst           67                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::cpu1.data        21289                       # number of ReadReq MSHR uncacheable
system.l2c.ReadReq_mshr_uncacheable::total        59629                       # number of ReadReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu0.data        18801                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::cpu1.data        19410                       # number of WriteReq MSHR uncacheable
system.l2c.WriteReq_mshr_uncacheable::total        38211                       # number of WriteReq MSHR uncacheable
system.l2c.overall_mshr_uncacheable_misses::cpu0.inst        21293                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu0.data        35781                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.inst           67                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::cpu1.data        40699                       # number of overall MSHR uncacheable misses
system.l2c.overall_mshr_uncacheable_misses::total        97840                       # number of overall MSHR uncacheable misses
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    520949500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    534002500                       # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total   1054952000                       # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     15625500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     19999000                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total     35624500                       # number of SCUpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   9290880791                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   4779832460                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total  14070713251                       # number of ReadExReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker    320987004                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker    304187500                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst   6041672064                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data  18926430190                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher  49733607723                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker    197523002                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker    144964000                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst   5494647043                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data  12706523221                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher  34499199531                       # number of ReadSharedReq MSHR miss cycles
system.l2c.ReadSharedReq_mshr_miss_latency::total 128369741278                       # number of ReadSharedReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data  11811554063                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data   2326727500                       # number of InvalidateReq MSHR miss cycles
system.l2c.InvalidateReq_mshr_miss_latency::total  14138281563                       # number of InvalidateReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker    320987004                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.itb.walker    304187500                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.inst   6041672064                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.data  28217310981                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher  49733607723                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker    197523002                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.itb.walker    144964000                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst   5494647043                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data  17486355681                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher  34499199531                       # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 142440454529                       # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker    320987004                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.itb.walker    304187500                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.inst   6041672064                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.data  28217310981                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher  49733607723                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker    197523002                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.itb.walker    144964000                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst   5494647043                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data  17486355681                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher  34499199531                       # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 142440454529                       # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst   1484185500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   2691376000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      5368000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   3243740000                       # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total   7424669500                       # number of ReadReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.inst   1484185500                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu0.data   2691376000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      5368000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data   3243740000                       # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total   7424669500                       # number of overall MSHR uncacheable cycles
system.l2c.CleanEvict_mshr_miss_rate::writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.107586                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.125299                       # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total     0.115771                       # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.011449                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.016031                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total     0.013612                       # mshr miss rate for SCUpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.638758                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.459123                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total     0.564225                       # mshr miss rate for ReadExReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker     0.223410                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker     0.415837                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst     0.101930                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data     0.224199                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker     0.141641                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker     0.226089                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst     0.095728                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data     0.166057                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # mshr miss rate for ReadSharedReq accesses
system.l2c.ReadSharedReq_mshr_miss_rate::total     0.260318                       # mshr miss rate for ReadSharedReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data     0.781516                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data     0.457585                       # mshr miss rate for InvalidateReq accesses
system.l2c.InvalidateReq_mshr_miss_rate::total     0.688886                       # mshr miss rate for InvalidateReq accesses
system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.223410                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.415837                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.inst     0.101930                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.data     0.286942                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.141641                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.226089                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst     0.095728                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data     0.203895                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total      0.278758                       # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.223410                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.415837                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.inst     0.101930                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.data     0.286942                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher     0.549761                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.141641                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.226089                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst     0.095728                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data     0.203895                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher     0.446489                       # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total     0.278758                       # mshr miss rate for overall accesses
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20295.679445                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20793.680153                       # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20544.742838                       # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24188.080495                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24720.642769                       # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24484.192440                       # average SCUpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98536.210915                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99453.454152                       # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 98845.895687                       # average ReadExReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99892.068119                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101990.786172                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102513.984272                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108368.427426                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077                       # average ReadSharedReq mshr miss latency
system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126261.676330                       # average ReadSharedReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24695.536494                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20746.752089                       # average InvalidateReq mshr miss latency
system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23945.493776                       # average InvalidateReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99892.068119                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100826.884185                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102513.984272                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105776.617110                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077                       # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 122894.565469                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99892.068119                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100826.884185                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102513.984272                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105776.617110                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077                       # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 122894.565469                       # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158502.709069                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152366.950068                       # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124514.405742                       # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75218.020737                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 79700.729748                       # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total 75885.828904                       # average overall mshr uncacheable latency
system.membus.snoop_filter.tot_requests       4262418                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.hit_single_requests      2509154                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_requests         3063                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadReq               59629                       # Transaction distribution
system.membus.trans_dist::ReadResp            1085265                       # Transaction distribution
system.membus.trans_dist::WriteReq              38211                       # Transaction distribution
system.membus.trans_dist::WriteResp             38211                       # Transaction distribution
system.membus.trans_dist::WritebackDirty      1413261                       # Transaction distribution
system.membus.trans_dist::CleanEvict           284296                       # Transaction distribution
system.membus.trans_dist::UpgradeReq           353595                       # Transaction distribution
system.membus.trans_dist::SCUpgradeReq         284030                       # Transaction distribution
system.membus.trans_dist::UpgradeResp              23                       # Transaction distribution
system.membus.trans_dist::ReadExReq            155418                       # Transaction distribution
system.membus.trans_dist::ReadExResp           141619                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq       1025636                       # Transaction distribution
system.membus.trans_dist::InvalidateReq        695069                       # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave       122584                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port           76                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio        25156                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port      5185454                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total      5333270                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port       238137                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total       238137                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                5571407                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave       155691                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port          556                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio        50312                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port    158067712                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::total    158274271                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port      7266112                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total      7266112                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total               165540383                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                           598647                       # Total snoops (count)
system.membus.snoopTraffic                     181312                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples           2611590                       # Request fanout histogram
system.membus.snoop_fanout::mean             0.013385                       # Request fanout histogram
system.membus.snoop_fanout::stdev            0.114916                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                 2576634     98.66%     98.66% # Request fanout histogram
system.membus.snoop_fanout::1                   34956      1.34%    100.00% # Request fanout histogram
system.membus.snoop_fanout::2                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               1                       # Request fanout histogram
system.membus.snoop_fanout::total             2611590                       # Request fanout histogram
system.membus.reqLayer0.occupancy            98274995                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer1.occupancy               52000                       # Layer occupancy (ticks)
system.membus.reqLayer1.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer2.occupancy            20993495                       # Layer occupancy (ticks)
system.membus.reqLayer2.utilization               0.0                       # Layer utilization (%)
system.membus.reqLayer5.occupancy          9731390131                       # Layer occupancy (ticks)
system.membus.reqLayer5.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer2.occupancy         6232103011                       # Layer occupancy (ticks)
system.membus.respLayer2.utilization              0.0                       # Layer utilization (%)
system.membus.respLayer3.occupancy           45620246                       # Layer occupancy (ticks)
system.membus.respLayer3.utilization              0.0                       # Layer utilization (%)
system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.dcc.osc_cpu.clock               16667                       # Clock period in ticks
system.realview.dcc.osc_ddr.clock               25000                       # Clock period in ticks
system.realview.dcc.osc_hsbm.clock              25000                       # Clock period in ticks
system.realview.dcc.osc_pxl.clock               42105                       # Clock period in ticks
system.realview.dcc.osc_smb.clock               20000                       # Clock period in ticks
system.realview.dcc.osc_sys.clock               16667                       # Clock period in ticks
system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.ethernet.txBytes                  966                       # Bytes Transmitted
system.realview.ethernet.txPackets                  3                       # Number of Packets Transmitted
system.realview.ethernet.txIpChecksums              0                       # Number of tx IP Checksums done by device
system.realview.ethernet.txTcpChecksums             0                       # Number of tx TCP Checksums done by device
system.realview.ethernet.txUdpChecksums             0                       # Number of tx UDP Checksums done by device
system.realview.ethernet.descDMAReads               0                       # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites              0                       # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.descDmaReadBytes            0                       # number of descriptor bytes read w/ DMA
system.realview.ethernet.descDmaWriteBytes            0                       # number of descriptor bytes write w/ DMA
system.realview.ethernet.totBandwidth             163                       # Total Bandwidth (bits/s)
system.realview.ethernet.totPackets                 3                       # Total Packets
system.realview.ethernet.totBytes                 966                       # Total Bytes
system.realview.ethernet.totPPS                     0                       # Total Tranmission Rate (packets/s)
system.realview.ethernet.txBandwidth              163                       # Transmit Bandwidth (bits/s)
system.realview.ethernet.txPPS                      0                       # Packet Tranmission Rate (packets/s)
system.realview.ethernet.postedSwi                  0                       # number of software interrupts posted to CPU
system.realview.ethernet.coalescedSwi               0                       # average number of Swi's coalesced into each post
system.realview.ethernet.totalSwi                   0                       # total number of Swi written to ISR
system.realview.ethernet.postedRxIdle               0                       # number of rxIdle interrupts posted to CPU
system.realview.ethernet.coalescedRxIdle            0                       # average number of RxIdle's coalesced into each post
system.realview.ethernet.totalRxIdle                0                       # total number of RxIdle written to ISR
system.realview.ethernet.postedRxOk                 0                       # number of RxOk interrupts posted to CPU
system.realview.ethernet.coalescedRxOk              0                       # average number of RxOk's coalesced into each post
system.realview.ethernet.totalRxOk                  0                       # total number of RxOk written to ISR
system.realview.ethernet.postedRxDesc               0                       # number of RxDesc interrupts posted to CPU
system.realview.ethernet.coalescedRxDesc            0                       # average number of RxDesc's coalesced into each post
system.realview.ethernet.totalRxDesc                0                       # total number of RxDesc written to ISR
system.realview.ethernet.postedTxOk                 0                       # number of TxOk interrupts posted to CPU
system.realview.ethernet.coalescedTxOk              0                       # average number of TxOk's coalesced into each post
system.realview.ethernet.totalTxOk                  0                       # total number of TxOk written to ISR
system.realview.ethernet.postedTxIdle               0                       # number of TxIdle interrupts posted to CPU
system.realview.ethernet.coalescedTxIdle            0                       # average number of TxIdle's coalesced into each post
system.realview.ethernet.totalTxIdle                0                       # total number of TxIdle written to ISR
system.realview.ethernet.postedTxDesc               0                       # number of TxDesc interrupts posted to CPU
system.realview.ethernet.coalescedTxDesc            0                       # average number of TxDesc's coalesced into each post
system.realview.ethernet.totalTxDesc                0                       # total number of TxDesc written to ISR
system.realview.ethernet.postedRxOrn                0                       # number of RxOrn posted to CPU
system.realview.ethernet.coalescedRxOrn             0                       # average number of RxOrn's coalesced into each post
system.realview.ethernet.totalRxOrn                 0                       # total number of RxOrn written to ISR
system.realview.ethernet.coalescedTotal             0                       # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts           13                       # number of posts to CPU
system.realview.ethernet.droppedPackets             0                       # number of packets dropped
system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.mcc.osc_clcd.clock              42105                       # Clock period in ticks
system.realview.mcc.osc_mcc.clock               20000                       # Clock period in ticks
system.realview.mcc.osc_peripheral.clock        41667                       # Clock period in ticks
system.realview.mcc.osc_system_bus.clock        41667                       # Clock period in ticks
system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.snoop_filter.tot_requests     12430379                       # Total number of requests made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_requests      6756092                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_requests      1976828                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.snoop_filter.tot_snoops         231635                       # Total number of snoops made to the snoop filter.
system.toL2Bus.snoop_filter.hit_single_snoops       213178                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.toL2Bus.snoop_filter.hit_multi_snoops        18457                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000                       # Cumulative time (in ticks) in various power states
system.toL2Bus.trans_dist::ReadReq              59631                       # Transaction distribution
system.toL2Bus.trans_dist::ReadResp           4752657                       # Transaction distribution
system.toL2Bus.trans_dist::WriteReq             38211                       # Transaction distribution
system.toL2Bus.trans_dist::WriteResp            38211                       # Transaction distribution
system.toL2Bus.trans_dist::WritebackDirty      4279629                       # Transaction distribution
system.toL2Bus.trans_dist::CleanEvict         2861492                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq          742959                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq        389463                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp        1132422                       # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeFailReq          133                       # Transaction distribution
system.toL2Bus.trans_dist::UpgradeFailResp          133                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq           304770                       # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp          304770                       # Transaction distribution
system.toL2Bus.trans_dist::ReadSharedReq      4693673                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq       888953                       # Transaction distribution
system.toL2Bus.trans_dist::InvalidateResp       857088                       # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side     10167135                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side      8009990                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total              18177125                       # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side    258318649                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side    198738470                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.pkt_size::total              457057119                       # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.snoops                         3168754                       # Total snoops (count)
system.toL2Bus.snoopTraffic                 137382864                       # Total snoop traffic (bytes)
system.toL2Bus.snoop_fanout::samples          8831298                       # Request fanout histogram
system.toL2Bus.snoop_fanout::mean            0.353414                       # Request fanout histogram
system.toL2Bus.snoop_fanout::stdev           0.482382                       # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0                5728650     64.87%     64.87% # Request fanout histogram
system.toL2Bus.snoop_fanout::1                3084191     34.92%     99.79% # Request fanout histogram
system.toL2Bus.snoop_fanout::2                  18457      0.21%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.toL2Bus.snoop_fanout::total            8831298                       # Request fanout histogram
system.toL2Bus.reqLayer0.occupancy         9716591105                       # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization              0.0                       # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy          2596400                       # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization            0.0                       # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy        4626263938                       # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization             0.0                       # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy        3958447661                       # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization             0.0                       # Layer utilization (%)
system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu0.kern.inst.quiesce                    5035                       # number of quiesce instructions executed
system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
system.cpu1.kern.inst.quiesce                   13834                       # number of quiesce instructions executed

---------- End Simulation Statistics   ----------