stats.txt revision 11680
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 47.384943 # Number of seconds simulated 4sim_ticks 47384942719000 # Number of ticks simulated 5final_tick 47384942719000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 146603 # Simulator instruction rate (inst/s) 8host_op_rate 172405 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 7419029838 # Simulator tick rate (ticks/s) 10host_mem_usage 776468 # Number of bytes of host memory used 11host_seconds 6386.95 # Real time elapsed on the host 12sim_insts 936348150 # Number of instructions simulated 13sim_ops 1101141201 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu0.dtb.walker 225984 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu0.itb.walker 211072 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu0.inst 4210272 # Number of bytes read from this memory 20system.physmem.bytes_read::cpu0.data 17875336 # Number of bytes read from this memory 21system.physmem.bytes_read::cpu0.l2cache.prefetcher 22288384 # Number of bytes read from this memory 22system.physmem.bytes_read::cpu1.dtb.walker 132032 # Number of bytes read from this memory 23system.physmem.bytes_read::cpu1.itb.walker 98944 # Number of bytes read from this memory 24system.physmem.bytes_read::cpu1.inst 3431264 # Number of bytes read from this memory 25system.physmem.bytes_read::cpu1.data 10538960 # Number of bytes read from this memory 26system.physmem.bytes_read::cpu1.l2cache.prefetcher 15414592 # Number of bytes read from this memory 27system.physmem.bytes_read::realview.ide 437696 # Number of bytes read from this memory 28system.physmem.bytes_read::total 74864536 # Number of bytes read from this memory 29system.physmem.bytes_inst_read::cpu0.inst 4210272 # Number of instructions bytes read from this memory 30system.physmem.bytes_inst_read::cpu1.inst 3431264 # Number of instructions bytes read from this memory 31system.physmem.bytes_inst_read::total 7641536 # Number of instructions bytes read from this memory 32system.physmem.bytes_written::writebacks 90448704 # Number of bytes written to this memory 33system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory 34system.physmem.bytes_written::cpu1.data 4 # Number of bytes written to this memory 35system.physmem.bytes_written::total 90469288 # Number of bytes written to this memory 36system.physmem.num_reads::cpu0.dtb.walker 3531 # Number of read requests responded to by this memory 37system.physmem.num_reads::cpu0.itb.walker 3298 # Number of read requests responded to by this memory 38system.physmem.num_reads::cpu0.inst 81738 # Number of read requests responded to by this memory 39system.physmem.num_reads::cpu0.data 279315 # Number of read requests responded to by this memory 40system.physmem.num_reads::cpu0.l2cache.prefetcher 348256 # Number of read requests responded to by this memory 41system.physmem.num_reads::cpu1.dtb.walker 2063 # Number of read requests responded to by this memory 42system.physmem.num_reads::cpu1.itb.walker 1546 # Number of read requests responded to by this memory 43system.physmem.num_reads::cpu1.inst 53657 # Number of read requests responded to by this memory 44system.physmem.num_reads::cpu1.data 164684 # Number of read requests responded to by this memory 45system.physmem.num_reads::cpu1.l2cache.prefetcher 240853 # Number of read requests responded to by this memory 46system.physmem.num_reads::realview.ide 6839 # Number of read requests responded to by this memory 47system.physmem.num_reads::total 1185780 # Number of read requests responded to by this memory 48system.physmem.num_writes::writebacks 1413261 # Number of write requests responded to by this memory 49system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory 50system.physmem.num_writes::cpu1.data 1 # Number of write requests responded to by this memory 51system.physmem.num_writes::total 1415835 # Number of write requests responded to by this memory 52system.physmem.bw_read::cpu0.dtb.walker 4769 # Total read bandwidth from this memory (bytes/s) 53system.physmem.bw_read::cpu0.itb.walker 4454 # Total read bandwidth from this memory (bytes/s) 54system.physmem.bw_read::cpu0.inst 88853 # Total read bandwidth from this memory (bytes/s) 55system.physmem.bw_read::cpu0.data 377237 # Total read bandwidth from this memory (bytes/s) 56system.physmem.bw_read::cpu0.l2cache.prefetcher 470368 # Total read bandwidth from this memory (bytes/s) 57system.physmem.bw_read::cpu1.dtb.walker 2786 # Total read bandwidth from this memory (bytes/s) 58system.physmem.bw_read::cpu1.itb.walker 2088 # Total read bandwidth from this memory (bytes/s) 59system.physmem.bw_read::cpu1.inst 72413 # Total read bandwidth from this memory (bytes/s) 60system.physmem.bw_read::cpu1.data 222412 # Total read bandwidth from this memory (bytes/s) 61system.physmem.bw_read::cpu1.l2cache.prefetcher 325306 # Total read bandwidth from this memory (bytes/s) 62system.physmem.bw_read::realview.ide 9237 # Total read bandwidth from this memory (bytes/s) 63system.physmem.bw_read::total 1579922 # Total read bandwidth from this memory (bytes/s) 64system.physmem.bw_inst_read::cpu0.inst 88853 # Instruction read bandwidth from this memory (bytes/s) 65system.physmem.bw_inst_read::cpu1.inst 72413 # Instruction read bandwidth from this memory (bytes/s) 66system.physmem.bw_inst_read::total 161265 # Instruction read bandwidth from this memory (bytes/s) 67system.physmem.bw_write::writebacks 1908807 # Write bandwidth from this memory (bytes/s) 68system.physmem.bw_write::cpu0.data 434 # Write bandwidth from this memory (bytes/s) 69system.physmem.bw_write::cpu1.data 0 # Write bandwidth from this memory (bytes/s) 70system.physmem.bw_write::total 1909241 # Write bandwidth from this memory (bytes/s) 71system.physmem.bw_total::writebacks 1908807 # Total bandwidth to/from this memory (bytes/s) 72system.physmem.bw_total::cpu0.dtb.walker 4769 # Total bandwidth to/from this memory (bytes/s) 73system.physmem.bw_total::cpu0.itb.walker 4454 # Total bandwidth to/from this memory (bytes/s) 74system.physmem.bw_total::cpu0.inst 88853 # Total bandwidth to/from this memory (bytes/s) 75system.physmem.bw_total::cpu0.data 377671 # Total bandwidth to/from this memory (bytes/s) 76system.physmem.bw_total::cpu0.l2cache.prefetcher 470368 # Total bandwidth to/from this memory (bytes/s) 77system.physmem.bw_total::cpu1.dtb.walker 2786 # Total bandwidth to/from this memory (bytes/s) 78system.physmem.bw_total::cpu1.itb.walker 2088 # Total bandwidth to/from this memory (bytes/s) 79system.physmem.bw_total::cpu1.inst 72413 # Total bandwidth to/from this memory (bytes/s) 80system.physmem.bw_total::cpu1.data 222412 # Total bandwidth to/from this memory (bytes/s) 81system.physmem.bw_total::cpu1.l2cache.prefetcher 325306 # Total bandwidth to/from this memory (bytes/s) 82system.physmem.bw_total::realview.ide 9237 # Total bandwidth to/from this memory (bytes/s) 83system.physmem.bw_total::total 3489164 # Total bandwidth to/from this memory (bytes/s) 84system.physmem.readReqs 1185780 # Number of read requests accepted 85system.physmem.writeReqs 1415835 # Number of write requests accepted 86system.physmem.readBursts 1185780 # Number of DRAM read bursts, including those serviced by the write queue 87system.physmem.writeBursts 1415835 # Number of DRAM write bursts, including those merged in the write queue 88system.physmem.bytesReadDRAM 75867200 # Total number of bytes read from DRAM 89system.physmem.bytesReadWrQ 22720 # Total number of bytes read from write queue 90system.physmem.bytesWritten 90467840 # Total number of bytes written to DRAM 91system.physmem.bytesReadSys 74864536 # Total read bytes from the system interface side 92system.physmem.bytesWrittenSys 90469288 # Total written bytes from the system interface side 93system.physmem.servicedByWrQ 355 # Number of DRAM read bursts serviced by the write queue 94system.physmem.mergedWrBursts 2247 # Number of DRAM write bursts merged with an existing one 95system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 96system.physmem.perBankRdBursts::0 74918 # Per bank write bursts 97system.physmem.perBankRdBursts::1 82946 # Per bank write bursts 98system.physmem.perBankRdBursts::2 75146 # Per bank write bursts 99system.physmem.perBankRdBursts::3 74319 # Per bank write bursts 100system.physmem.perBankRdBursts::4 73960 # Per bank write bursts 101system.physmem.perBankRdBursts::5 83356 # Per bank write bursts 102system.physmem.perBankRdBursts::6 71088 # Per bank write bursts 103system.physmem.perBankRdBursts::7 75076 # Per bank write bursts 104system.physmem.perBankRdBursts::8 69225 # Per bank write bursts 105system.physmem.perBankRdBursts::9 91582 # Per bank write bursts 106system.physmem.perBankRdBursts::10 63014 # Per bank write bursts 107system.physmem.perBankRdBursts::11 68676 # Per bank write bursts 108system.physmem.perBankRdBursts::12 68042 # Per bank write bursts 109system.physmem.perBankRdBursts::13 71091 # Per bank write bursts 110system.physmem.perBankRdBursts::14 73017 # Per bank write bursts 111system.physmem.perBankRdBursts::15 69969 # Per bank write bursts 112system.physmem.perBankWrBursts::0 88621 # Per bank write bursts 113system.physmem.perBankWrBursts::1 92960 # Per bank write bursts 114system.physmem.perBankWrBursts::2 88280 # Per bank write bursts 115system.physmem.perBankWrBursts::3 90026 # Per bank write bursts 116system.physmem.perBankWrBursts::4 89701 # Per bank write bursts 117system.physmem.perBankWrBursts::5 97248 # Per bank write bursts 118system.physmem.perBankWrBursts::6 87218 # Per bank write bursts 119system.physmem.perBankWrBursts::7 89230 # Per bank write bursts 120system.physmem.perBankWrBursts::8 86326 # Per bank write bursts 121system.physmem.perBankWrBursts::9 88636 # Per bank write bursts 122system.physmem.perBankWrBursts::10 82100 # Per bank write bursts 123system.physmem.perBankWrBursts::11 87622 # Per bank write bursts 124system.physmem.perBankWrBursts::12 86001 # Per bank write bursts 125system.physmem.perBankWrBursts::13 87485 # Per bank write bursts 126system.physmem.perBankWrBursts::14 85741 # Per bank write bursts 127system.physmem.perBankWrBursts::15 86365 # Per bank write bursts 128system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 129system.physmem.numWrRetry 51113 # Number of times write queue was full causing retry 130system.physmem.totGap 47384941205500 # Total gap between requests 131system.physmem.readPktSize::0 0 # Read request sizes (log2) 132system.physmem.readPktSize::1 0 # Read request sizes (log2) 133system.physmem.readPktSize::2 0 # Read request sizes (log2) 134system.physmem.readPktSize::3 25 # Read request sizes (log2) 135system.physmem.readPktSize::4 21333 # Read request sizes (log2) 136system.physmem.readPktSize::5 0 # Read request sizes (log2) 137system.physmem.readPktSize::6 1164422 # Read request sizes (log2) 138system.physmem.writePktSize::0 0 # Write request sizes (log2) 139system.physmem.writePktSize::1 0 # Write request sizes (log2) 140system.physmem.writePktSize::2 2 # Write request sizes (log2) 141system.physmem.writePktSize::3 2572 # Write request sizes (log2) 142system.physmem.writePktSize::4 0 # Write request sizes (log2) 143system.physmem.writePktSize::5 0 # Write request sizes (log2) 144system.physmem.writePktSize::6 1413261 # Write request sizes (log2) 145system.physmem.rdQLenPdf::0 492558 # What read queue length does an incoming req see 146system.physmem.rdQLenPdf::1 272193 # What read queue length does an incoming req see 147system.physmem.rdQLenPdf::2 123866 # What read queue length does an incoming req see 148system.physmem.rdQLenPdf::3 77106 # What read queue length does an incoming req see 149system.physmem.rdQLenPdf::4 49827 # What read queue length does an incoming req see 150system.physmem.rdQLenPdf::5 41505 # What read queue length does an incoming req see 151system.physmem.rdQLenPdf::6 37948 # What read queue length does an incoming req see 152system.physmem.rdQLenPdf::7 35214 # What read queue length does an incoming req see 153system.physmem.rdQLenPdf::8 31591 # What read queue length does an incoming req see 154system.physmem.rdQLenPdf::9 9310 # What read queue length does an incoming req see 155system.physmem.rdQLenPdf::10 5210 # What read queue length does an incoming req see 156system.physmem.rdQLenPdf::11 3059 # What read queue length does an incoming req see 157system.physmem.rdQLenPdf::12 1824 # What read queue length does an incoming req see 158system.physmem.rdQLenPdf::13 1397 # What read queue length does an incoming req see 159system.physmem.rdQLenPdf::14 811 # What read queue length does an incoming req see 160system.physmem.rdQLenPdf::15 674 # What read queue length does an incoming req see 161system.physmem.rdQLenPdf::16 576 # What read queue length does an incoming req see 162system.physmem.rdQLenPdf::17 471 # What read queue length does an incoming req see 163system.physmem.rdQLenPdf::18 162 # What read queue length does an incoming req see 164system.physmem.rdQLenPdf::19 110 # What read queue length does an incoming req see 165system.physmem.rdQLenPdf::20 10 # What read queue length does an incoming req see 166system.physmem.rdQLenPdf::21 3 # What read queue length does an incoming req see 167system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 168system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 169system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 170system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 171system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 172system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 173system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 174system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 175system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 176system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 177system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::15 22656 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::16 26213 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::17 37414 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::18 43560 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::19 48703 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::20 53588 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::21 59870 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::22 65839 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::23 71191 # What write queue length does an incoming req see 201system.physmem.wrQLenPdf::24 73927 # What write queue length does an incoming req see 202system.physmem.wrQLenPdf::25 78606 # What write queue length does an incoming req see 203system.physmem.wrQLenPdf::26 82389 # What write queue length does an incoming req see 204system.physmem.wrQLenPdf::27 81499 # What write queue length does an incoming req see 205system.physmem.wrQLenPdf::28 83906 # What write queue length does an incoming req see 206system.physmem.wrQLenPdf::29 89741 # What write queue length does an incoming req see 207system.physmem.wrQLenPdf::30 97285 # What write queue length does an incoming req see 208system.physmem.wrQLenPdf::31 86545 # What write queue length does an incoming req see 209system.physmem.wrQLenPdf::32 80600 # What write queue length does an incoming req see 210system.physmem.wrQLenPdf::33 8679 # What write queue length does an incoming req see 211system.physmem.wrQLenPdf::34 5080 # What write queue length does an incoming req see 212system.physmem.wrQLenPdf::35 3802 # What write queue length does an incoming req see 213system.physmem.wrQLenPdf::36 2902 # What write queue length does an incoming req see 214system.physmem.wrQLenPdf::37 2352 # What write queue length does an incoming req see 215system.physmem.wrQLenPdf::38 2103 # What write queue length does an incoming req see 216system.physmem.wrQLenPdf::39 1842 # What write queue length does an incoming req see 217system.physmem.wrQLenPdf::40 1736 # What write queue length does an incoming req see 218system.physmem.wrQLenPdf::41 1672 # What write queue length does an incoming req see 219system.physmem.wrQLenPdf::42 1659 # What write queue length does an incoming req see 220system.physmem.wrQLenPdf::43 1715 # What write queue length does an incoming req see 221system.physmem.wrQLenPdf::44 1682 # What write queue length does an incoming req see 222system.physmem.wrQLenPdf::45 1630 # What write queue length does an incoming req see 223system.physmem.wrQLenPdf::46 1838 # What write queue length does an incoming req see 224system.physmem.wrQLenPdf::47 1694 # What write queue length does an incoming req see 225system.physmem.wrQLenPdf::48 1790 # What write queue length does an incoming req see 226system.physmem.wrQLenPdf::49 1915 # What write queue length does an incoming req see 227system.physmem.wrQLenPdf::50 1936 # What write queue length does an incoming req see 228system.physmem.wrQLenPdf::51 2089 # What write queue length does an incoming req see 229system.physmem.wrQLenPdf::52 2158 # What write queue length does an incoming req see 230system.physmem.wrQLenPdf::53 2578 # What write queue length does an incoming req see 231system.physmem.wrQLenPdf::54 2909 # What write queue length does an incoming req see 232system.physmem.wrQLenPdf::55 3105 # What write queue length does an incoming req see 233system.physmem.wrQLenPdf::56 3321 # What write queue length does an incoming req see 234system.physmem.wrQLenPdf::57 3357 # What write queue length does an incoming req see 235system.physmem.wrQLenPdf::58 3394 # What write queue length does an incoming req see 236system.physmem.wrQLenPdf::59 4009 # What write queue length does an incoming req see 237system.physmem.wrQLenPdf::60 5197 # What write queue length does an incoming req see 238system.physmem.wrQLenPdf::61 6401 # What write queue length does an incoming req see 239system.physmem.wrQLenPdf::62 25051 # What write queue length does an incoming req see 240system.physmem.wrQLenPdf::63 120445 # What write queue length does an incoming req see 241system.physmem.bytesPerActivate::samples 1083045 # Bytes accessed per row activation 242system.physmem.bytesPerActivate::mean 153.580618 # Bytes accessed per row activation 243system.physmem.bytesPerActivate::gmean 102.695829 # Bytes accessed per row activation 244system.physmem.bytesPerActivate::stdev 199.684011 # Bytes accessed per row activation 245system.physmem.bytesPerActivate::0-127 694535 64.13% 64.13% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::128-255 223527 20.64% 84.77% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::256-383 61545 5.68% 90.45% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::384-511 27125 2.50% 92.95% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::512-639 21919 2.02% 94.98% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::640-767 12312 1.14% 96.11% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::768-895 8465 0.78% 96.90% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::896-1023 6818 0.63% 97.53% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::1024-1151 26799 2.47% 100.00% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::total 1083045 # Bytes accessed per row activation 255system.physmem.rdPerTurnAround::samples 67614 # Reads before turning the bus around for writes 256system.physmem.rdPerTurnAround::mean 17.532168 # Reads before turning the bus around for writes 257system.physmem.rdPerTurnAround::stdev 68.484066 # Reads before turning the bus around for writes 258system.physmem.rdPerTurnAround::0-511 67610 99.99% 99.99% # Reads before turning the bus around for writes 259system.physmem.rdPerTurnAround::512-1023 2 0.00% 100.00% # Reads before turning the bus around for writes 260system.physmem.rdPerTurnAround::10240-10751 1 0.00% 100.00% # Reads before turning the bus around for writes 261system.physmem.rdPerTurnAround::13824-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 262system.physmem.rdPerTurnAround::total 67614 # Reads before turning the bus around for writes 263system.physmem.wrPerTurnAround::samples 67614 # Writes before turning the bus around for reads 264system.physmem.wrPerTurnAround::mean 20.906321 # Writes before turning the bus around for reads 265system.physmem.wrPerTurnAround::gmean 17.453992 # Writes before turning the bus around for reads 266system.physmem.wrPerTurnAround::stdev 533.973047 # Writes before turning the bus around for reads 267system.physmem.wrPerTurnAround::0-2047 67611 100.00% 100.00% # Writes before turning the bus around for reads 268system.physmem.wrPerTurnAround::12288-14335 1 0.00% 100.00% # Writes before turning the bus around for reads 269system.physmem.wrPerTurnAround::43008-45055 1 0.00% 100.00% # Writes before turning the bus around for reads 270system.physmem.wrPerTurnAround::129024-131071 1 0.00% 100.00% # Writes before turning the bus around for reads 271system.physmem.wrPerTurnAround::total 67614 # Writes before turning the bus around for reads 272system.physmem.totQLat 72498378118 # Total ticks spent queuing 273system.physmem.totMemAccLat 94725096868 # Total ticks spent from burst creation until serviced by the DRAM 274system.physmem.totBusLat 5927125000 # Total ticks spent in databus transfers 275system.physmem.avgQLat 61158.13 # Average queueing delay per DRAM burst 276system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 277system.physmem.avgMemAccLat 79908.13 # Average memory access latency per DRAM burst 278system.physmem.avgRdBW 1.60 # Average DRAM read bandwidth in MiByte/s 279system.physmem.avgWrBW 1.91 # Average achieved write bandwidth in MiByte/s 280system.physmem.avgRdBWSys 1.58 # Average system read bandwidth in MiByte/s 281system.physmem.avgWrBWSys 1.91 # Average system write bandwidth in MiByte/s 282system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 283system.physmem.busUtil 0.03 # Data bus utilization in percentage 284system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads 285system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes 286system.physmem.avgRdQLen 1.24 # Average read queue length when enqueuing 287system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing 288system.physmem.readRowHits 894792 # Number of row buffer hits during reads 289system.physmem.writeRowHits 621147 # Number of row buffer hits during writes 290system.physmem.readRowHitRate 75.48 # Row buffer hit rate for reads 291system.physmem.writeRowHitRate 43.94 # Row buffer hit rate for writes 292system.physmem.avgGap 18213663.90 # Average gap between requests 293system.physmem.pageHitRate 58.33 # Row buffer hit rate, read and write combined 294system.physmem_0.actEnergy 4041154320 # Energy for activate commands per rank (pJ) 295system.physmem_0.preEnergy 2147920665 # Energy for precharge commands per rank (pJ) 296system.physmem_0.readEnergy 4361176260 # Energy for read commands per rank (pJ) 297system.physmem_0.writeEnergy 3775542480 # Energy for write commands per rank (pJ) 298system.physmem_0.refreshEnergy 33222521280.000008 # Energy for refresh commands per rank (pJ) 299system.physmem_0.actBackEnergy 42262106220 # Energy for active background per rank (pJ) 300system.physmem_0.preBackEnergy 1577144160 # Energy for precharge background per rank (pJ) 301system.physmem_0.actPowerDownEnergy 67404809070 # Energy for active power-down per rank (pJ) 302system.physmem_0.prePowerDownEnergy 44351104800 # Energy for precharge power-down per rank (pJ) 303system.physmem_0.selfRefreshEnergy 11290594038405 # Energy for self refresh per rank (pJ) 304system.physmem_0.totalEnergy 11493753562350 # Total energy per rank (pJ) 305system.physmem_0.averagePower 242.561305 # Core power per rank (mW) 306system.physmem_0.totalIdleTime 47288119152834 # Total Idle time Per DRAM Rank 307system.physmem_0.memoryStateTime::IDLE 2641670410 # Time in different power states 308system.physmem_0.memoryStateTime::REF 14105156000 # Time in different power states 309system.physmem_0.memoryStateTime::SREF 47024804557250 # Time in different power states 310system.physmem_0.memoryStateTime::PRE_PDN 115497548988 # Time in different power states 311system.physmem_0.memoryStateTime::ACT 80076687506 # Time in different power states 312system.physmem_0.memoryStateTime::ACT_PDN 147817098846 # Time in different power states 313system.physmem_1.actEnergy 3691794120 # Energy for activate commands per rank (pJ) 314system.physmem_1.preEnergy 1962235110 # Energy for precharge commands per rank (pJ) 315system.physmem_1.readEnergy 4102758240 # Energy for read commands per rank (pJ) 316system.physmem_1.writeEnergy 3603240720 # Energy for write commands per rank (pJ) 317system.physmem_1.refreshEnergy 31839581280.000008 # Energy for refresh commands per rank (pJ) 318system.physmem_1.actBackEnergy 42875044890 # Energy for active background per rank (pJ) 319system.physmem_1.preBackEnergy 1564584000 # Energy for precharge background per rank (pJ) 320system.physmem_1.actPowerDownEnergy 59886050220 # Energy for active power-down per rank (pJ) 321system.physmem_1.prePowerDownEnergy 43118785440 # Energy for precharge power-down per rank (pJ) 322system.physmem_1.selfRefreshEnergy 11295073117425 # Energy for self refresh per rank (pJ) 323system.physmem_1.totalEnergy 11487733544595 # Total energy per rank (pJ) 324system.physmem_1.averagePower 242.434260 # Core power per rank (mW) 325system.physmem_1.totalIdleTime 47286801320918 # Total Idle time Per DRAM Rank 326system.physmem_1.memoryStateTime::IDLE 2657158504 # Time in different power states 327system.physmem_1.memoryStateTime::REF 13520630000 # Time in different power states 328system.physmem_1.memoryStateTime::SREF 47043190241000 # Time in different power states 329system.physmem_1.memoryStateTime::PRE_PDN 112288389331 # Time in different power states 330system.physmem_1.memoryStateTime::ACT 81956603828 # Time in different power states 331system.physmem_1.memoryStateTime::ACT_PDN 131329696337 # Time in different power states 332system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 333system.realview.nvmem.bytes_read::cpu0.inst 368 # Number of bytes read from this memory 334system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory 335system.realview.nvmem.bytes_read::cpu1.inst 144 # Number of bytes read from this memory 336system.realview.nvmem.bytes_read::cpu1.data 8 # Number of bytes read from this memory 337system.realview.nvmem.bytes_read::total 556 # Number of bytes read from this memory 338system.realview.nvmem.bytes_inst_read::cpu0.inst 368 # Number of instructions bytes read from this memory 339system.realview.nvmem.bytes_inst_read::cpu1.inst 144 # Number of instructions bytes read from this memory 340system.realview.nvmem.bytes_inst_read::total 512 # Number of instructions bytes read from this memory 341system.realview.nvmem.num_reads::cpu0.inst 23 # Number of read requests responded to by this memory 342system.realview.nvmem.num_reads::cpu0.data 5 # Number of read requests responded to by this memory 343system.realview.nvmem.num_reads::cpu1.inst 9 # Number of read requests responded to by this memory 344system.realview.nvmem.num_reads::cpu1.data 1 # Number of read requests responded to by this memory 345system.realview.nvmem.num_reads::total 38 # Number of read requests responded to by this memory 346system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) 347system.realview.nvmem.bw_read::cpu0.data 1 # Total read bandwidth from this memory (bytes/s) 348system.realview.nvmem.bw_read::cpu1.inst 3 # Total read bandwidth from this memory (bytes/s) 349system.realview.nvmem.bw_read::cpu1.data 0 # Total read bandwidth from this memory (bytes/s) 350system.realview.nvmem.bw_read::total 12 # Total read bandwidth from this memory (bytes/s) 351system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) 352system.realview.nvmem.bw_inst_read::cpu1.inst 3 # Instruction read bandwidth from this memory (bytes/s) 353system.realview.nvmem.bw_inst_read::total 11 # Instruction read bandwidth from this memory (bytes/s) 354system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) 355system.realview.nvmem.bw_total::cpu0.data 1 # Total bandwidth to/from this memory (bytes/s) 356system.realview.nvmem.bw_total::cpu1.inst 3 # Total bandwidth to/from this memory (bytes/s) 357system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s) 358system.realview.nvmem.bw_total::total 12 # Total bandwidth to/from this memory (bytes/s) 359system.realview.vram.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 360system.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 361system.bridge.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 362system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD). 363system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD). 364system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD). 365system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes. 366system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes. 367system.cf0.dma_write_txs 1670 # Number of DMA write transactions. 368system.cpu0.branchPred.lookups 139745078 # Number of BP lookups 369system.cpu0.branchPred.condPredicted 92256746 # Number of conditional branches predicted 370system.cpu0.branchPred.condIncorrect 6767345 # Number of conditional branches incorrect 371system.cpu0.branchPred.BTBLookups 98774130 # Number of BTB lookups 372system.cpu0.branchPred.BTBHits 61692324 # Number of BTB hits 373system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 374system.cpu0.branchPred.BTBHitPct 62.457978 # BTB Hit Percentage 375system.cpu0.branchPred.usedRAS 19130272 # Number of times the RAS was used to get a target. 376system.cpu0.branchPred.RASInCorrect 187780 # Number of incorrect RAS predictions. 377system.cpu0.branchPred.indirectLookups 4236971 # Number of indirect predictor lookups. 378system.cpu0.branchPred.indirectHits 2716946 # Number of indirect target hits. 379system.cpu0.branchPred.indirectMisses 1520025 # Number of indirect misses. 380system.cpu0.branchPredindirectMispredicted 386103 # Number of mispredicted indirect branches. 381system.cpu_clk_domain.clock 500 # Clock period in ticks 382system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 383system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 384system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 385system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 387system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 388system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 390system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 391system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 392system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 393system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 394system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 395system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 396system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 397system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 398system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 399system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 400system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 401system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 402system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 403system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 404system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 405system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 407system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 408system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 409system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 410system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 411system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 412system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 413system.cpu0.dtb.walker.walks 642249 # Table walker walks requested 414system.cpu0.dtb.walker.walksLong 642249 # Table walker walks initiated with long descriptors 415system.cpu0.dtb.walker.walksLongTerminationLevel::Level2 14371 # Level at which table walker walks with long descriptors terminate 416system.cpu0.dtb.walker.walksLongTerminationLevel::Level3 105891 # Level at which table walker walks with long descriptors terminate 417system.cpu0.dtb.walker.walksSquashedBefore 311173 # Table walks squashed before starting 418system.cpu0.dtb.walker.walkWaitTime::samples 331076 # Table walker wait (enqueue to first request) latency 419system.cpu0.dtb.walker.walkWaitTime::mean 2394.451727 # Table walker wait (enqueue to first request) latency 420system.cpu0.dtb.walker.walkWaitTime::stdev 14284.464178 # Table walker wait (enqueue to first request) latency 421system.cpu0.dtb.walker.walkWaitTime::0-65535 328283 99.16% 99.16% # Table walker wait (enqueue to first request) latency 422system.cpu0.dtb.walker.walkWaitTime::65536-131071 2041 0.62% 99.77% # Table walker wait (enqueue to first request) latency 423system.cpu0.dtb.walker.walkWaitTime::131072-196607 492 0.15% 99.92% # Table walker wait (enqueue to first request) latency 424system.cpu0.dtb.walker.walkWaitTime::196608-262143 140 0.04% 99.96% # Table walker wait (enqueue to first request) latency 425system.cpu0.dtb.walker.walkWaitTime::262144-327679 44 0.01% 99.98% # Table walker wait (enqueue to first request) latency 426system.cpu0.dtb.walker.walkWaitTime::327680-393215 49 0.01% 99.99% # Table walker wait (enqueue to first request) latency 427system.cpu0.dtb.walker.walkWaitTime::393216-458751 5 0.00% 99.99% # Table walker wait (enqueue to first request) latency 428system.cpu0.dtb.walker.walkWaitTime::458752-524287 3 0.00% 99.99% # Table walker wait (enqueue to first request) latency 429system.cpu0.dtb.walker.walkWaitTime::524288-589823 3 0.00% 100.00% # Table walker wait (enqueue to first request) latency 430system.cpu0.dtb.walker.walkWaitTime::589824-655359 15 0.00% 100.00% # Table walker wait (enqueue to first request) latency 431system.cpu0.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 432system.cpu0.dtb.walker.walkWaitTime::total 331076 # Table walker wait (enqueue to first request) latency 433system.cpu0.dtb.walker.walkCompletionTime::samples 352054 # Table walker service (enqueue to completion) latency 434system.cpu0.dtb.walker.walkCompletionTime::mean 21918.096372 # Table walker service (enqueue to completion) latency 435system.cpu0.dtb.walker.walkCompletionTime::gmean 18874.221671 # Table walker service (enqueue to completion) latency 436system.cpu0.dtb.walker.walkCompletionTime::stdev 17893.290078 # Table walker service (enqueue to completion) latency 437system.cpu0.dtb.walker.walkCompletionTime::0-65535 347548 98.72% 98.72% # Table walker service (enqueue to completion) latency 438system.cpu0.dtb.walker.walkCompletionTime::65536-131071 2975 0.85% 99.57% # Table walker service (enqueue to completion) latency 439system.cpu0.dtb.walker.walkCompletionTime::131072-196607 632 0.18% 99.74% # Table walker service (enqueue to completion) latency 440system.cpu0.dtb.walker.walkCompletionTime::196608-262143 594 0.17% 99.91% # Table walker service (enqueue to completion) latency 441system.cpu0.dtb.walker.walkCompletionTime::262144-327679 153 0.04% 99.96% # Table walker service (enqueue to completion) latency 442system.cpu0.dtb.walker.walkCompletionTime::327680-393215 118 0.03% 99.99% # Table walker service (enqueue to completion) latency 443system.cpu0.dtb.walker.walkCompletionTime::393216-458751 25 0.01% 100.00% # Table walker service (enqueue to completion) latency 444system.cpu0.dtb.walker.walkCompletionTime::458752-524287 5 0.00% 100.00% # Table walker service (enqueue to completion) latency 445system.cpu0.dtb.walker.walkCompletionTime::524288-589823 4 0.00% 100.00% # Table walker service (enqueue to completion) latency 446system.cpu0.dtb.walker.walkCompletionTime::total 352054 # Table walker service (enqueue to completion) latency 447system.cpu0.dtb.walker.walksPending::samples 539733877528 # Table walker pending requests distribution 448system.cpu0.dtb.walker.walksPending::mean 0.599244 # Table walker pending requests distribution 449system.cpu0.dtb.walker.walksPending::stdev 0.552867 # Table walker pending requests distribution 450system.cpu0.dtb.walker.walksPending::0-1 538149503028 99.71% 99.71% # Table walker pending requests distribution 451system.cpu0.dtb.walker.walksPending::2-3 904434000 0.17% 99.87% # Table walker pending requests distribution 452system.cpu0.dtb.walker.walksPending::4-5 320975500 0.06% 99.93% # Table walker pending requests distribution 453system.cpu0.dtb.walker.walksPending::6-7 139201000 0.03% 99.96% # Table walker pending requests distribution 454system.cpu0.dtb.walker.walksPending::8-9 110066000 0.02% 99.98% # Table walker pending requests distribution 455system.cpu0.dtb.walker.walksPending::10-11 60836000 0.01% 99.99% # Table walker pending requests distribution 456system.cpu0.dtb.walker.walksPending::12-13 22060500 0.00% 100.00% # Table walker pending requests distribution 457system.cpu0.dtb.walker.walksPending::14-15 25840500 0.00% 100.00% # Table walker pending requests distribution 458system.cpu0.dtb.walker.walksPending::16-17 959500 0.00% 100.00% # Table walker pending requests distribution 459system.cpu0.dtb.walker.walksPending::18-19 1500 0.00% 100.00% # Table walker pending requests distribution 460system.cpu0.dtb.walker.walksPending::total 539733877528 # Table walker pending requests distribution 461system.cpu0.dtb.walker.walkPageSizes::4K 105891 88.05% 88.05% # Table walker page sizes translated 462system.cpu0.dtb.walker.walkPageSizes::2M 14371 11.95% 100.00% # Table walker page sizes translated 463system.cpu0.dtb.walker.walkPageSizes::total 120262 # Table walker page sizes translated 464system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 642249 # Table walker requests started/completed, data/inst 465system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 466system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 642249 # Table walker requests started/completed, data/inst 467system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 120262 # Table walker requests started/completed, data/inst 468system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 469system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 120262 # Table walker requests started/completed, data/inst 470system.cpu0.dtb.walker.walkRequestOrigin::total 762511 # Table walker requests started/completed, data/inst 471system.cpu0.dtb.inst_hits 0 # ITB inst hits 472system.cpu0.dtb.inst_misses 0 # ITB inst misses 473system.cpu0.dtb.read_hits 102850435 # DTB read hits 474system.cpu0.dtb.read_misses 467880 # DTB read misses 475system.cpu0.dtb.write_hits 83320332 # DTB write hits 476system.cpu0.dtb.write_misses 174369 # DTB write misses 477system.cpu0.dtb.flush_tlb 16 # Number of times complete TLB was flushed 478system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 479system.cpu0.dtb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID 480system.cpu0.dtb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID 481system.cpu0.dtb.flush_entries 42516 # Number of entries that have been flushed from TLB 482system.cpu0.dtb.align_faults 599 # Number of TLB faults due to alignment restrictions 483system.cpu0.dtb.prefetch_faults 7036 # Number of TLB faults due to prefetch 484system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 485system.cpu0.dtb.perms_faults 38961 # Number of TLB faults due to permissions restrictions 486system.cpu0.dtb.read_accesses 103318315 # DTB read accesses 487system.cpu0.dtb.write_accesses 83494701 # DTB write accesses 488system.cpu0.dtb.inst_accesses 0 # ITB inst accesses 489system.cpu0.dtb.hits 186170767 # DTB hits 490system.cpu0.dtb.misses 642249 # DTB misses 491system.cpu0.dtb.accesses 186813016 # DTB accesses 492system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 493system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 494system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 495system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 496system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 497system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 498system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 499system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 500system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 501system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 502system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 503system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 504system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 505system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 506system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 507system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 508system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 509system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 510system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 511system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 512system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 513system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 514system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 515system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 516system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 517system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 518system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 519system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits 520system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses 521system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 522system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 523system.cpu0.itb.walker.walks 84160 # Table walker walks requested 524system.cpu0.itb.walker.walksLong 84160 # Table walker walks initiated with long descriptors 525system.cpu0.itb.walker.walksLongTerminationLevel::Level2 1044 # Level at which table walker walks with long descriptors terminate 526system.cpu0.itb.walker.walksLongTerminationLevel::Level3 58792 # Level at which table walker walks with long descriptors terminate 527system.cpu0.itb.walker.walksSquashedBefore 10193 # Table walks squashed before starting 528system.cpu0.itb.walker.walkWaitTime::samples 73967 # Table walker wait (enqueue to first request) latency 529system.cpu0.itb.walker.walkWaitTime::mean 1726.006192 # Table walker wait (enqueue to first request) latency 530system.cpu0.itb.walker.walkWaitTime::stdev 15527.215020 # Table walker wait (enqueue to first request) latency 531system.cpu0.itb.walker.walkWaitTime::0-65535 73402 99.24% 99.24% # Table walker wait (enqueue to first request) latency 532system.cpu0.itb.walker.walkWaitTime::65536-131071 457 0.62% 99.85% # Table walker wait (enqueue to first request) latency 533system.cpu0.itb.walker.walkWaitTime::131072-196607 56 0.08% 99.93% # Table walker wait (enqueue to first request) latency 534system.cpu0.itb.walker.walkWaitTime::196608-262143 12 0.02% 99.95% # Table walker wait (enqueue to first request) latency 535system.cpu0.itb.walker.walkWaitTime::262144-327679 7 0.01% 99.96% # Table walker wait (enqueue to first request) latency 536system.cpu0.itb.walker.walkWaitTime::327680-393215 9 0.01% 99.97% # Table walker wait (enqueue to first request) latency 537system.cpu0.itb.walker.walkWaitTime::393216-458751 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency 538system.cpu0.itb.walker.walkWaitTime::524288-589823 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency 539system.cpu0.itb.walker.walkWaitTime::589824-655359 22 0.03% 100.00% # Table walker wait (enqueue to first request) latency 540system.cpu0.itb.walker.walkWaitTime::total 73967 # Table walker wait (enqueue to first request) latency 541system.cpu0.itb.walker.walkCompletionTime::samples 70029 # Table walker service (enqueue to completion) latency 542system.cpu0.itb.walker.walkCompletionTime::mean 27234.188693 # Table walker service (enqueue to completion) latency 543system.cpu0.itb.walker.walkCompletionTime::gmean 23423.171681 # Table walker service (enqueue to completion) latency 544system.cpu0.itb.walker.walkCompletionTime::stdev 26401.977199 # Table walker service (enqueue to completion) latency 545system.cpu0.itb.walker.walkCompletionTime::0-65535 67612 96.55% 96.55% # Table walker service (enqueue to completion) latency 546system.cpu0.itb.walker.walkCompletionTime::65536-131071 1634 2.33% 98.88% # Table walker service (enqueue to completion) latency 547system.cpu0.itb.walker.walkCompletionTime::131072-196607 479 0.68% 99.57% # Table walker service (enqueue to completion) latency 548system.cpu0.itb.walker.walkCompletionTime::196608-262143 184 0.26% 99.83% # Table walker service (enqueue to completion) latency 549system.cpu0.itb.walker.walkCompletionTime::262144-327679 51 0.07% 99.90% # Table walker service (enqueue to completion) latency 550system.cpu0.itb.walker.walkCompletionTime::327680-393215 27 0.04% 99.94% # Table walker service (enqueue to completion) latency 551system.cpu0.itb.walker.walkCompletionTime::393216-458751 16 0.02% 99.96% # Table walker service (enqueue to completion) latency 552system.cpu0.itb.walker.walkCompletionTime::524288-589823 4 0.01% 99.97% # Table walker service (enqueue to completion) latency 553system.cpu0.itb.walker.walkCompletionTime::589824-655359 21 0.03% 100.00% # Table walker service (enqueue to completion) latency 554system.cpu0.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency 555system.cpu0.itb.walker.walkCompletionTime::total 70029 # Table walker service (enqueue to completion) latency 556system.cpu0.itb.walker.walksPending::samples 423766533036 # Table walker pending requests distribution 557system.cpu0.itb.walker.walksPending::mean 0.875739 # Table walker pending requests distribution 558system.cpu0.itb.walker.walksPending::stdev 0.330248 # Table walker pending requests distribution 559system.cpu0.itb.walker.walksPending::0 52705402108 12.44% 12.44% # Table walker pending requests distribution 560system.cpu0.itb.walker.walksPending::1 371016436928 87.55% 99.99% # Table walker pending requests distribution 561system.cpu0.itb.walker.walksPending::2 42131000 0.01% 100.00% # Table walker pending requests distribution 562system.cpu0.itb.walker.walksPending::3 1939000 0.00% 100.00% # Table walker pending requests distribution 563system.cpu0.itb.walker.walksPending::4 624000 0.00% 100.00% # Table walker pending requests distribution 564system.cpu0.itb.walker.walksPending::total 423766533036 # Table walker pending requests distribution 565system.cpu0.itb.walker.walkPageSizes::4K 58792 98.26% 98.26% # Table walker page sizes translated 566system.cpu0.itb.walker.walkPageSizes::2M 1044 1.74% 100.00% # Table walker page sizes translated 567system.cpu0.itb.walker.walkPageSizes::total 59836 # Table walker page sizes translated 568system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 569system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 84160 # Table walker requests started/completed, data/inst 570system.cpu0.itb.walker.walkRequestOrigin_Requested::total 84160 # Table walker requests started/completed, data/inst 571system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 572system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 59836 # Table walker requests started/completed, data/inst 573system.cpu0.itb.walker.walkRequestOrigin_Completed::total 59836 # Table walker requests started/completed, data/inst 574system.cpu0.itb.walker.walkRequestOrigin::total 143996 # Table walker requests started/completed, data/inst 575system.cpu0.itb.inst_hits 220066677 # ITB inst hits 576system.cpu0.itb.inst_misses 84160 # ITB inst misses 577system.cpu0.itb.read_hits 0 # DTB read hits 578system.cpu0.itb.read_misses 0 # DTB read misses 579system.cpu0.itb.write_hits 0 # DTB write hits 580system.cpu0.itb.write_misses 0 # DTB write misses 581system.cpu0.itb.flush_tlb 16 # Number of times complete TLB was flushed 582system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 583system.cpu0.itb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID 584system.cpu0.itb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID 585system.cpu0.itb.flush_entries 30584 # Number of entries that have been flushed from TLB 586system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 587system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 588system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 589system.cpu0.itb.perms_faults 203568 # Number of TLB faults due to permissions restrictions 590system.cpu0.itb.read_accesses 0 # DTB read accesses 591system.cpu0.itb.write_accesses 0 # DTB write accesses 592system.cpu0.itb.inst_accesses 220150837 # ITB inst accesses 593system.cpu0.itb.hits 220066677 # DTB hits 594system.cpu0.itb.misses 84160 # DTB misses 595system.cpu0.itb.accesses 220150837 # DTB accesses 596system.cpu0.numPwrStateTransitions 10070 # Number of power state transitions 597system.cpu0.pwrStateClkGateDist::samples 5035 # Distribution of time spent in the clock gated state 598system.cpu0.pwrStateClkGateDist::mean 9333517887.918768 # Distribution of time spent in the clock gated state 599system.cpu0.pwrStateClkGateDist::stdev 154504325024.809692 # Distribution of time spent in the clock gated state 600system.cpu0.pwrStateClkGateDist::underflows 3827 76.01% 76.01% # Distribution of time spent in the clock gated state 601system.cpu0.pwrStateClkGateDist::1000-5e+10 1181 23.46% 99.46% # Distribution of time spent in the clock gated state 602system.cpu0.pwrStateClkGateDist::5e+10-1e+11 7 0.14% 99.60% # Distribution of time spent in the clock gated state 603system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.02% 99.62% # Distribution of time spent in the clock gated state 604system.cpu0.pwrStateClkGateDist::2e+11-2.5e+11 3 0.06% 99.68% # Distribution of time spent in the clock gated state 605system.cpu0.pwrStateClkGateDist::3.5e+11-4e+11 1 0.02% 99.70% # Distribution of time spent in the clock gated state 606system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 1 0.02% 99.72% # Distribution of time spent in the clock gated state 607system.cpu0.pwrStateClkGateDist::6.5e+11-7e+11 1 0.02% 99.74% # Distribution of time spent in the clock gated state 608system.cpu0.pwrStateClkGateDist::overflows 13 0.26% 100.00% # Distribution of time spent in the clock gated state 609system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 610system.cpu0.pwrStateClkGateDist::max_value 6914082505000 # Distribution of time spent in the clock gated state 611system.cpu0.pwrStateClkGateDist::total 5035 # Distribution of time spent in the clock gated state 612system.cpu0.pwrStateResidencyTicks::ON 390680153329 # Cumulative time (in ticks) in various power states 613system.cpu0.pwrStateResidencyTicks::CLK_GATED 46994262565671 # Cumulative time (in ticks) in various power states 614system.cpu0.numCycles 781361530 # number of cpu cycles simulated 615system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started 616system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed 617system.cpu0.fetch.icacheStallCycles 89977379 # Number of cycles fetch is stalled on an Icache miss 618system.cpu0.fetch.Insts 618690334 # Number of instructions fetch has processed 619system.cpu0.fetch.Branches 139745078 # Number of branches that fetch encountered 620system.cpu0.fetch.predictedBranches 83539542 # Number of branches that fetch has predicted taken 621system.cpu0.fetch.Cycles 647313928 # Number of cycles fetch has run and was not squashing or blocked 622system.cpu0.fetch.SquashCycles 14578052 # Number of cycles fetch has spent squashing 623system.cpu0.fetch.TlbCycles 1993554 # Number of cycles fetch has spent waiting for tlb 624system.cpu0.fetch.MiscStallCycles 302966 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 625system.cpu0.fetch.PendingTrapStallCycles 5990682 # Number of stall cycles due to pending traps 626system.cpu0.fetch.PendingQuiesceStallCycles 771527 # Number of stall cycles due to pending quiesce instructions 627system.cpu0.fetch.IcacheWaitRetryStallCycles 852599 # Number of stall cycles due to full MSHR 628system.cpu0.fetch.CacheLines 219863904 # Number of cache lines fetched 629system.cpu0.fetch.IcacheSquashes 1701332 # Number of outstanding Icache misses that were squashed 630system.cpu0.fetch.ItlbSquashes 27447 # Number of outstanding ITLB misses that were squashed 631system.cpu0.fetch.rateDist::samples 754491661 # Number of instructions fetched each cycle (Total) 632system.cpu0.fetch.rateDist::mean 0.959990 # Number of instructions fetched each cycle (Total) 633system.cpu0.fetch.rateDist::stdev 1.215112 # Number of instructions fetched each cycle (Total) 634system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 635system.cpu0.fetch.rateDist::0 407421945 54.00% 54.00% # Number of instructions fetched each cycle (Total) 636system.cpu0.fetch.rateDist::1 135112889 17.91% 71.91% # Number of instructions fetched each cycle (Total) 637system.cpu0.fetch.rateDist::2 46679176 6.19% 78.09% # Number of instructions fetched each cycle (Total) 638system.cpu0.fetch.rateDist::3 165277651 21.91% 100.00% # Number of instructions fetched each cycle (Total) 639system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 640system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 641system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 642system.cpu0.fetch.rateDist::total 754491661 # Number of instructions fetched each cycle (Total) 643system.cpu0.fetch.branchRate 0.178848 # Number of branch fetches per cycle 644system.cpu0.fetch.rate 0.791811 # Number of inst fetches per cycle 645system.cpu0.decode.IdleCycles 107863691 # Number of cycles decode is idle 646system.cpu0.decode.BlockedCycles 373653702 # Number of cycles decode is blocked 647system.cpu0.decode.RunCycles 228590583 # Number of cycles decode is running 648system.cpu0.decode.UnblockCycles 39162463 # Number of cycles decode is unblocking 649system.cpu0.decode.SquashCycles 5221222 # Number of cycles decode is squashing 650system.cpu0.decode.BranchResolved 20030707 # Number of times decode resolved a branch 651system.cpu0.decode.BranchMispred 2107727 # Number of times decode detected a branch misprediction 652system.cpu0.decode.DecodedInsts 640747867 # Number of instructions handled by decode 653system.cpu0.decode.SquashedInsts 23352656 # Number of squashed instructions handled by decode 654system.cpu0.rename.SquashCycles 5221222 # Number of cycles rename is squashing 655system.cpu0.rename.IdleCycles 144093047 # Number of cycles rename is idle 656system.cpu0.rename.BlockCycles 59069591 # Number of cycles rename is blocking 657system.cpu0.rename.serializeStallCycles 244366962 # count of cycles rename stalled for serializing inst 658system.cpu0.rename.RunCycles 230957488 # Number of cycles rename is running 659system.cpu0.rename.UnblockCycles 70783351 # Number of cycles rename is unblocking 660system.cpu0.rename.RenamedInsts 623359263 # Number of instructions processed by rename 661system.cpu0.rename.SquashedInsts 6158447 # Number of squashed instructions processed by rename 662system.cpu0.rename.ROBFullEvents 11021555 # Number of times rename has blocked due to ROB full 663system.cpu0.rename.IQFullEvents 440656 # Number of times rename has blocked due to IQ full 664system.cpu0.rename.LQFullEvents 940490 # Number of times rename has blocked due to LQ full 665system.cpu0.rename.SQFullEvents 33921586 # Number of times rename has blocked due to SQ full 666system.cpu0.rename.FullRegisterEvents 11494 # Number of times there has been no free registers 667system.cpu0.rename.RenamedOperands 594689945 # Number of destination operands rename has renamed 668system.cpu0.rename.RenameLookups 962815337 # Number of register rename lookups that rename has made 669system.cpu0.rename.int_rename_lookups 736259751 # Number of integer rename lookups 670system.cpu0.rename.fp_rename_lookups 682623 # Number of floating rename lookups 671system.cpu0.rename.CommittedMaps 536299590 # Number of HB maps that are committed 672system.cpu0.rename.UndoneMaps 58390349 # Number of HB maps that are undone due to squashing 673system.cpu0.rename.serializingInsts 16178274 # count of serializing insts renamed 674system.cpu0.rename.tempSerializingInsts 14135285 # count of temporary serializing insts renamed 675system.cpu0.rename.skidInsts 78489785 # count of insts added to the skid buffer 676system.cpu0.memDep0.insertedLoads 102915286 # Number of loads inserted to the mem dependence unit. 677system.cpu0.memDep0.insertedStores 86617273 # Number of stores inserted to the mem dependence unit. 678system.cpu0.memDep0.conflictingLoads 9593817 # Number of conflicting loads. 679system.cpu0.memDep0.conflictingStores 8133429 # Number of conflicting stores. 680system.cpu0.iq.iqInstsAdded 600294247 # Number of instructions added to the IQ (excludes non-spec) 681system.cpu0.iq.iqNonSpecInstsAdded 16347683 # Number of non-speculative instructions added to the IQ 682system.cpu0.iq.iqInstsIssued 605471525 # Number of instructions issued 683system.cpu0.iq.iqSquashedInstsIssued 2720884 # Number of squashed instructions issued 684system.cpu0.iq.iqSquashedInstsExamined 54918264 # Number of squashed instructions iterated over during squash; mainly for profiling 685system.cpu0.iq.iqSquashedOperandsExamined 35662191 # Number of squashed operands that are examined and possibly removed from graph 686system.cpu0.iq.iqSquashedNonSpecRemoved 285806 # Number of squashed non-spec instructions that were removed 687system.cpu0.iq.issued_per_cycle::samples 754491661 # Number of insts issued each cycle 688system.cpu0.iq.issued_per_cycle::mean 0.802489 # Number of insts issued each cycle 689system.cpu0.iq.issued_per_cycle::stdev 1.061507 # Number of insts issued each cycle 690system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 691system.cpu0.iq.issued_per_cycle::0 423297632 56.10% 56.10% # Number of insts issued each cycle 692system.cpu0.iq.issued_per_cycle::1 139867580 18.54% 74.64% # Number of insts issued each cycle 693system.cpu0.iq.issued_per_cycle::2 116427415 15.43% 90.07% # Number of insts issued each cycle 694system.cpu0.iq.issued_per_cycle::3 66852551 8.86% 98.93% # Number of insts issued each cycle 695system.cpu0.iq.issued_per_cycle::4 8040953 1.07% 100.00% # Number of insts issued each cycle 696system.cpu0.iq.issued_per_cycle::5 5530 0.00% 100.00% # Number of insts issued each cycle 697system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 698system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 699system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 700system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 701system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 702system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 703system.cpu0.iq.issued_per_cycle::total 754491661 # Number of insts issued each cycle 704system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 705system.cpu0.iq.fu_full::IntAlu 62202700 45.10% 45.10% # attempts to use FU when none available 706system.cpu0.iq.fu_full::IntMult 65869 0.05% 45.14% # attempts to use FU when none available 707system.cpu0.iq.fu_full::IntDiv 12866 0.01% 45.15% # attempts to use FU when none available 708system.cpu0.iq.fu_full::FloatAdd 0 0.00% 45.15% # attempts to use FU when none available 709system.cpu0.iq.fu_full::FloatCmp 0 0.00% 45.15% # attempts to use FU when none available 710system.cpu0.iq.fu_full::FloatCvt 0 0.00% 45.15% # attempts to use FU when none available 711system.cpu0.iq.fu_full::FloatMult 0 0.00% 45.15% # attempts to use FU when none available 712system.cpu0.iq.fu_full::FloatDiv 0 0.00% 45.15% # attempts to use FU when none available 713system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 45.15% # attempts to use FU when none available 714system.cpu0.iq.fu_full::SimdAdd 0 0.00% 45.15% # attempts to use FU when none available 715system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 45.15% # attempts to use FU when none available 716system.cpu0.iq.fu_full::SimdAlu 0 0.00% 45.15% # attempts to use FU when none available 717system.cpu0.iq.fu_full::SimdCmp 0 0.00% 45.15% # attempts to use FU when none available 718system.cpu0.iq.fu_full::SimdCvt 0 0.00% 45.15% # attempts to use FU when none available 719system.cpu0.iq.fu_full::SimdMisc 0 0.00% 45.15% # attempts to use FU when none available 720system.cpu0.iq.fu_full::SimdMult 0 0.00% 45.15% # attempts to use FU when none available 721system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 45.15% # attempts to use FU when none available 722system.cpu0.iq.fu_full::SimdShift 0 0.00% 45.15% # attempts to use FU when none available 723system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 45.15% # attempts to use FU when none available 724system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 45.15% # attempts to use FU when none available 725system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 45.15% # attempts to use FU when none available 726system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 45.15% # attempts to use FU when none available 727system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 45.15% # attempts to use FU when none available 728system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 45.15% # attempts to use FU when none available 729system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 45.15% # attempts to use FU when none available 730system.cpu0.iq.fu_full::SimdFloatMisc 27 0.00% 45.15% # attempts to use FU when none available 731system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 45.15% # attempts to use FU when none available 732system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.15% # attempts to use FU when none available 733system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 45.15% # attempts to use FU when none available 734system.cpu0.iq.fu_full::MemRead 36951420 26.79% 71.94% # attempts to use FU when none available 735system.cpu0.iq.fu_full::MemWrite 38701650 28.06% 100.00% # attempts to use FU when none available 736system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 737system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 738system.cpu0.iq.FU_type_0::No_OpClass 51 0.00% 0.00% # Type of FU issued 739system.cpu0.iq.FU_type_0::IntAlu 413123878 68.23% 68.23% # Type of FU issued 740system.cpu0.iq.FU_type_0::IntMult 1535668 0.25% 68.49% # Type of FU issued 741system.cpu0.iq.FU_type_0::IntDiv 80204 0.01% 68.50% # Type of FU issued 742system.cpu0.iq.FU_type_0::FloatAdd 6 0.00% 68.50% # Type of FU issued 743system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 68.50% # Type of FU issued 744system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 68.50% # Type of FU issued 745system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 68.50% # Type of FU issued 746system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 68.50% # Type of FU issued 747system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 68.50% # Type of FU issued 748system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 68.50% # Type of FU issued 749system.cpu0.iq.FU_type_0::SimdAddAcc 1 0.00% 68.50% # Type of FU issued 750system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 68.50% # Type of FU issued 751system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 68.50% # Type of FU issued 752system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 68.50% # Type of FU issued 753system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 68.50% # Type of FU issued 754system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 68.50% # Type of FU issued 755system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 68.50% # Type of FU issued 756system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 68.50% # Type of FU issued 757system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.50% # Type of FU issued 758system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 68.50% # Type of FU issued 759system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.50% # Type of FU issued 760system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.50% # Type of FU issued 761system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.50% # Type of FU issued 762system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.50% # Type of FU issued 763system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.50% # Type of FU issued 764system.cpu0.iq.FU_type_0::SimdFloatMisc 45354 0.01% 68.51% # Type of FU issued 765system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 68.51% # Type of FU issued 766system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.51% # Type of FU issued 767system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.51% # Type of FU issued 768system.cpu0.iq.FU_type_0::MemRead 106103331 17.52% 86.03% # Type of FU issued 769system.cpu0.iq.FU_type_0::MemWrite 84583031 13.97% 100.00% # Type of FU issued 770system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 771system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 772system.cpu0.iq.FU_type_0::total 605471525 # Type of FU issued 773system.cpu0.iq.rate 0.774893 # Inst issue rate 774system.cpu0.iq.fu_busy_cnt 137934532 # FU busy when requested 775system.cpu0.iq.fu_busy_rate 0.227813 # FU busy rate (busy events/executed inst) 776system.cpu0.iq.int_inst_queue_reads 2104985611 # Number of integer instruction queue reads 777system.cpu0.iq.int_inst_queue_writes 671273361 # Number of integer instruction queue writes 778system.cpu0.iq.int_inst_queue_wakeup_accesses 587796479 # Number of integer instruction queue wakeup accesses 779system.cpu0.iq.fp_inst_queue_reads 1104514 # Number of floating instruction queue reads 780system.cpu0.iq.fp_inst_queue_writes 436534 # Number of floating instruction queue writes 781system.cpu0.iq.fp_inst_queue_wakeup_accesses 408765 # Number of floating instruction queue wakeup accesses 782system.cpu0.iq.int_alu_accesses 742719141 # Number of integer alu accesses 783system.cpu0.iq.fp_alu_accesses 686865 # Number of floating point alu accesses 784system.cpu0.iew.lsq.thread0.forwLoads 2818576 # Number of loads that had data forwarded from stores 785system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 786system.cpu0.iew.lsq.thread0.squashedLoads 12827708 # Number of loads squashed 787system.cpu0.iew.lsq.thread0.ignoredResponses 17934 # Number of memory responses ignored because the instruction is squashed 788system.cpu0.iew.lsq.thread0.memOrderViolation 150945 # Number of memory ordering violations 789system.cpu0.iew.lsq.thread0.squashedStores 5597965 # Number of stores squashed 790system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 791system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 792system.cpu0.iew.lsq.thread0.rescheduledLoads 2832815 # Number of loads that were rescheduled 793system.cpu0.iew.lsq.thread0.cacheBlocked 4794177 # Number of times an access to memory failed due to the cache being blocked 794system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle 795system.cpu0.iew.iewSquashCycles 5221222 # Number of cycles IEW is squashing 796system.cpu0.iew.iewBlockCycles 8523162 # Number of cycles IEW is blocking 797system.cpu0.iew.iewUnblockCycles 2018525 # Number of cycles IEW is unblocking 798system.cpu0.iew.iewDispatchedInsts 616773219 # Number of instructions dispatched to IQ 799system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 800system.cpu0.iew.iewDispLoadInsts 102915286 # Number of dispatched load instructions 801system.cpu0.iew.iewDispStoreInsts 86617273 # Number of dispatched store instructions 802system.cpu0.iew.iewDispNonSpecInsts 13889545 # Number of dispatched non-speculative instructions 803system.cpu0.iew.iewIQFullEvents 69101 # Number of times the IQ has become full, causing a stall 804system.cpu0.iew.iewLSQFullEvents 1866975 # Number of times the LSQ has become full, causing a stall 805system.cpu0.iew.memOrderViolationEvents 150945 # Number of memory order violations 806system.cpu0.iew.predictedTakenIncorrect 1955799 # Number of branches that were predicted taken incorrectly 807system.cpu0.iew.predictedNotTakenIncorrect 3092868 # Number of branches that were predicted not taken incorrectly 808system.cpu0.iew.branchMispredicts 5048667 # Number of branch mispredicts detected at execute 809system.cpu0.iew.iewExecutedInsts 597424685 # Number of executed instructions 810system.cpu0.iew.iewExecLoadInsts 102845914 # Number of load instructions executed 811system.cpu0.iew.iewExecSquashedInsts 7413191 # Number of squashed instructions skipped in execute 812system.cpu0.iew.exec_swp 0 # number of swp insts executed 813system.cpu0.iew.exec_nop 131289 # number of nop insts executed 814system.cpu0.iew.exec_refs 186166471 # number of memory reference insts executed 815system.cpu0.iew.exec_branches 112308682 # Number of branches executed 816system.cpu0.iew.exec_stores 83320557 # Number of stores executed 817system.cpu0.iew.exec_rate 0.764594 # Inst execution rate 818system.cpu0.iew.wb_sent 588977240 # cumulative count of insts sent to commit 819system.cpu0.iew.wb_count 588205244 # cumulative count of insts written-back 820system.cpu0.iew.wb_producers 286222957 # num instructions producing a value 821system.cpu0.iew.wb_consumers 469478170 # num instructions consuming a value 822system.cpu0.iew.wb_rate 0.752795 # insts written-back per cycle 823system.cpu0.iew.wb_fanout 0.609662 # average fanout of values written-back 824system.cpu0.commit.commitSquashedInsts 48006701 # The number of squashed insts skipped by commit 825system.cpu0.commit.commitNonSpecStalls 16061877 # The number of times commit has been forced to stall to communicate backwards 826system.cpu0.commit.branchMispredicts 4699541 # The number of times a branch was mispredicted 827system.cpu0.commit.committed_per_cycle::samples 745382545 # Number of insts commited each cycle 828system.cpu0.commit.committed_per_cycle::mean 0.753605 # Number of insts commited each cycle 829system.cpu0.commit.committed_per_cycle::stdev 1.560188 # Number of insts commited each cycle 830system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 831system.cpu0.commit.committed_per_cycle::0 499589625 67.02% 67.02% # Number of insts commited each cycle 832system.cpu0.commit.committed_per_cycle::1 127846284 17.15% 84.18% # Number of insts commited each cycle 833system.cpu0.commit.committed_per_cycle::2 54154407 7.27% 91.44% # Number of insts commited each cycle 834system.cpu0.commit.committed_per_cycle::3 18022208 2.42% 93.86% # Number of insts commited each cycle 835system.cpu0.commit.committed_per_cycle::4 12958039 1.74% 95.60% # Number of insts commited each cycle 836system.cpu0.commit.committed_per_cycle::5 8991225 1.21% 96.80% # Number of insts commited each cycle 837system.cpu0.commit.committed_per_cycle::6 6101110 0.82% 97.62% # Number of insts commited each cycle 838system.cpu0.commit.committed_per_cycle::7 3650180 0.49% 98.11% # Number of insts commited each cycle 839system.cpu0.commit.committed_per_cycle::8 14069467 1.89% 100.00% # Number of insts commited each cycle 840system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 841system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 842system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 843system.cpu0.commit.committed_per_cycle::total 745382545 # Number of insts commited each cycle 844system.cpu0.commit.committedInsts 478330111 # Number of instructions committed 845system.cpu0.commit.committedOps 561723659 # Number of ops (including micro ops) committed 846system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed 847system.cpu0.commit.refs 171106885 # Number of memory references committed 848system.cpu0.commit.loads 90087577 # Number of loads committed 849system.cpu0.commit.membars 3940521 # Number of memory barriers committed 850system.cpu0.commit.branches 106744395 # Number of branches committed 851system.cpu0.commit.fp_insts 400838 # Number of committed floating point instructions. 852system.cpu0.commit.int_insts 515553500 # Number of committed integer instructions. 853system.cpu0.commit.function_calls 14275050 # Number of function calls committed. 854system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 855system.cpu0.commit.op_class_0::IntAlu 389225467 69.29% 69.29% # Class of committed instruction 856system.cpu0.commit.op_class_0::IntMult 1288146 0.23% 69.52% # Class of committed instruction 857system.cpu0.commit.op_class_0::IntDiv 63590 0.01% 69.53% # Class of committed instruction 858system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 69.53% # Class of committed instruction 859system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 69.53% # Class of committed instruction 860system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 69.53% # Class of committed instruction 861system.cpu0.commit.op_class_0::FloatMult 0 0.00% 69.53% # Class of committed instruction 862system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 69.53% # Class of committed instruction 863system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 69.53% # Class of committed instruction 864system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 69.53% # Class of committed instruction 865system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 69.53% # Class of committed instruction 866system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 69.53% # Class of committed instruction 867system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 69.53% # Class of committed instruction 868system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 69.53% # Class of committed instruction 869system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 69.53% # Class of committed instruction 870system.cpu0.commit.op_class_0::SimdMult 0 0.00% 69.53% # Class of committed instruction 871system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 69.53% # Class of committed instruction 872system.cpu0.commit.op_class_0::SimdShift 0 0.00% 69.53% # Class of committed instruction 873system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 69.53% # Class of committed instruction 874system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 69.53% # Class of committed instruction 875system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 69.53% # Class of committed instruction 876system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 69.53% # Class of committed instruction 877system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 69.53% # Class of committed instruction 878system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 69.53% # Class of committed instruction 879system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 69.53% # Class of committed instruction 880system.cpu0.commit.op_class_0::SimdFloatMisc 39571 0.01% 69.54% # Class of committed instruction 881system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 69.54% # Class of committed instruction 882system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.54% # Class of committed instruction 883system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.54% # Class of committed instruction 884system.cpu0.commit.op_class_0::MemRead 90087577 16.04% 85.58% # Class of committed instruction 885system.cpu0.commit.op_class_0::MemWrite 81019308 14.42% 100.00% # Class of committed instruction 886system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 887system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 888system.cpu0.commit.op_class_0::total 561723659 # Class of committed instruction 889system.cpu0.commit.bw_lim_events 14069467 # number cycles where commit BW limit reached 890system.cpu0.rob.rob_reads 1336864700 # The number of ROB reads 891system.cpu0.rob.rob_writes 1228532736 # The number of ROB writes 892system.cpu0.timesIdled 1001309 # Number of times that the entire CPU went into an idle state and unscheduled itself 893system.cpu0.idleCycles 26869869 # Total number of cycles that the CPU has spent unscheduled due to idling 894system.cpu0.quiesceCycles 93988523944 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 895system.cpu0.committedInsts 478330111 # Number of Instructions Simulated 896system.cpu0.committedOps 561723659 # Number of Ops (including micro ops) Simulated 897system.cpu0.cpi 1.633519 # CPI: Cycles Per Instruction 898system.cpu0.cpi_total 1.633519 # CPI: Total CPI of All Threads 899system.cpu0.ipc 0.612175 # IPC: Instructions Per Cycle 900system.cpu0.ipc_total 0.612175 # IPC: Total IPC of All Threads 901system.cpu0.int_regfile_reads 705719528 # number of integer regfile reads 902system.cpu0.int_regfile_writes 419138035 # number of integer regfile writes 903system.cpu0.fp_regfile_reads 669802 # number of floating regfile reads 904system.cpu0.fp_regfile_writes 321532 # number of floating regfile writes 905system.cpu0.cc_regfile_reads 129631161 # number of cc regfile reads 906system.cpu0.cc_regfile_writes 130314957 # number of cc regfile writes 907system.cpu0.misc_regfile_reads 1341639409 # number of misc regfile reads 908system.cpu0.misc_regfile_writes 16172326 # number of misc regfile writes 909system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 910system.cpu0.dcache.tags.replacements 6359267 # number of replacements 911system.cpu0.dcache.tags.tagsinuse 478.495579 # Cycle average of tags in use 912system.cpu0.dcache.tags.total_refs 158196405 # Total number of references to valid blocks. 913system.cpu0.dcache.tags.sampled_refs 6359779 # Sample count of references to valid blocks. 914system.cpu0.dcache.tags.avg_refs 24.874513 # Average number of references to valid blocks. 915system.cpu0.dcache.tags.warmup_cycle 2049282000 # Cycle when the warmup percentage was hit. 916system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.495579 # Average occupied blocks per requestor 917system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934562 # Average percentage of cache occupancy 918system.cpu0.dcache.tags.occ_percent::total 0.934562 # Average percentage of cache occupancy 919system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 920system.cpu0.dcache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 921system.cpu0.dcache.tags.age_task_id_blocks_1024::1 386 # Occupied blocks per task id 922system.cpu0.dcache.tags.age_task_id_blocks_1024::2 32 # Occupied blocks per task id 923system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id 924system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 925system.cpu0.dcache.tags.tag_accesses 355337560 # Number of tag accesses 926system.cpu0.dcache.tags.data_accesses 355337560 # Number of data accesses 927system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 928system.cpu0.dcache.ReadReq_hits::cpu0.data 83119639 # number of ReadReq hits 929system.cpu0.dcache.ReadReq_hits::total 83119639 # number of ReadReq hits 930system.cpu0.dcache.WriteReq_hits::cpu0.data 70042361 # number of WriteReq hits 931system.cpu0.dcache.WriteReq_hits::total 70042361 # number of WriteReq hits 932system.cpu0.dcache.SoftPFReq_hits::cpu0.data 205739 # number of SoftPFReq hits 933system.cpu0.dcache.SoftPFReq_hits::total 205739 # number of SoftPFReq hits 934system.cpu0.dcache.WriteLineReq_hits::cpu0.data 143941 # number of WriteLineReq hits 935system.cpu0.dcache.WriteLineReq_hits::total 143941 # number of WriteLineReq hits 936system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1893040 # number of LoadLockedReq hits 937system.cpu0.dcache.LoadLockedReq_hits::total 1893040 # number of LoadLockedReq hits 938system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1948071 # number of StoreCondReq hits 939system.cpu0.dcache.StoreCondReq_hits::total 1948071 # number of StoreCondReq hits 940system.cpu0.dcache.demand_hits::cpu0.data 153305941 # number of demand (read+write) hits 941system.cpu0.dcache.demand_hits::total 153305941 # number of demand (read+write) hits 942system.cpu0.dcache.overall_hits::cpu0.data 153511680 # number of overall hits 943system.cpu0.dcache.overall_hits::total 153511680 # number of overall hits 944system.cpu0.dcache.ReadReq_misses::cpu0.data 7167523 # number of ReadReq misses 945system.cpu0.dcache.ReadReq_misses::total 7167523 # number of ReadReq misses 946system.cpu0.dcache.WriteReq_misses::cpu0.data 7883078 # number of WriteReq misses 947system.cpu0.dcache.WriteReq_misses::total 7883078 # number of WriteReq misses 948system.cpu0.dcache.SoftPFReq_misses::cpu0.data 755741 # number of SoftPFReq misses 949system.cpu0.dcache.SoftPFReq_misses::total 755741 # number of SoftPFReq misses 950system.cpu0.dcache.WriteLineReq_misses::cpu0.data 796292 # number of WriteLineReq misses 951system.cpu0.dcache.WriteLineReq_misses::total 796292 # number of WriteLineReq misses 952system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 289192 # number of LoadLockedReq misses 953system.cpu0.dcache.LoadLockedReq_misses::total 289192 # number of LoadLockedReq misses 954system.cpu0.dcache.StoreCondReq_misses::cpu0.data 197314 # number of StoreCondReq misses 955system.cpu0.dcache.StoreCondReq_misses::total 197314 # number of StoreCondReq misses 956system.cpu0.dcache.demand_misses::cpu0.data 15846893 # number of demand (read+write) misses 957system.cpu0.dcache.demand_misses::total 15846893 # number of demand (read+write) misses 958system.cpu0.dcache.overall_misses::cpu0.data 16602634 # number of overall misses 959system.cpu0.dcache.overall_misses::total 16602634 # number of overall misses 960system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 116616484000 # number of ReadReq miss cycles 961system.cpu0.dcache.ReadReq_miss_latency::total 116616484000 # number of ReadReq miss cycles 962system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 160918615442 # number of WriteReq miss cycles 963system.cpu0.dcache.WriteReq_miss_latency::total 160918615442 # number of WriteReq miss cycles 964system.cpu0.dcache.WriteLineReq_miss_latency::cpu0.data 30600076090 # number of WriteLineReq miss cycles 965system.cpu0.dcache.WriteLineReq_miss_latency::total 30600076090 # number of WriteLineReq miss cycles 966system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 4458676000 # number of LoadLockedReq miss cycles 967system.cpu0.dcache.LoadLockedReq_miss_latency::total 4458676000 # number of LoadLockedReq miss cycles 968system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 4713253000 # number of StoreCondReq miss cycles 969system.cpu0.dcache.StoreCondReq_miss_latency::total 4713253000 # number of StoreCondReq miss cycles 970system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 2519000 # number of StoreCondFailReq miss cycles 971system.cpu0.dcache.StoreCondFailReq_miss_latency::total 2519000 # number of StoreCondFailReq miss cycles 972system.cpu0.dcache.demand_miss_latency::cpu0.data 308135175532 # number of demand (read+write) miss cycles 973system.cpu0.dcache.demand_miss_latency::total 308135175532 # number of demand (read+write) miss cycles 974system.cpu0.dcache.overall_miss_latency::cpu0.data 308135175532 # number of overall miss cycles 975system.cpu0.dcache.overall_miss_latency::total 308135175532 # number of overall miss cycles 976system.cpu0.dcache.ReadReq_accesses::cpu0.data 90287162 # number of ReadReq accesses(hits+misses) 977system.cpu0.dcache.ReadReq_accesses::total 90287162 # number of ReadReq accesses(hits+misses) 978system.cpu0.dcache.WriteReq_accesses::cpu0.data 77925439 # number of WriteReq accesses(hits+misses) 979system.cpu0.dcache.WriteReq_accesses::total 77925439 # number of WriteReq accesses(hits+misses) 980system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 961480 # number of SoftPFReq accesses(hits+misses) 981system.cpu0.dcache.SoftPFReq_accesses::total 961480 # number of SoftPFReq accesses(hits+misses) 982system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 940233 # number of WriteLineReq accesses(hits+misses) 983system.cpu0.dcache.WriteLineReq_accesses::total 940233 # number of WriteLineReq accesses(hits+misses) 984system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 2182232 # number of LoadLockedReq accesses(hits+misses) 985system.cpu0.dcache.LoadLockedReq_accesses::total 2182232 # number of LoadLockedReq accesses(hits+misses) 986system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 2145385 # number of StoreCondReq accesses(hits+misses) 987system.cpu0.dcache.StoreCondReq_accesses::total 2145385 # number of StoreCondReq accesses(hits+misses) 988system.cpu0.dcache.demand_accesses::cpu0.data 169152834 # number of demand (read+write) accesses 989system.cpu0.dcache.demand_accesses::total 169152834 # number of demand (read+write) accesses 990system.cpu0.dcache.overall_accesses::cpu0.data 170114314 # number of overall (read+write) accesses 991system.cpu0.dcache.overall_accesses::total 170114314 # number of overall (read+write) accesses 992system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.079386 # miss rate for ReadReq accesses 993system.cpu0.dcache.ReadReq_miss_rate::total 0.079386 # miss rate for ReadReq accesses 994system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.101162 # miss rate for WriteReq accesses 995system.cpu0.dcache.WriteReq_miss_rate::total 0.101162 # miss rate for WriteReq accesses 996system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.786018 # miss rate for SoftPFReq accesses 997system.cpu0.dcache.SoftPFReq_miss_rate::total 0.786018 # miss rate for SoftPFReq accesses 998system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.846909 # miss rate for WriteLineReq accesses 999system.cpu0.dcache.WriteLineReq_miss_rate::total 0.846909 # miss rate for WriteLineReq accesses 1000system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.132521 # miss rate for LoadLockedReq accesses 1001system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.132521 # miss rate for LoadLockedReq accesses 1002system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.091971 # miss rate for StoreCondReq accesses 1003system.cpu0.dcache.StoreCondReq_miss_rate::total 0.091971 # miss rate for StoreCondReq accesses 1004system.cpu0.dcache.demand_miss_rate::cpu0.data 0.093684 # miss rate for demand accesses 1005system.cpu0.dcache.demand_miss_rate::total 0.093684 # miss rate for demand accesses 1006system.cpu0.dcache.overall_miss_rate::cpu0.data 0.097597 # miss rate for overall accesses 1007system.cpu0.dcache.overall_miss_rate::total 0.097597 # miss rate for overall accesses 1008system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 16270.123444 # average ReadReq miss latency 1009system.cpu0.dcache.ReadReq_avg_miss_latency::total 16270.123444 # average ReadReq miss latency 1010system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20413.170521 # average WriteReq miss latency 1011system.cpu0.dcache.WriteReq_avg_miss_latency::total 20413.170521 # average WriteReq miss latency 1012system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu0.data 38428.209865 # average WriteLineReq miss latency 1013system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 38428.209865 # average WriteLineReq miss latency 1014system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15417.701734 # average LoadLockedReq miss latency 1015system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15417.701734 # average LoadLockedReq miss latency 1016system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23887.068328 # average StoreCondReq miss latency 1017system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23887.068328 # average StoreCondReq miss latency 1018system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency 1019system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 1020system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19444.516697 # average overall miss latency 1021system.cpu0.dcache.demand_avg_miss_latency::total 19444.516697 # average overall miss latency 1022system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 18559.415062 # average overall miss latency 1023system.cpu0.dcache.overall_avg_miss_latency::total 18559.415062 # average overall miss latency 1024system.cpu0.dcache.blocked_cycles::no_mshrs 9297521 # number of cycles access was blocked 1025system.cpu0.dcache.blocked_cycles::no_targets 24817691 # number of cycles access was blocked 1026system.cpu0.dcache.blocked::no_mshrs 744023 # number of cycles access was blocked 1027system.cpu0.dcache.blocked::no_targets 779199 # number of cycles access was blocked 1028system.cpu0.dcache.avg_blocked_cycles::no_mshrs 12.496282 # average number of cycles each access was blocked 1029system.cpu0.dcache.avg_blocked_cycles::no_targets 31.850260 # average number of cycles each access was blocked 1030system.cpu0.dcache.writebacks::writebacks 6359403 # number of writebacks 1031system.cpu0.dcache.writebacks::total 6359403 # number of writebacks 1032system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 3686639 # number of ReadReq MSHR hits 1033system.cpu0.dcache.ReadReq_mshr_hits::total 3686639 # number of ReadReq MSHR hits 1034system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 6327255 # number of WriteReq MSHR hits 1035system.cpu0.dcache.WriteReq_mshr_hits::total 6327255 # number of WriteReq MSHR hits 1036system.cpu0.dcache.WriteLineReq_mshr_hits::cpu0.data 4271 # number of WriteLineReq MSHR hits 1037system.cpu0.dcache.WriteLineReq_mshr_hits::total 4271 # number of WriteLineReq MSHR hits 1038system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 148971 # number of LoadLockedReq MSHR hits 1039system.cpu0.dcache.LoadLockedReq_mshr_hits::total 148971 # number of LoadLockedReq MSHR hits 1040system.cpu0.dcache.demand_mshr_hits::cpu0.data 10018165 # number of demand (read+write) MSHR hits 1041system.cpu0.dcache.demand_mshr_hits::total 10018165 # number of demand (read+write) MSHR hits 1042system.cpu0.dcache.overall_mshr_hits::cpu0.data 10018165 # number of overall MSHR hits 1043system.cpu0.dcache.overall_mshr_hits::total 10018165 # number of overall MSHR hits 1044system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 3480884 # number of ReadReq MSHR misses 1045system.cpu0.dcache.ReadReq_mshr_misses::total 3480884 # number of ReadReq MSHR misses 1046system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1555823 # number of WriteReq MSHR misses 1047system.cpu0.dcache.WriteReq_mshr_misses::total 1555823 # number of WriteReq MSHR misses 1048system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 748893 # number of SoftPFReq MSHR misses 1049system.cpu0.dcache.SoftPFReq_mshr_misses::total 748893 # number of SoftPFReq MSHR misses 1050system.cpu0.dcache.WriteLineReq_mshr_misses::cpu0.data 792021 # number of WriteLineReq MSHR misses 1051system.cpu0.dcache.WriteLineReq_mshr_misses::total 792021 # number of WriteLineReq MSHR misses 1052system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 140221 # number of LoadLockedReq MSHR misses 1053system.cpu0.dcache.LoadLockedReq_mshr_misses::total 140221 # number of LoadLockedReq MSHR misses 1054system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 197311 # number of StoreCondReq MSHR misses 1055system.cpu0.dcache.StoreCondReq_mshr_misses::total 197311 # number of StoreCondReq MSHR misses 1056system.cpu0.dcache.demand_mshr_misses::cpu0.data 5828728 # number of demand (read+write) MSHR misses 1057system.cpu0.dcache.demand_mshr_misses::total 5828728 # number of demand (read+write) MSHR misses 1058system.cpu0.dcache.overall_mshr_misses::cpu0.data 6577621 # number of overall MSHR misses 1059system.cpu0.dcache.overall_mshr_misses::total 6577621 # number of overall MSHR misses 1060system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 16980 # number of ReadReq MSHR uncacheable 1061system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16980 # number of ReadReq MSHR uncacheable 1062system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 18801 # number of WriteReq MSHR uncacheable 1063system.cpu0.dcache.WriteReq_mshr_uncacheable::total 18801 # number of WriteReq MSHR uncacheable 1064system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 35781 # number of overall MSHR uncacheable misses 1065system.cpu0.dcache.overall_mshr_uncacheable_misses::total 35781 # number of overall MSHR uncacheable misses 1066system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 53164892500 # number of ReadReq MSHR miss cycles 1067system.cpu0.dcache.ReadReq_mshr_miss_latency::total 53164892500 # number of ReadReq MSHR miss cycles 1068system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 34944889021 # number of WriteReq MSHR miss cycles 1069system.cpu0.dcache.WriteReq_mshr_miss_latency::total 34944889021 # number of WriteReq MSHR miss cycles 1070system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 18458336500 # number of SoftPFReq MSHR miss cycles 1071system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 18458336500 # number of SoftPFReq MSHR miss cycles 1072system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu0.data 29638184090 # number of WriteLineReq MSHR miss cycles 1073system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 29638184090 # number of WriteLineReq MSHR miss cycles 1074system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1982757000 # number of LoadLockedReq MSHR miss cycles 1075system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1982757000 # number of LoadLockedReq MSHR miss cycles 1076system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 4516003000 # number of StoreCondReq MSHR miss cycles 1077system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 4516003000 # number of StoreCondReq MSHR miss cycles 1078system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2458000 # number of StoreCondFailReq MSHR miss cycles 1079system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2458000 # number of StoreCondFailReq MSHR miss cycles 1080system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 117747965611 # number of demand (read+write) MSHR miss cycles 1081system.cpu0.dcache.demand_mshr_miss_latency::total 117747965611 # number of demand (read+write) MSHR miss cycles 1082system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 136206302111 # number of overall MSHR miss cycles 1083system.cpu0.dcache.overall_mshr_miss_latency::total 136206302111 # number of overall MSHR miss cycles 1084system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3133590500 # number of ReadReq MSHR uncacheable cycles 1085system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3133590500 # number of ReadReq MSHR uncacheable cycles 1086system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3133590500 # number of overall MSHR uncacheable cycles 1087system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3133590500 # number of overall MSHR uncacheable cycles 1088system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.038553 # mshr miss rate for ReadReq accesses 1089system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.038553 # mshr miss rate for ReadReq accesses 1090system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019966 # mshr miss rate for WriteReq accesses 1091system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019966 # mshr miss rate for WriteReq accesses 1092system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.778896 # mshr miss rate for SoftPFReq accesses 1093system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.778896 # mshr miss rate for SoftPFReq accesses 1094system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu0.data 0.842367 # mshr miss rate for WriteLineReq accesses 1095system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.842367 # mshr miss rate for WriteLineReq accesses 1096system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.064256 # mshr miss rate for LoadLockedReq accesses 1097system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064256 # mshr miss rate for LoadLockedReq accesses 1098system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.091970 # mshr miss rate for StoreCondReq accesses 1099system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.091970 # mshr miss rate for StoreCondReq accesses 1100system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.034458 # mshr miss rate for demand accesses 1101system.cpu0.dcache.demand_mshr_miss_rate::total 0.034458 # mshr miss rate for demand accesses 1102system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.038666 # mshr miss rate for overall accesses 1103system.cpu0.dcache.overall_mshr_miss_rate::total 0.038666 # mshr miss rate for overall accesses 1104system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 15273.388168 # average ReadReq mshr miss latency 1105system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 15273.388168 # average ReadReq mshr miss latency 1106system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22460.709876 # average WriteReq mshr miss latency 1107system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22460.709876 # average WriteReq mshr miss latency 1108system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 24647.495036 # average SoftPFReq mshr miss latency 1109system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 24647.495036 # average SoftPFReq mshr miss latency 1110system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu0.data 37420.957386 # average WriteLineReq mshr miss latency 1111system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 37420.957386 # average WriteLineReq mshr miss latency 1112system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14140.228639 # average LoadLockedReq mshr miss latency 1113system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14140.228639 # average LoadLockedReq mshr miss latency 1114system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22887.740673 # average StoreCondReq mshr miss latency 1115system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22887.740673 # average StoreCondReq mshr miss latency 1116system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency 1117system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 1118system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20201.314182 # average overall mshr miss latency 1119system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20201.314182 # average overall mshr miss latency 1120system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20707.532725 # average overall mshr miss latency 1121system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20707.532725 # average overall mshr miss latency 1122system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 184545.965842 # average ReadReq mshr uncacheable latency 1123system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 184545.965842 # average ReadReq mshr uncacheable latency 1124system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 87576.940276 # average overall mshr uncacheable latency 1125system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 87576.940276 # average overall mshr uncacheable latency 1126system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 1127system.cpu0.icache.tags.replacements 6086800 # number of replacements 1128system.cpu0.icache.tags.tagsinuse 511.960315 # Cycle average of tags in use 1129system.cpu0.icache.tags.total_refs 213393241 # Total number of references to valid blocks. 1130system.cpu0.icache.tags.sampled_refs 6087312 # Sample count of references to valid blocks. 1131system.cpu0.icache.tags.avg_refs 35.055414 # Average number of references to valid blocks. 1132system.cpu0.icache.tags.warmup_cycle 13476237000 # Cycle when the warmup percentage was hit. 1133system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.960315 # Average occupied blocks per requestor 1134system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999922 # Average percentage of cache occupancy 1135system.cpu0.icache.tags.occ_percent::total 0.999922 # Average percentage of cache occupancy 1136system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 1137system.cpu0.icache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id 1138system.cpu0.icache.tags.age_task_id_blocks_1024::1 315 # Occupied blocks per task id 1139system.cpu0.icache.tags.age_task_id_blocks_1024::2 84 # Occupied blocks per task id 1140system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 1141system.cpu0.icache.tags.tag_accesses 445759262 # Number of tag accesses 1142system.cpu0.icache.tags.data_accesses 445759262 # Number of data accesses 1143system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 1144system.cpu0.icache.ReadReq_hits::cpu0.inst 213393241 # number of ReadReq hits 1145system.cpu0.icache.ReadReq_hits::total 213393241 # number of ReadReq hits 1146system.cpu0.icache.demand_hits::cpu0.inst 213393241 # number of demand (read+write) hits 1147system.cpu0.icache.demand_hits::total 213393241 # number of demand (read+write) hits 1148system.cpu0.icache.overall_hits::cpu0.inst 213393241 # number of overall hits 1149system.cpu0.icache.overall_hits::total 213393241 # number of overall hits 1150system.cpu0.icache.ReadReq_misses::cpu0.inst 6442715 # number of ReadReq misses 1151system.cpu0.icache.ReadReq_misses::total 6442715 # number of ReadReq misses 1152system.cpu0.icache.demand_misses::cpu0.inst 6442715 # number of demand (read+write) misses 1153system.cpu0.icache.demand_misses::total 6442715 # number of demand (read+write) misses 1154system.cpu0.icache.overall_misses::cpu0.inst 6442715 # number of overall misses 1155system.cpu0.icache.overall_misses::total 6442715 # number of overall misses 1156system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 71477790896 # number of ReadReq miss cycles 1157system.cpu0.icache.ReadReq_miss_latency::total 71477790896 # number of ReadReq miss cycles 1158system.cpu0.icache.demand_miss_latency::cpu0.inst 71477790896 # number of demand (read+write) miss cycles 1159system.cpu0.icache.demand_miss_latency::total 71477790896 # number of demand (read+write) miss cycles 1160system.cpu0.icache.overall_miss_latency::cpu0.inst 71477790896 # number of overall miss cycles 1161system.cpu0.icache.overall_miss_latency::total 71477790896 # number of overall miss cycles 1162system.cpu0.icache.ReadReq_accesses::cpu0.inst 219835956 # number of ReadReq accesses(hits+misses) 1163system.cpu0.icache.ReadReq_accesses::total 219835956 # number of ReadReq accesses(hits+misses) 1164system.cpu0.icache.demand_accesses::cpu0.inst 219835956 # number of demand (read+write) accesses 1165system.cpu0.icache.demand_accesses::total 219835956 # number of demand (read+write) accesses 1166system.cpu0.icache.overall_accesses::cpu0.inst 219835956 # number of overall (read+write) accesses 1167system.cpu0.icache.overall_accesses::total 219835956 # number of overall (read+write) accesses 1168system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.029307 # miss rate for ReadReq accesses 1169system.cpu0.icache.ReadReq_miss_rate::total 0.029307 # miss rate for ReadReq accesses 1170system.cpu0.icache.demand_miss_rate::cpu0.inst 0.029307 # miss rate for demand accesses 1171system.cpu0.icache.demand_miss_rate::total 0.029307 # miss rate for demand accesses 1172system.cpu0.icache.overall_miss_rate::cpu0.inst 0.029307 # miss rate for overall accesses 1173system.cpu0.icache.overall_miss_rate::total 0.029307 # miss rate for overall accesses 1174system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 11094.358651 # average ReadReq miss latency 1175system.cpu0.icache.ReadReq_avg_miss_latency::total 11094.358651 # average ReadReq miss latency 1176system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 11094.358651 # average overall miss latency 1177system.cpu0.icache.demand_avg_miss_latency::total 11094.358651 # average overall miss latency 1178system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 11094.358651 # average overall miss latency 1179system.cpu0.icache.overall_avg_miss_latency::total 11094.358651 # average overall miss latency 1180system.cpu0.icache.blocked_cycles::no_mshrs 10557387 # number of cycles access was blocked 1181system.cpu0.icache.blocked_cycles::no_targets 2753 # number of cycles access was blocked 1182system.cpu0.icache.blocked::no_mshrs 752829 # number of cycles access was blocked 1183system.cpu0.icache.blocked::no_targets 14 # number of cycles access was blocked 1184system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.023619 # average number of cycles each access was blocked 1185system.cpu0.icache.avg_blocked_cycles::no_targets 196.642857 # average number of cycles each access was blocked 1186system.cpu0.icache.writebacks::writebacks 6086800 # number of writebacks 1187system.cpu0.icache.writebacks::total 6086800 # number of writebacks 1188system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 355365 # number of ReadReq MSHR hits 1189system.cpu0.icache.ReadReq_mshr_hits::total 355365 # number of ReadReq MSHR hits 1190system.cpu0.icache.demand_mshr_hits::cpu0.inst 355365 # number of demand (read+write) MSHR hits 1191system.cpu0.icache.demand_mshr_hits::total 355365 # number of demand (read+write) MSHR hits 1192system.cpu0.icache.overall_mshr_hits::cpu0.inst 355365 # number of overall MSHR hits 1193system.cpu0.icache.overall_mshr_hits::total 355365 # number of overall MSHR hits 1194system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 6087350 # number of ReadReq MSHR misses 1195system.cpu0.icache.ReadReq_mshr_misses::total 6087350 # number of ReadReq MSHR misses 1196system.cpu0.icache.demand_mshr_misses::cpu0.inst 6087350 # number of demand (read+write) MSHR misses 1197system.cpu0.icache.demand_mshr_misses::total 6087350 # number of demand (read+write) MSHR misses 1198system.cpu0.icache.overall_mshr_misses::cpu0.inst 6087350 # number of overall MSHR misses 1199system.cpu0.icache.overall_mshr_misses::total 6087350 # number of overall MSHR misses 1200system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1201system.cpu0.icache.ReadReq_mshr_uncacheable::total 21293 # number of ReadReq MSHR uncacheable 1202system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1203system.cpu0.icache.overall_mshr_uncacheable_misses::total 21293 # number of overall MSHR uncacheable misses 1204system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 64448796094 # number of ReadReq MSHR miss cycles 1205system.cpu0.icache.ReadReq_mshr_miss_latency::total 64448796094 # number of ReadReq MSHR miss cycles 1206system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 64448796094 # number of demand (read+write) MSHR miss cycles 1207system.cpu0.icache.demand_mshr_miss_latency::total 64448796094 # number of demand (read+write) MSHR miss cycles 1208system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 64448796094 # number of overall MSHR miss cycles 1209system.cpu0.icache.overall_mshr_miss_latency::total 64448796094 # number of overall MSHR miss cycles 1210system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of ReadReq MSHR uncacheable cycles 1211system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 2027158498 # number of ReadReq MSHR uncacheable cycles 1212system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 2027158498 # number of overall MSHR uncacheable cycles 1213system.cpu0.icache.overall_mshr_uncacheable_latency::total 2027158498 # number of overall MSHR uncacheable cycles 1214system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for ReadReq accesses 1215system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027690 # mshr miss rate for ReadReq accesses 1216system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for demand accesses 1217system.cpu0.icache.demand_mshr_miss_rate::total 0.027690 # mshr miss rate for demand accesses 1218system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027690 # mshr miss rate for overall accesses 1219system.cpu0.icache.overall_mshr_miss_rate::total 0.027690 # mshr miss rate for overall accesses 1220system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average ReadReq mshr miss latency 1221system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10587.332106 # average ReadReq mshr miss latency 1222system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average overall mshr miss latency 1223system.cpu0.icache.demand_avg_mshr_miss_latency::total 10587.332106 # average overall mshr miss latency 1224system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10587.332106 # average overall mshr miss latency 1225system.cpu0.icache.overall_avg_mshr_miss_latency::total 10587.332106 # average overall mshr miss latency 1226system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average ReadReq mshr uncacheable latency 1227system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 95203.047856 # average ReadReq mshr uncacheable latency 1228system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 95203.047856 # average overall mshr uncacheable latency 1229system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 95203.047856 # average overall mshr uncacheable latency 1230system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 1231system.cpu0.l2cache.prefetcher.num_hwpf_issued 8595677 # number of hwpf issued 1232system.cpu0.l2cache.prefetcher.pfIdentified 8603285 # number of prefetch candidates identified 1233system.cpu0.l2cache.prefetcher.pfBufferHit 6909 # number of redundant prefetches already in prefetch queue 1234system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 1235system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 1236system.cpu0.l2cache.prefetcher.pfSpanPage 1123339 # number of prefetches not generated due to page crossing 1237system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 1238system.cpu0.l2cache.tags.replacements 2781248 # number of replacements 1239system.cpu0.l2cache.tags.tagsinuse 15839.093178 # Cycle average of tags in use 1240system.cpu0.l2cache.tags.total_refs 10966307 # Total number of references to valid blocks. 1241system.cpu0.l2cache.tags.sampled_refs 2797118 # Sample count of references to valid blocks. 1242system.cpu0.l2cache.tags.avg_refs 3.920574 # Average number of references to valid blocks. 1243system.cpu0.l2cache.tags.warmup_cycle 2357977000 # Cycle when the warmup percentage was hit. 1244system.cpu0.l2cache.tags.occ_blocks::writebacks 15519.164563 # Average occupied blocks per requestor 1245system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 33.011471 # Average occupied blocks per requestor 1246system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 18.049668 # Average occupied blocks per requestor 1247system.cpu0.l2cache.tags.occ_blocks::cpu0.data 0.000001 # Average occupied blocks per requestor 1248system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 268.867475 # Average occupied blocks per requestor 1249system.cpu0.l2cache.tags.occ_percent::writebacks 0.947215 # Average percentage of cache occupancy 1250system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002015 # Average percentage of cache occupancy 1251system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.001102 # Average percentage of cache occupancy 1252system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.000000 # Average percentage of cache occupancy 1253system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.016410 # Average percentage of cache occupancy 1254system.cpu0.l2cache.tags.occ_percent::total 0.966742 # Average percentage of cache occupancy 1255system.cpu0.l2cache.tags.occ_task_id_blocks::1022 337 # Occupied blocks per task id 1256system.cpu0.l2cache.tags.occ_task_id_blocks::1023 83 # Occupied blocks per task id 1257system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15450 # Occupied blocks per task id 1258system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 2 # Occupied blocks per task id 1259system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 131 # Occupied blocks per task id 1260system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 116 # Occupied blocks per task id 1261system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 88 # Occupied blocks per task id 1262system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id 1263system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id 1264system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 44 # Occupied blocks per task id 1265system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 1266system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 20 # Occupied blocks per task id 1267system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 205 # Occupied blocks per task id 1268system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1708 # Occupied blocks per task id 1269system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7197 # Occupied blocks per task id 1270system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4776 # Occupied blocks per task id 1271system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1564 # Occupied blocks per task id 1272system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.020569 # Percentage of cache occupancy per task id 1273system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.005066 # Percentage of cache occupancy per task id 1274system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.942993 # Percentage of cache occupancy per task id 1275system.cpu0.l2cache.tags.tag_accesses 434183760 # Number of tag accesses 1276system.cpu0.l2cache.tags.data_accesses 434183760 # Number of data accesses 1277system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 1278system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 639992 # number of ReadReq hits 1279system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 185315 # number of ReadReq hits 1280system.cpu0.l2cache.ReadReq_hits::total 825307 # number of ReadReq hits 1281system.cpu0.l2cache.WritebackDirty_hits::writebacks 4159646 # number of WritebackDirty hits 1282system.cpu0.l2cache.WritebackDirty_hits::total 4159646 # number of WritebackDirty hits 1283system.cpu0.l2cache.WritebackClean_hits::writebacks 8284827 # number of WritebackClean hits 1284system.cpu0.l2cache.WritebackClean_hits::total 8284827 # number of WritebackClean hits 1285system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 23 # number of UpgradeReq hits 1286system.cpu0.l2cache.UpgradeReq_hits::total 23 # number of UpgradeReq hits 1287system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 2 # number of SCUpgradeReq hits 1288system.cpu0.l2cache.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits 1289system.cpu0.l2cache.ReadExReq_hits::cpu0.data 995756 # number of ReadExReq hits 1290system.cpu0.l2cache.ReadExReq_hits::total 995756 # number of ReadExReq hits 1291system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 5493946 # number of ReadCleanReq hits 1292system.cpu0.l2cache.ReadCleanReq_hits::total 5493946 # number of ReadCleanReq hits 1293system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 3273779 # number of ReadSharedReq hits 1294system.cpu0.l2cache.ReadSharedReq_hits::total 3273779 # number of ReadSharedReq hits 1295system.cpu0.l2cache.InvalidateReq_hits::cpu0.data 166627 # number of InvalidateReq hits 1296system.cpu0.l2cache.InvalidateReq_hits::total 166627 # number of InvalidateReq hits 1297system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 639992 # number of demand (read+write) hits 1298system.cpu0.l2cache.demand_hits::cpu0.itb.walker 185315 # number of demand (read+write) hits 1299system.cpu0.l2cache.demand_hits::cpu0.inst 5493946 # number of demand (read+write) hits 1300system.cpu0.l2cache.demand_hits::cpu0.data 4269535 # number of demand (read+write) hits 1301system.cpu0.l2cache.demand_hits::total 10588788 # number of demand (read+write) hits 1302system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 639992 # number of overall hits 1303system.cpu0.l2cache.overall_hits::cpu0.itb.walker 185315 # number of overall hits 1304system.cpu0.l2cache.overall_hits::cpu0.inst 5493946 # number of overall hits 1305system.cpu0.l2cache.overall_hits::cpu0.data 4269535 # number of overall hits 1306system.cpu0.l2cache.overall_hits::total 10588788 # number of overall hits 1307system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 23429 # number of ReadReq misses 1308system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 11592 # number of ReadReq misses 1309system.cpu0.l2cache.ReadReq_misses::total 35021 # number of ReadReq misses 1310system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 269158 # number of UpgradeReq misses 1311system.cpu0.l2cache.UpgradeReq_misses::total 269158 # number of UpgradeReq misses 1312system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 197304 # number of SCUpgradeReq misses 1313system.cpu0.l2cache.SCUpgradeReq_misses::total 197304 # number of SCUpgradeReq misses 1314system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 5 # number of SCUpgradeFailReq misses 1315system.cpu0.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses 1316system.cpu0.l2cache.ReadExReq_misses::cpu0.data 301043 # number of ReadExReq misses 1317system.cpu0.l2cache.ReadExReq_misses::total 301043 # number of ReadExReq misses 1318system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 593373 # number of ReadCleanReq misses 1319system.cpu0.l2cache.ReadCleanReq_misses::total 593373 # number of ReadCleanReq misses 1320system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 1093007 # number of ReadSharedReq misses 1321system.cpu0.l2cache.ReadSharedReq_misses::total 1093007 # number of ReadSharedReq misses 1322system.cpu0.l2cache.InvalidateReq_misses::cpu0.data 623543 # number of InvalidateReq misses 1323system.cpu0.l2cache.InvalidateReq_misses::total 623543 # number of InvalidateReq misses 1324system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 23429 # number of demand (read+write) misses 1325system.cpu0.l2cache.demand_misses::cpu0.itb.walker 11592 # number of demand (read+write) misses 1326system.cpu0.l2cache.demand_misses::cpu0.inst 593373 # number of demand (read+write) misses 1327system.cpu0.l2cache.demand_misses::cpu0.data 1394050 # number of demand (read+write) misses 1328system.cpu0.l2cache.demand_misses::total 2022444 # number of demand (read+write) misses 1329system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 23429 # number of overall misses 1330system.cpu0.l2cache.overall_misses::cpu0.itb.walker 11592 # number of overall misses 1331system.cpu0.l2cache.overall_misses::cpu0.inst 593373 # number of overall misses 1332system.cpu0.l2cache.overall_misses::cpu0.data 1394050 # number of overall misses 1333system.cpu0.l2cache.overall_misses::total 2022444 # number of overall misses 1334system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 862921500 # number of ReadReq miss cycles 1335system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 562577500 # number of ReadReq miss cycles 1336system.cpu0.l2cache.ReadReq_miss_latency::total 1425499000 # number of ReadReq miss cycles 1337system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 983366500 # number of UpgradeReq miss cycles 1338system.cpu0.l2cache.UpgradeReq_miss_latency::total 983366500 # number of UpgradeReq miss cycles 1339system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 308777000 # number of SCUpgradeReq miss cycles 1340system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 308777000 # number of SCUpgradeReq miss cycles 1341system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 2366500 # number of SCUpgradeFailReq miss cycles 1342system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 2366500 # number of SCUpgradeFailReq miss cycles 1343system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 18857416997 # number of ReadExReq miss cycles 1344system.cpu0.l2cache.ReadExReq_miss_latency::total 18857416997 # number of ReadExReq miss cycles 1345system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 22027267000 # number of ReadCleanReq miss cycles 1346system.cpu0.l2cache.ReadCleanReq_miss_latency::total 22027267000 # number of ReadCleanReq miss cycles 1347system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 45190340989 # number of ReadSharedReq miss cycles 1348system.cpu0.l2cache.ReadSharedReq_miss_latency::total 45190340989 # number of ReadSharedReq miss cycles 1349system.cpu0.l2cache.InvalidateReq_miss_latency::cpu0.data 290057500 # number of InvalidateReq miss cycles 1350system.cpu0.l2cache.InvalidateReq_miss_latency::total 290057500 # number of InvalidateReq miss cycles 1351system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 862921500 # number of demand (read+write) miss cycles 1352system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 562577500 # number of demand (read+write) miss cycles 1353system.cpu0.l2cache.demand_miss_latency::cpu0.inst 22027267000 # number of demand (read+write) miss cycles 1354system.cpu0.l2cache.demand_miss_latency::cpu0.data 64047757986 # number of demand (read+write) miss cycles 1355system.cpu0.l2cache.demand_miss_latency::total 87500523986 # number of demand (read+write) miss cycles 1356system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 862921500 # number of overall miss cycles 1357system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 562577500 # number of overall miss cycles 1358system.cpu0.l2cache.overall_miss_latency::cpu0.inst 22027267000 # number of overall miss cycles 1359system.cpu0.l2cache.overall_miss_latency::cpu0.data 64047757986 # number of overall miss cycles 1360system.cpu0.l2cache.overall_miss_latency::total 87500523986 # number of overall miss cycles 1361system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 663421 # number of ReadReq accesses(hits+misses) 1362system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 196907 # number of ReadReq accesses(hits+misses) 1363system.cpu0.l2cache.ReadReq_accesses::total 860328 # number of ReadReq accesses(hits+misses) 1364system.cpu0.l2cache.WritebackDirty_accesses::writebacks 4159646 # number of WritebackDirty accesses(hits+misses) 1365system.cpu0.l2cache.WritebackDirty_accesses::total 4159646 # number of WritebackDirty accesses(hits+misses) 1366system.cpu0.l2cache.WritebackClean_accesses::writebacks 8284827 # number of WritebackClean accesses(hits+misses) 1367system.cpu0.l2cache.WritebackClean_accesses::total 8284827 # number of WritebackClean accesses(hits+misses) 1368system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 269181 # number of UpgradeReq accesses(hits+misses) 1369system.cpu0.l2cache.UpgradeReq_accesses::total 269181 # number of UpgradeReq accesses(hits+misses) 1370system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 197306 # number of SCUpgradeReq accesses(hits+misses) 1371system.cpu0.l2cache.SCUpgradeReq_accesses::total 197306 # number of SCUpgradeReq accesses(hits+misses) 1372system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 5 # number of SCUpgradeFailReq accesses(hits+misses) 1373system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 5 # number of SCUpgradeFailReq accesses(hits+misses) 1374system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 1296799 # number of ReadExReq accesses(hits+misses) 1375system.cpu0.l2cache.ReadExReq_accesses::total 1296799 # number of ReadExReq accesses(hits+misses) 1376system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 6087319 # number of ReadCleanReq accesses(hits+misses) 1377system.cpu0.l2cache.ReadCleanReq_accesses::total 6087319 # number of ReadCleanReq accesses(hits+misses) 1378system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 4366786 # number of ReadSharedReq accesses(hits+misses) 1379system.cpu0.l2cache.ReadSharedReq_accesses::total 4366786 # number of ReadSharedReq accesses(hits+misses) 1380system.cpu0.l2cache.InvalidateReq_accesses::cpu0.data 790170 # number of InvalidateReq accesses(hits+misses) 1381system.cpu0.l2cache.InvalidateReq_accesses::total 790170 # number of InvalidateReq accesses(hits+misses) 1382system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 663421 # number of demand (read+write) accesses 1383system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 196907 # number of demand (read+write) accesses 1384system.cpu0.l2cache.demand_accesses::cpu0.inst 6087319 # number of demand (read+write) accesses 1385system.cpu0.l2cache.demand_accesses::cpu0.data 5663585 # number of demand (read+write) accesses 1386system.cpu0.l2cache.demand_accesses::total 12611232 # number of demand (read+write) accesses 1387system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 663421 # number of overall (read+write) accesses 1388system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 196907 # number of overall (read+write) accesses 1389system.cpu0.l2cache.overall_accesses::cpu0.inst 6087319 # number of overall (read+write) accesses 1390system.cpu0.l2cache.overall_accesses::cpu0.data 5663585 # number of overall (read+write) accesses 1391system.cpu0.l2cache.overall_accesses::total 12611232 # number of overall (read+write) accesses 1392system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.035315 # miss rate for ReadReq accesses 1393system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.058870 # miss rate for ReadReq accesses 1394system.cpu0.l2cache.ReadReq_miss_rate::total 0.040707 # miss rate for ReadReq accesses 1395system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999915 # miss rate for UpgradeReq accesses 1396system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999915 # miss rate for UpgradeReq accesses 1397system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.999990 # miss rate for SCUpgradeReq accesses 1398system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.999990 # miss rate for SCUpgradeReq accesses 1399system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses 1400system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 1401system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.232143 # miss rate for ReadExReq accesses 1402system.cpu0.l2cache.ReadExReq_miss_rate::total 0.232143 # miss rate for ReadExReq accesses 1403system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.097477 # miss rate for ReadCleanReq accesses 1404system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.097477 # miss rate for ReadCleanReq accesses 1405system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.250300 # miss rate for ReadSharedReq accesses 1406system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.250300 # miss rate for ReadSharedReq accesses 1407system.cpu0.l2cache.InvalidateReq_miss_rate::cpu0.data 0.789125 # miss rate for InvalidateReq accesses 1408system.cpu0.l2cache.InvalidateReq_miss_rate::total 0.789125 # miss rate for InvalidateReq accesses 1409system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.035315 # miss rate for demand accesses 1410system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.058870 # miss rate for demand accesses 1411system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.097477 # miss rate for demand accesses 1412system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.246143 # miss rate for demand accesses 1413system.cpu0.l2cache.demand_miss_rate::total 0.160368 # miss rate for demand accesses 1414system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.035315 # miss rate for overall accesses 1415system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.058870 # miss rate for overall accesses 1416system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.097477 # miss rate for overall accesses 1417system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.246143 # miss rate for overall accesses 1418system.cpu0.l2cache.overall_miss_rate::total 0.160368 # miss rate for overall accesses 1419system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 36831.341500 # average ReadReq miss latency 1420system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 48531.530366 # average ReadReq miss latency 1421system.cpu0.l2cache.ReadReq_avg_miss_latency::total 40704.120385 # average ReadReq miss latency 1422system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 3653.491629 # average UpgradeReq miss latency 1423system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 3653.491629 # average UpgradeReq miss latency 1424system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 1564.980943 # average SCUpgradeReq miss latency 1425system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 1564.980943 # average SCUpgradeReq miss latency 1426system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 473300 # average SCUpgradeFailReq miss latency 1427system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 473300 # average SCUpgradeFailReq miss latency 1428system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 62640.277293 # average ReadExReq miss latency 1429system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 62640.277293 # average ReadExReq miss latency 1430system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 37122.125543 # average ReadCleanReq miss latency 1431system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 37122.125543 # average ReadCleanReq miss latency 1432system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 41344.969418 # average ReadSharedReq miss latency 1433system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 41344.969418 # average ReadSharedReq miss latency 1434system.cpu0.l2cache.InvalidateReq_avg_miss_latency::cpu0.data 465.176419 # average InvalidateReq miss latency 1435system.cpu0.l2cache.InvalidateReq_avg_miss_latency::total 465.176419 # average InvalidateReq miss latency 1436system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 36831.341500 # average overall miss latency 1437system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 48531.530366 # average overall miss latency 1438system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 37122.125543 # average overall miss latency 1439system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 45943.659113 # average overall miss latency 1440system.cpu0.l2cache.demand_avg_miss_latency::total 43264.745024 # average overall miss latency 1441system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 36831.341500 # average overall miss latency 1442system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 48531.530366 # average overall miss latency 1443system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 37122.125543 # average overall miss latency 1444system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 45943.659113 # average overall miss latency 1445system.cpu0.l2cache.overall_avg_miss_latency::total 43264.745024 # average overall miss latency 1446system.cpu0.l2cache.blocked_cycles::no_mshrs 1347 # number of cycles access was blocked 1447system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1448system.cpu0.l2cache.blocked::no_mshrs 28 # number of cycles access was blocked 1449system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1450system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 48.107143 # average number of cycles each access was blocked 1451system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1452system.cpu0.l2cache.unused_prefetches 49330 # number of HardPF blocks evicted w/o reference 1453system.cpu0.l2cache.writebacks::writebacks 1802209 # number of writebacks 1454system.cpu0.l2cache.writebacks::total 1802209 # number of writebacks 1455system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 136 # number of ReadReq MSHR hits 1456system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 303 # number of ReadReq MSHR hits 1457system.cpu0.l2cache.ReadReq_mshr_hits::total 439 # number of ReadReq MSHR hits 1458system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 20845 # number of ReadExReq MSHR hits 1459system.cpu0.l2cache.ReadExReq_mshr_hits::total 20845 # number of ReadExReq MSHR hits 1460system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 2 # number of ReadCleanReq MSHR hits 1461system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 2 # number of ReadCleanReq MSHR hits 1462system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 4784 # number of ReadSharedReq MSHR hits 1463system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 4784 # number of ReadSharedReq MSHR hits 1464system.cpu0.l2cache.InvalidateReq_mshr_hits::cpu0.data 6 # number of InvalidateReq MSHR hits 1465system.cpu0.l2cache.InvalidateReq_mshr_hits::total 6 # number of InvalidateReq MSHR hits 1466system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 136 # number of demand (read+write) MSHR hits 1467system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 303 # number of demand (read+write) MSHR hits 1468system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits 1469system.cpu0.l2cache.demand_mshr_hits::cpu0.data 25629 # number of demand (read+write) MSHR hits 1470system.cpu0.l2cache.demand_mshr_hits::total 26070 # number of demand (read+write) MSHR hits 1471system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 136 # number of overall MSHR hits 1472system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 303 # number of overall MSHR hits 1473system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits 1474system.cpu0.l2cache.overall_mshr_hits::cpu0.data 25629 # number of overall MSHR hits 1475system.cpu0.l2cache.overall_mshr_hits::total 26070 # number of overall MSHR hits 1476system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 23293 # number of ReadReq MSHR misses 1477system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 11289 # number of ReadReq MSHR misses 1478system.cpu0.l2cache.ReadReq_mshr_misses::total 34582 # number of ReadReq MSHR misses 1479system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 895757 # number of HardPFReq MSHR misses 1480system.cpu0.l2cache.HardPFReq_mshr_misses::total 895757 # number of HardPFReq MSHR misses 1481system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 269158 # number of UpgradeReq MSHR misses 1482system.cpu0.l2cache.UpgradeReq_mshr_misses::total 269158 # number of UpgradeReq MSHR misses 1483system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 197304 # number of SCUpgradeReq MSHR misses 1484system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 197304 # number of SCUpgradeReq MSHR misses 1485system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 5 # number of SCUpgradeFailReq MSHR misses 1486system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 5 # number of SCUpgradeFailReq MSHR misses 1487system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 280198 # number of ReadExReq MSHR misses 1488system.cpu0.l2cache.ReadExReq_mshr_misses::total 280198 # number of ReadExReq MSHR misses 1489system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 593371 # number of ReadCleanReq MSHR misses 1490system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 593371 # number of ReadCleanReq MSHR misses 1491system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 1088223 # number of ReadSharedReq MSHR misses 1492system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 1088223 # number of ReadSharedReq MSHR misses 1493system.cpu0.l2cache.InvalidateReq_mshr_misses::cpu0.data 623537 # number of InvalidateReq MSHR misses 1494system.cpu0.l2cache.InvalidateReq_mshr_misses::total 623537 # number of InvalidateReq MSHR misses 1495system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 23293 # number of demand (read+write) MSHR misses 1496system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 11289 # number of demand (read+write) MSHR misses 1497system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 593371 # number of demand (read+write) MSHR misses 1498system.cpu0.l2cache.demand_mshr_misses::cpu0.data 1368421 # number of demand (read+write) MSHR misses 1499system.cpu0.l2cache.demand_mshr_misses::total 1996374 # number of demand (read+write) MSHR misses 1500system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 23293 # number of overall MSHR misses 1501system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 11289 # number of overall MSHR misses 1502system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 593371 # number of overall MSHR misses 1503system.cpu0.l2cache.overall_mshr_misses::cpu0.data 1368421 # number of overall MSHR misses 1504system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 895757 # number of overall MSHR misses 1505system.cpu0.l2cache.overall_mshr_misses::total 2892131 # number of overall MSHR misses 1506system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 1507system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 16980 # number of ReadReq MSHR uncacheable 1508system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 38273 # number of ReadReq MSHR uncacheable 1509system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 18801 # number of WriteReq MSHR uncacheable 1510system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 18801 # number of WriteReq MSHR uncacheable 1511system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 1512system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 35781 # number of overall MSHR uncacheable misses 1513system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 57074 # number of overall MSHR uncacheable misses 1514system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 720471000 # number of ReadReq MSHR miss cycles 1515system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 489799000 # number of ReadReq MSHR miss cycles 1516system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 1210270000 # number of ReadReq MSHR miss cycles 1517system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 58575065392 # number of HardPFReq MSHR miss cycles 1518system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 58575065392 # number of HardPFReq MSHR miss cycles 1519system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 4984780995 # number of UpgradeReq MSHR miss cycles 1520system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 4984780995 # number of UpgradeReq MSHR miss cycles 1521system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 3032798496 # number of SCUpgradeReq MSHR miss cycles 1522system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 3032798496 # number of SCUpgradeReq MSHR miss cycles 1523system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 2000500 # number of SCUpgradeFailReq MSHR miss cycles 1524system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2000500 # number of SCUpgradeFailReq MSHR miss cycles 1525system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 14111841497 # number of ReadExReq MSHR miss cycles 1526system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 14111841497 # number of ReadExReq MSHR miss cycles 1527system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 18467014500 # number of ReadCleanReq MSHR miss cycles 1528system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 18467014500 # number of ReadCleanReq MSHR miss cycles 1529system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 38294410989 # number of ReadSharedReq MSHR miss cycles 1530system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 38294410989 # number of ReadSharedReq MSHR miss cycles 1531system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::cpu0.data 22764184995 # number of InvalidateReq MSHR miss cycles 1532system.cpu0.l2cache.InvalidateReq_mshr_miss_latency::total 22764184995 # number of InvalidateReq MSHR miss cycles 1533system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 720471000 # number of demand (read+write) MSHR miss cycles 1534system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 489799000 # number of demand (read+write) MSHR miss cycles 1535system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 18467014500 # number of demand (read+write) MSHR miss cycles 1536system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 52406252486 # number of demand (read+write) MSHR miss cycles 1537system.cpu0.l2cache.demand_mshr_miss_latency::total 72083536986 # number of demand (read+write) MSHR miss cycles 1538system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 720471000 # number of overall MSHR miss cycles 1539system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 489799000 # number of overall MSHR miss cycles 1540system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 18467014500 # number of overall MSHR miss cycles 1541system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 52406252486 # number of overall MSHR miss cycles 1542system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 58575065392 # number of overall MSHR miss cycles 1543system.cpu0.l2cache.overall_mshr_miss_latency::total 130658602378 # number of overall MSHR miss cycles 1544system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of ReadReq MSHR uncacheable cycles 1545system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 2997239500 # number of ReadReq MSHR uncacheable cycles 1546system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 4864699500 # number of ReadReq MSHR uncacheable cycles 1547system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 1867460000 # number of overall MSHR uncacheable cycles 1548system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 2997239500 # number of overall MSHR uncacheable cycles 1549system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 4864699500 # number of overall MSHR uncacheable cycles 1550system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.035110 # mshr miss rate for ReadReq accesses 1551system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.057332 # mshr miss rate for ReadReq accesses 1552system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.040196 # mshr miss rate for ReadReq accesses 1553system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1554system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1555system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999915 # mshr miss rate for UpgradeReq accesses 1556system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999915 # mshr miss rate for UpgradeReq accesses 1557system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.999990 # mshr miss rate for SCUpgradeReq accesses 1558system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999990 # mshr miss rate for SCUpgradeReq accesses 1559system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses 1560system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 1561system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.216069 # mshr miss rate for ReadExReq accesses 1562system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.216069 # mshr miss rate for ReadExReq accesses 1563system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for ReadCleanReq accesses 1564system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097477 # mshr miss rate for ReadCleanReq accesses 1565system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.249205 # mshr miss rate for ReadSharedReq accesses 1566system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.249205 # mshr miss rate for ReadSharedReq accesses 1567system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::cpu0.data 0.789118 # mshr miss rate for InvalidateReq accesses 1568system.cpu0.l2cache.InvalidateReq_mshr_miss_rate::total 0.789118 # mshr miss rate for InvalidateReq accesses 1569system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.035110 # mshr miss rate for demand accesses 1570system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.057332 # mshr miss rate for demand accesses 1571system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for demand accesses 1572system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.241617 # mshr miss rate for demand accesses 1573system.cpu0.l2cache.demand_mshr_miss_rate::total 0.158301 # mshr miss rate for demand accesses 1574system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.035110 # mshr miss rate for overall accesses 1575system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.057332 # mshr miss rate for overall accesses 1576system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.097477 # mshr miss rate for overall accesses 1577system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.241617 # mshr miss rate for overall accesses 1578system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses 1579system.cpu0.l2cache.overall_mshr_miss_rate::total 0.229330 # mshr miss rate for overall accesses 1580system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average ReadReq mshr miss latency 1581system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average ReadReq mshr miss latency 1582system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34997.108322 # average ReadReq mshr miss latency 1583system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488 # average HardPFReq mshr miss latency 1584system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65391.691488 # average HardPFReq mshr miss latency 1585system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 18519.906505 # average UpgradeReq mshr miss latency 1586system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18519.906505 # average UpgradeReq mshr miss latency 1587system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15371.196205 # average SCUpgradeReq mshr miss latency 1588system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15371.196205 # average SCUpgradeReq mshr miss latency 1589system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400100 # average SCUpgradeFailReq mshr miss latency 1590system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400100 # average SCUpgradeFailReq mshr miss latency 1591system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50363.819503 # average ReadExReq mshr miss latency 1592system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50363.819503 # average ReadExReq mshr miss latency 1593system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average ReadCleanReq mshr miss latency 1594system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31122.206006 # average ReadCleanReq mshr miss latency 1595system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 35189.856297 # average ReadSharedReq mshr miss latency 1596system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 35189.856297 # average ReadSharedReq mshr miss latency 1597system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu0.data 36508.154280 # average InvalidateReq mshr miss latency 1598system.cpu0.l2cache.InvalidateReq_avg_mshr_miss_latency::total 36508.154280 # average InvalidateReq mshr miss latency 1599system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average overall mshr miss latency 1600system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average overall mshr miss latency 1601system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average overall mshr miss latency 1602system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38296.878290 # average overall mshr miss latency 1603system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36107.230903 # average overall mshr miss latency 1604system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30930.794659 # average overall mshr miss latency 1605system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 43387.279653 # average overall mshr miss latency 1606system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31122.206006 # average overall mshr miss latency 1607system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38296.878290 # average overall mshr miss latency 1608system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65391.691488 # average overall mshr miss latency 1609system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45177.276679 # average overall mshr miss latency 1610system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average ReadReq mshr uncacheable latency 1611system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 176515.871614 # average ReadReq mshr uncacheable latency 1612system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 127105.256970 # average ReadReq mshr uncacheable latency 1613system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 87703.000986 # average overall mshr uncacheable latency 1614system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 83766.230681 # average overall mshr uncacheable latency 1615system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 85234.949364 # average overall mshr uncacheable latency 1616system.cpu0.toL2Bus.snoop_filter.tot_requests 25828303 # Total number of requests made to the snoop filter. 1617system.cpu0.toL2Bus.snoop_filter.hit_single_requests 13287358 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1618system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 1712 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1619system.cpu0.toL2Bus.snoop_filter.tot_snoops 676521 # Total number of snoops made to the snoop filter. 1620system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 676518 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1621system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 3 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1622system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 1623system.cpu0.toL2Bus.trans_dist::ReadReq 990165 # Transaction distribution 1624system.cpu0.toL2Bus.trans_dist::ReadResp 11537181 # Transaction distribution 1625system.cpu0.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution 1626system.cpu0.toL2Bus.trans_dist::WriteReq 18801 # Transaction distribution 1627system.cpu0.toL2Bus.trans_dist::WriteResp 18801 # Transaction distribution 1628system.cpu0.toL2Bus.trans_dist::WritebackDirty 5966642 # Transaction distribution 1629system.cpu0.toL2Bus.trans_dist::WritebackClean 8286555 # Transaction distribution 1630system.cpu0.toL2Bus.trans_dist::CleanEvict 1378403 # Transaction distribution 1631system.cpu0.toL2Bus.trans_dist::HardPFReq 1136481 # Transaction distribution 1632system.cpu0.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution 1633system.cpu0.toL2Bus.trans_dist::UpgradeReq 480580 # Transaction distribution 1634system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 352407 # Transaction distribution 1635system.cpu0.toL2Bus.trans_dist::UpgradeResp 530357 # Transaction distribution 1636system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 77 # Transaction distribution 1637system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 1638system.cpu0.toL2Bus.trans_dist::ReadExReq 1327096 # Transaction distribution 1639system.cpu0.toL2Bus.trans_dist::ReadExResp 1303956 # Transaction distribution 1640system.cpu0.toL2Bus.trans_dist::ReadCleanReq 6087350 # Transaction distribution 1641system.cpu0.toL2Bus.trans_dist::ReadSharedReq 5339261 # Transaction distribution 1642system.cpu0.toL2Bus.trans_dist::InvalidateReq 842479 # Transaction distribution 1643system.cpu0.toL2Bus.trans_dist::InvalidateResp 790170 # Transaction distribution 1644system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 18304055 # Packet count per connected master and slave (bytes) 1645system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 20435509 # Packet count per connected master and slave (bytes) 1646system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 413815 # Packet count per connected master and slave (bytes) 1647system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1398403 # Packet count per connected master and slave (bytes) 1648system.cpu0.toL2Bus.pkt_count::total 40551782 # Packet count per connected master and slave (bytes) 1649system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 779484304 # Cumulative packet size per connected master and slave (bytes) 1650system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 775974521 # Cumulative packet size per connected master and slave (bytes) 1651system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1575256 # Cumulative packet size per connected master and slave (bytes) 1652system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 5307368 # Cumulative packet size per connected master and slave (bytes) 1653system.cpu0.toL2Bus.pkt_size::total 1562341449 # Cumulative packet size per connected master and slave (bytes) 1654system.cpu0.toL2Bus.snoops 5999180 # Total snoops (count) 1655system.cpu0.toL2Bus.snoopTraffic 122789024 # Total snoop traffic (bytes) 1656system.cpu0.toL2Bus.snoop_fanout::samples 19760108 # Request fanout histogram 1657system.cpu0.toL2Bus.snoop_fanout::mean 0.053277 # Request fanout histogram 1658system.cpu0.toL2Bus.snoop_fanout::stdev 0.224586 # Request fanout histogram 1659system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1660system.cpu0.toL2Bus.snoop_fanout::0 18707349 94.67% 94.67% # Request fanout histogram 1661system.cpu0.toL2Bus.snoop_fanout::1 1052756 5.33% 100.00% # Request fanout histogram 1662system.cpu0.toL2Bus.snoop_fanout::2 3 0.00% 100.00% # Request fanout histogram 1663system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1664system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1665system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1666system.cpu0.toL2Bus.snoop_fanout::total 19760108 # Request fanout histogram 1667system.cpu0.toL2Bus.reqLayer0.occupancy 25687014453 # Layer occupancy (ticks) 1668system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) 1669system.cpu0.toL2Bus.snoopLayer0.occupancy 182391125 # Layer occupancy (ticks) 1670system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1671system.cpu0.toL2Bus.respLayer0.occupancy 9158694684 # Layer occupancy (ticks) 1672system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1673system.cpu0.toL2Bus.respLayer1.occupancy 9158841551 # Layer occupancy (ticks) 1674system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 1675system.cpu0.toL2Bus.respLayer2.occupancy 217386526 # Layer occupancy (ticks) 1676system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 1677system.cpu0.toL2Bus.respLayer3.occupancy 735766915 # Layer occupancy (ticks) 1678system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 1679system.cpu1.branchPred.lookups 134369829 # Number of BP lookups 1680system.cpu1.branchPred.condPredicted 89463085 # Number of conditional branches predicted 1681system.cpu1.branchPred.condIncorrect 6609561 # Number of conditional branches incorrect 1682system.cpu1.branchPred.BTBLookups 94230263 # Number of BTB lookups 1683system.cpu1.branchPred.BTBHits 58109960 # Number of BTB hits 1684system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 1685system.cpu1.branchPred.BTBHitPct 61.668044 # BTB Hit Percentage 1686system.cpu1.branchPred.usedRAS 17839939 # Number of times the RAS was used to get a target. 1687system.cpu1.branchPred.RASInCorrect 183627 # Number of incorrect RAS predictions. 1688system.cpu1.branchPred.indirectLookups 4347444 # Number of indirect predictor lookups. 1689system.cpu1.branchPred.indirectHits 2695405 # Number of indirect target hits. 1690system.cpu1.branchPred.indirectMisses 1652039 # Number of indirect misses. 1691system.cpu1.branchPredindirectMispredicted 417102 # Number of mispredicted indirect branches. 1692system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 1693system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1694system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1695system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1696system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1697system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1698system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1699system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1700system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1701system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1702system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1703system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1704system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1705system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1706system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1707system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1708system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1709system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1710system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1711system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1712system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1713system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1714system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1715system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1716system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1717system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1718system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1719system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 1720system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 1721system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1722system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 1723system.cpu1.dtb.walker.walks 561952 # Table walker walks requested 1724system.cpu1.dtb.walker.walksLong 561952 # Table walker walks initiated with long descriptors 1725system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 11814 # Level at which table walker walks with long descriptors terminate 1726system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 88087 # Level at which table walker walks with long descriptors terminate 1727system.cpu1.dtb.walker.walksSquashedBefore 261651 # Table walks squashed before starting 1728system.cpu1.dtb.walker.walkWaitTime::samples 300301 # Table walker wait (enqueue to first request) latency 1729system.cpu1.dtb.walker.walkWaitTime::mean 2363.057399 # Table walker wait (enqueue to first request) latency 1730system.cpu1.dtb.walker.walkWaitTime::stdev 13317.227915 # Table walker wait (enqueue to first request) latency 1731system.cpu1.dtb.walker.walkWaitTime::0-65535 298048 99.25% 99.25% # Table walker wait (enqueue to first request) latency 1732system.cpu1.dtb.walker.walkWaitTime::65536-131071 1567 0.52% 99.77% # Table walker wait (enqueue to first request) latency 1733system.cpu1.dtb.walker.walkWaitTime::131072-196607 436 0.15% 99.92% # Table walker wait (enqueue to first request) latency 1734system.cpu1.dtb.walker.walkWaitTime::196608-262143 167 0.06% 99.97% # Table walker wait (enqueue to first request) latency 1735system.cpu1.dtb.walker.walkWaitTime::262144-327679 36 0.01% 99.98% # Table walker wait (enqueue to first request) latency 1736system.cpu1.dtb.walker.walkWaitTime::327680-393215 40 0.01% 100.00% # Table walker wait (enqueue to first request) latency 1737system.cpu1.dtb.walker.walkWaitTime::393216-458751 4 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1738system.cpu1.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1739system.cpu1.dtb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1740system.cpu1.dtb.walker.walkWaitTime::total 300301 # Table walker wait (enqueue to first request) latency 1741system.cpu1.dtb.walker.walkCompletionTime::samples 287935 # Table walker service (enqueue to completion) latency 1742system.cpu1.dtb.walker.walkCompletionTime::mean 21029.369476 # Table walker service (enqueue to completion) latency 1743system.cpu1.dtb.walker.walkCompletionTime::gmean 18280.568505 # Table walker service (enqueue to completion) latency 1744system.cpu1.dtb.walker.walkCompletionTime::stdev 15111.837725 # Table walker service (enqueue to completion) latency 1745system.cpu1.dtb.walker.walkCompletionTime::0-65535 285795 99.26% 99.26% # Table walker service (enqueue to completion) latency 1746system.cpu1.dtb.walker.walkCompletionTime::65536-131071 1436 0.50% 99.76% # Table walker service (enqueue to completion) latency 1747system.cpu1.dtb.walker.walkCompletionTime::131072-196607 377 0.13% 99.89% # Table walker service (enqueue to completion) latency 1748system.cpu1.dtb.walker.walkCompletionTime::196608-262143 181 0.06% 99.95% # Table walker service (enqueue to completion) latency 1749system.cpu1.dtb.walker.walkCompletionTime::262144-327679 86 0.03% 99.98% # Table walker service (enqueue to completion) latency 1750system.cpu1.dtb.walker.walkCompletionTime::327680-393215 29 0.01% 99.99% # Table walker service (enqueue to completion) latency 1751system.cpu1.dtb.walker.walkCompletionTime::393216-458751 11 0.00% 99.99% # Table walker service (enqueue to completion) latency 1752system.cpu1.dtb.walker.walkCompletionTime::458752-524287 3 0.00% 99.99% # Table walker service (enqueue to completion) latency 1753system.cpu1.dtb.walker.walkCompletionTime::524288-589823 1 0.00% 99.99% # Table walker service (enqueue to completion) latency 1754system.cpu1.dtb.walker.walkCompletionTime::589824-655359 16 0.01% 100.00% # Table walker service (enqueue to completion) latency 1755system.cpu1.dtb.walker.walkCompletionTime::total 287935 # Table walker service (enqueue to completion) latency 1756system.cpu1.dtb.walker.walksPending::samples 466714959496 # Table walker pending requests distribution 1757system.cpu1.dtb.walker.walksPending::mean 0.597643 # Table walker pending requests distribution 1758system.cpu1.dtb.walker.walksPending::stdev 0.555516 # Table walker pending requests distribution 1759system.cpu1.dtb.walker.walksPending::0-1 465490623496 99.74% 99.74% # Table walker pending requests distribution 1760system.cpu1.dtb.walker.walksPending::2-3 621983000 0.13% 99.87% # Table walker pending requests distribution 1761system.cpu1.dtb.walker.walksPending::4-5 266845500 0.06% 99.93% # Table walker pending requests distribution 1762system.cpu1.dtb.walker.walksPending::6-7 131382500 0.03% 99.96% # Table walker pending requests distribution 1763system.cpu1.dtb.walker.walksPending::8-9 96036000 0.02% 99.98% # Table walker pending requests distribution 1764system.cpu1.dtb.walker.walksPending::10-11 60845000 0.01% 99.99% # Table walker pending requests distribution 1765system.cpu1.dtb.walker.walksPending::12-13 18797500 0.00% 99.99% # Table walker pending requests distribution 1766system.cpu1.dtb.walker.walksPending::14-15 27878000 0.01% 100.00% # Table walker pending requests distribution 1767system.cpu1.dtb.walker.walksPending::16-17 546500 0.00% 100.00% # Table walker pending requests distribution 1768system.cpu1.dtb.walker.walksPending::18-19 22000 0.00% 100.00% # Table walker pending requests distribution 1769system.cpu1.dtb.walker.walksPending::total 466714959496 # Table walker pending requests distribution 1770system.cpu1.dtb.walker.walkPageSizes::4K 88088 88.17% 88.17% # Table walker page sizes translated 1771system.cpu1.dtb.walker.walkPageSizes::2M 11814 11.83% 100.00% # Table walker page sizes translated 1772system.cpu1.dtb.walker.walkPageSizes::total 99902 # Table walker page sizes translated 1773system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 561952 # Table walker requests started/completed, data/inst 1774system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1775system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 561952 # Table walker requests started/completed, data/inst 1776system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 99902 # Table walker requests started/completed, data/inst 1777system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1778system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 99902 # Table walker requests started/completed, data/inst 1779system.cpu1.dtb.walker.walkRequestOrigin::total 661854 # Table walker requests started/completed, data/inst 1780system.cpu1.dtb.inst_hits 0 # ITB inst hits 1781system.cpu1.dtb.inst_misses 0 # ITB inst misses 1782system.cpu1.dtb.read_hits 97791245 # DTB read hits 1783system.cpu1.dtb.read_misses 385118 # DTB read misses 1784system.cpu1.dtb.write_hits 81245431 # DTB write hits 1785system.cpu1.dtb.write_misses 176834 # DTB write misses 1786system.cpu1.dtb.flush_tlb 16 # Number of times complete TLB was flushed 1787system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1788system.cpu1.dtb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID 1789system.cpu1.dtb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID 1790system.cpu1.dtb.flush_entries 36850 # Number of entries that have been flushed from TLB 1791system.cpu1.dtb.align_faults 268 # Number of TLB faults due to alignment restrictions 1792system.cpu1.dtb.prefetch_faults 6109 # Number of TLB faults due to prefetch 1793system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 1794system.cpu1.dtb.perms_faults 40755 # Number of TLB faults due to permissions restrictions 1795system.cpu1.dtb.read_accesses 98176363 # DTB read accesses 1796system.cpu1.dtb.write_accesses 81422265 # DTB write accesses 1797system.cpu1.dtb.inst_accesses 0 # ITB inst accesses 1798system.cpu1.dtb.hits 179036676 # DTB hits 1799system.cpu1.dtb.misses 561952 # DTB misses 1800system.cpu1.dtb.accesses 179598628 # DTB accesses 1801system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 1802system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 1803system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1804system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 1805system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 1806system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1807system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 1808system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 1809system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 1810system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 1811system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 1812system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 1813system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 1814system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 1815system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 1816system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 1817system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1818system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 1819system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 1820system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 1821system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 1822system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 1823system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 1824system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 1825system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 1826system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 1827system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 1828system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits 1829system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses 1830system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 1831system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 1832system.cpu1.itb.walker.walks 84407 # Table walker walks requested 1833system.cpu1.itb.walker.walksLong 84407 # Table walker walks initiated with long descriptors 1834system.cpu1.itb.walker.walksLongTerminationLevel::Level2 1027 # Level at which table walker walks with long descriptors terminate 1835system.cpu1.itb.walker.walksLongTerminationLevel::Level3 60740 # Level at which table walker walks with long descriptors terminate 1836system.cpu1.itb.walker.walksSquashedBefore 10156 # Table walks squashed before starting 1837system.cpu1.itb.walker.walkWaitTime::samples 74251 # Table walker wait (enqueue to first request) latency 1838system.cpu1.itb.walker.walkWaitTime::mean 1057.238286 # Table walker wait (enqueue to first request) latency 1839system.cpu1.itb.walker.walkWaitTime::stdev 8622.114888 # Table walker wait (enqueue to first request) latency 1840system.cpu1.itb.walker.walkWaitTime::0-65535 74015 99.68% 99.68% # Table walker wait (enqueue to first request) latency 1841system.cpu1.itb.walker.walkWaitTime::65536-131071 199 0.27% 99.95% # Table walker wait (enqueue to first request) latency 1842system.cpu1.itb.walker.walkWaitTime::131072-196607 18 0.02% 99.97% # Table walker wait (enqueue to first request) latency 1843system.cpu1.itb.walker.walkWaitTime::196608-262143 10 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1844system.cpu1.itb.walker.walkWaitTime::262144-327679 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency 1845system.cpu1.itb.walker.walkWaitTime::327680-393215 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1846system.cpu1.itb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1847system.cpu1.itb.walker.walkWaitTime::589824-655359 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency 1848system.cpu1.itb.walker.walkWaitTime::total 74251 # Table walker wait (enqueue to first request) latency 1849system.cpu1.itb.walker.walkCompletionTime::samples 71923 # Table walker service (enqueue to completion) latency 1850system.cpu1.itb.walker.walkCompletionTime::mean 24988.821378 # Table walker service (enqueue to completion) latency 1851system.cpu1.itb.walker.walkCompletionTime::gmean 22597.090075 # Table walker service (enqueue to completion) latency 1852system.cpu1.itb.walker.walkCompletionTime::stdev 18666.984039 # Table walker service (enqueue to completion) latency 1853system.cpu1.itb.walker.walkCompletionTime::0-65535 70820 98.47% 98.47% # Table walker service (enqueue to completion) latency 1854system.cpu1.itb.walker.walkCompletionTime::65536-131071 715 0.99% 99.46% # Table walker service (enqueue to completion) latency 1855system.cpu1.itb.walker.walkCompletionTime::131072-196607 265 0.37% 99.83% # Table walker service (enqueue to completion) latency 1856system.cpu1.itb.walker.walkCompletionTime::196608-262143 63 0.09% 99.92% # Table walker service (enqueue to completion) latency 1857system.cpu1.itb.walker.walkCompletionTime::262144-327679 24 0.03% 99.95% # Table walker service (enqueue to completion) latency 1858system.cpu1.itb.walker.walkCompletionTime::327680-393215 16 0.02% 99.97% # Table walker service (enqueue to completion) latency 1859system.cpu1.itb.walker.walkCompletionTime::393216-458751 3 0.00% 99.98% # Table walker service (enqueue to completion) latency 1860system.cpu1.itb.walker.walkCompletionTime::458752-524287 3 0.00% 99.98% # Table walker service (enqueue to completion) latency 1861system.cpu1.itb.walker.walkCompletionTime::524288-589823 2 0.00% 99.98% # Table walker service (enqueue to completion) latency 1862system.cpu1.itb.walker.walkCompletionTime::589824-655359 10 0.01% 100.00% # Table walker service (enqueue to completion) latency 1863system.cpu1.itb.walker.walkCompletionTime::655360-720895 2 0.00% 100.00% # Table walker service (enqueue to completion) latency 1864system.cpu1.itb.walker.walkCompletionTime::total 71923 # Table walker service (enqueue to completion) latency 1865system.cpu1.itb.walker.walksPending::samples 410850107648 # Table walker pending requests distribution 1866system.cpu1.itb.walker.walksPending::mean 0.878728 # Table walker pending requests distribution 1867system.cpu1.itb.walker.walksPending::stdev 0.326631 # Table walker pending requests distribution 1868system.cpu1.itb.walker.walksPending::0 49848543788 12.13% 12.13% # Table walker pending requests distribution 1869system.cpu1.itb.walker.walksPending::1 360979116860 87.86% 99.99% # Table walker pending requests distribution 1870system.cpu1.itb.walker.walksPending::2 21177000 0.01% 100.00% # Table walker pending requests distribution 1871system.cpu1.itb.walker.walksPending::3 1227500 0.00% 100.00% # Table walker pending requests distribution 1872system.cpu1.itb.walker.walksPending::4 42500 0.00% 100.00% # Table walker pending requests distribution 1873system.cpu1.itb.walker.walksPending::total 410850107648 # Table walker pending requests distribution 1874system.cpu1.itb.walker.walkPageSizes::4K 60740 98.34% 98.34% # Table walker page sizes translated 1875system.cpu1.itb.walker.walkPageSizes::2M 1027 1.66% 100.00% # Table walker page sizes translated 1876system.cpu1.itb.walker.walkPageSizes::total 61767 # Table walker page sizes translated 1877system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 1878system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 84407 # Table walker requests started/completed, data/inst 1879system.cpu1.itb.walker.walkRequestOrigin_Requested::total 84407 # Table walker requests started/completed, data/inst 1880system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 1881system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 61767 # Table walker requests started/completed, data/inst 1882system.cpu1.itb.walker.walkRequestOrigin_Completed::total 61767 # Table walker requests started/completed, data/inst 1883system.cpu1.itb.walker.walkRequestOrigin::total 146174 # Table walker requests started/completed, data/inst 1884system.cpu1.itb.inst_hits 210802915 # ITB inst hits 1885system.cpu1.itb.inst_misses 84407 # ITB inst misses 1886system.cpu1.itb.read_hits 0 # DTB read hits 1887system.cpu1.itb.read_misses 0 # DTB read misses 1888system.cpu1.itb.write_hits 0 # DTB write hits 1889system.cpu1.itb.write_misses 0 # DTB write misses 1890system.cpu1.itb.flush_tlb 16 # Number of times complete TLB was flushed 1891system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 1892system.cpu1.itb.flush_tlb_mva_asid 45792 # Number of times TLB was flushed by MVA & ASID 1893system.cpu1.itb.flush_tlb_asid 1079 # Number of times TLB was flushed by ASID 1894system.cpu1.itb.flush_entries 26222 # Number of entries that have been flushed from TLB 1895system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 1896system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 1897system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 1898system.cpu1.itb.perms_faults 208943 # Number of TLB faults due to permissions restrictions 1899system.cpu1.itb.read_accesses 0 # DTB read accesses 1900system.cpu1.itb.write_accesses 0 # DTB write accesses 1901system.cpu1.itb.inst_accesses 210887322 # ITB inst accesses 1902system.cpu1.itb.hits 210802915 # DTB hits 1903system.cpu1.itb.misses 84407 # DTB misses 1904system.cpu1.itb.accesses 210887322 # DTB accesses 1905system.cpu1.numPwrStateTransitions 27667 # Number of power state transitions 1906system.cpu1.pwrStateClkGateDist::samples 13834 # Distribution of time spent in the clock gated state 1907system.cpu1.pwrStateClkGateDist::mean 3399006591.183533 # Distribution of time spent in the clock gated state 1908system.cpu1.pwrStateClkGateDist::stdev 87524078188.715500 # Distribution of time spent in the clock gated state 1909system.cpu1.pwrStateClkGateDist::underflows 3453 24.96% 24.96% # Distribution of time spent in the clock gated state 1910system.cpu1.pwrStateClkGateDist::1000-5e+10 10352 74.83% 99.79% # Distribution of time spent in the clock gated state 1911system.cpu1.pwrStateClkGateDist::5e+10-1e+11 5 0.04% 99.83% # Distribution of time spent in the clock gated state 1912system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 2 0.01% 99.84% # Distribution of time spent in the clock gated state 1913system.cpu1.pwrStateClkGateDist::2e+11-2.5e+11 3 0.02% 99.86% # Distribution of time spent in the clock gated state 1914system.cpu1.pwrStateClkGateDist::4.5e+11-5e+11 2 0.01% 99.88% # Distribution of time spent in the clock gated state 1915system.cpu1.pwrStateClkGateDist::6.5e+11-7e+11 1 0.01% 99.88% # Distribution of time spent in the clock gated state 1916system.cpu1.pwrStateClkGateDist::7e+11-7.5e+11 1 0.01% 99.89% # Distribution of time spent in the clock gated state 1917system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.01% 99.90% # Distribution of time spent in the clock gated state 1918system.cpu1.pwrStateClkGateDist::overflows 14 0.10% 100.00% # Distribution of time spent in the clock gated state 1919system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state 1920system.cpu1.pwrStateClkGateDist::max_value 7390880477084 # Distribution of time spent in the clock gated state 1921system.cpu1.pwrStateClkGateDist::total 13834 # Distribution of time spent in the clock gated state 1922system.cpu1.pwrStateResidencyTicks::ON 363085536567 # Cumulative time (in ticks) in various power states 1923system.cpu1.pwrStateResidencyTicks::CLK_GATED 47021857182433 # Cumulative time (in ticks) in various power states 1924system.cpu1.numCycles 726181462 # number of cpu cycles simulated 1925system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started 1926system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 1927system.cpu1.fetch.icacheStallCycles 86390303 # Number of cycles fetch is stalled on an Icache miss 1928system.cpu1.fetch.Insts 594062843 # Number of instructions fetch has processed 1929system.cpu1.fetch.Branches 134369829 # Number of branches that fetch encountered 1930system.cpu1.fetch.predictedBranches 78645304 # Number of branches that fetch has predicted taken 1931system.cpu1.fetch.Cycles 601498232 # Number of cycles fetch has run and was not squashing or blocked 1932system.cpu1.fetch.SquashCycles 14253482 # Number of cycles fetch has spent squashing 1933system.cpu1.fetch.TlbCycles 1820697 # Number of cycles fetch has spent waiting for tlb 1934system.cpu1.fetch.MiscStallCycles 287238 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 1935system.cpu1.fetch.PendingTrapStallCycles 5988786 # Number of stall cycles due to pending traps 1936system.cpu1.fetch.PendingQuiesceStallCycles 713679 # Number of stall cycles due to pending quiesce instructions 1937system.cpu1.fetch.IcacheWaitRetryStallCycles 819715 # Number of stall cycles due to full MSHR 1938system.cpu1.fetch.CacheLines 210572695 # Number of cache lines fetched 1939system.cpu1.fetch.IcacheSquashes 1658938 # Number of outstanding Icache misses that were squashed 1940system.cpu1.fetch.ItlbSquashes 27666 # Number of outstanding ITLB misses that were squashed 1941system.cpu1.fetch.rateDist::samples 704645391 # Number of instructions fetched each cycle (Total) 1942system.cpu1.fetch.rateDist::mean 0.988963 # Number of instructions fetched each cycle (Total) 1943system.cpu1.fetch.rateDist::stdev 1.222689 # Number of instructions fetched each cycle (Total) 1944system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 1945system.cpu1.fetch.rateDist::0 370929364 52.64% 52.64% # Number of instructions fetched each cycle (Total) 1946system.cpu1.fetch.rateDist::1 130277469 18.49% 71.13% # Number of instructions fetched each cycle (Total) 1947system.cpu1.fetch.rateDist::2 43725033 6.21% 77.33% # Number of instructions fetched each cycle (Total) 1948system.cpu1.fetch.rateDist::3 159713525 22.67% 100.00% # Number of instructions fetched each cycle (Total) 1949system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 1950system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 1951system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 1952system.cpu1.fetch.rateDist::total 704645391 # Number of instructions fetched each cycle (Total) 1953system.cpu1.fetch.branchRate 0.185036 # Number of branch fetches per cycle 1954system.cpu1.fetch.rate 0.818064 # Number of inst fetches per cycle 1955system.cpu1.decode.IdleCycles 103020673 # Number of cycles decode is idle 1956system.cpu1.decode.BlockedCycles 337373962 # Number of cycles decode is blocked 1957system.cpu1.decode.RunCycles 222407115 # Number of cycles decode is running 1958system.cpu1.decode.UnblockCycles 36734416 # Number of cycles decode is unblocking 1959system.cpu1.decode.SquashCycles 5109225 # Number of cycles decode is squashing 1960system.cpu1.decode.BranchResolved 18739170 # Number of times decode resolved a branch 1961system.cpu1.decode.BranchMispred 2055775 # Number of times decode detected a branch misprediction 1962system.cpu1.decode.DecodedInsts 616426802 # Number of instructions handled by decode 1963system.cpu1.decode.SquashedInsts 23026844 # Number of squashed instructions handled by decode 1964system.cpu1.rename.SquashCycles 5109225 # Number of cycles rename is squashing 1965system.cpu1.rename.IdleCycles 137867421 # Number of cycles rename is idle 1966system.cpu1.rename.BlockCycles 45074504 # Number of cycles rename is blocking 1967system.cpu1.rename.serializeStallCycles 232811775 # count of cycles rename stalled for serializing inst 1968system.cpu1.rename.RunCycles 223900939 # Number of cycles rename is running 1969system.cpu1.rename.UnblockCycles 59881527 # Number of cycles rename is unblocking 1970system.cpu1.rename.RenamedInsts 599411621 # Number of instructions processed by rename 1971system.cpu1.rename.SquashedInsts 6042296 # Number of squashed instructions processed by rename 1972system.cpu1.rename.ROBFullEvents 9969882 # Number of times rename has blocked due to ROB full 1973system.cpu1.rename.IQFullEvents 242190 # Number of times rename has blocked due to IQ full 1974system.cpu1.rename.LQFullEvents 299313 # Number of times rename has blocked due to LQ full 1975system.cpu1.rename.SQFullEvents 25537080 # Number of times rename has blocked due to SQ full 1976system.cpu1.rename.FullRegisterEvents 11262 # Number of times there has been no free registers 1977system.cpu1.rename.RenamedOperands 571214843 # Number of destination operands rename has renamed 1978system.cpu1.rename.RenameLookups 926423560 # Number of register rename lookups that rename has made 1979system.cpu1.rename.int_rename_lookups 707359605 # Number of integer rename lookups 1980system.cpu1.rename.fp_rename_lookups 805393 # Number of floating rename lookups 1981system.cpu1.rename.CommittedMaps 514629531 # Number of HB maps that are committed 1982system.cpu1.rename.UndoneMaps 56585312 # Number of HB maps that are undone due to squashing 1983system.cpu1.rename.serializingInsts 15957043 # count of serializing insts renamed 1984system.cpu1.rename.tempSerializingInsts 14048251 # count of temporary serializing insts renamed 1985system.cpu1.rename.skidInsts 73992297 # count of insts added to the skid buffer 1986system.cpu1.memDep0.insertedLoads 98060208 # Number of loads inserted to the mem dependence unit. 1987system.cpu1.memDep0.insertedStores 84478655 # Number of stores inserted to the mem dependence unit. 1988system.cpu1.memDep0.conflictingLoads 8950565 # Number of conflicting loads. 1989system.cpu1.memDep0.conflictingStores 7675207 # Number of conflicting stores. 1990system.cpu1.iq.iqInstsAdded 576680308 # Number of instructions added to the IQ (excludes non-spec) 1991system.cpu1.iq.iqNonSpecInstsAdded 16104006 # Number of non-speculative instructions added to the IQ 1992system.cpu1.iq.iqInstsIssued 581772484 # Number of instructions issued 1993system.cpu1.iq.iqSquashedInstsIssued 2680133 # Number of squashed instructions issued 1994system.cpu1.iq.iqSquashedInstsExamined 53366771 # Number of squashed instructions iterated over during squash; mainly for profiling 1995system.cpu1.iq.iqSquashedOperandsExamined 34273904 # Number of squashed operands that are examined and possibly removed from graph 1996system.cpu1.iq.iqSquashedNonSpecRemoved 266458 # Number of squashed non-spec instructions that were removed 1997system.cpu1.iq.issued_per_cycle::samples 704645391 # Number of insts issued each cycle 1998system.cpu1.iq.issued_per_cycle::mean 0.825624 # Number of insts issued each cycle 1999system.cpu1.iq.issued_per_cycle::stdev 1.067009 # Number of insts issued each cycle 2000system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 2001system.cpu1.iq.issued_per_cycle::0 385934490 54.77% 54.77% # Number of insts issued each cycle 2002system.cpu1.iq.issued_per_cycle::1 135280434 19.20% 73.97% # Number of insts issued each cycle 2003system.cpu1.iq.issued_per_cycle::2 111501247 15.82% 89.79% # Number of insts issued each cycle 2004system.cpu1.iq.issued_per_cycle::3 64231431 9.12% 98.91% # Number of insts issued each cycle 2005system.cpu1.iq.issued_per_cycle::4 7693682 1.09% 100.00% # Number of insts issued each cycle 2006system.cpu1.iq.issued_per_cycle::5 4107 0.00% 100.00% # Number of insts issued each cycle 2007system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 2008system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 2009system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 2010system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 2011system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 2012system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 2013system.cpu1.iq.issued_per_cycle::total 704645391 # Number of insts issued each cycle 2014system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 2015system.cpu1.iq.fu_full::IntAlu 58591735 44.23% 44.23% # attempts to use FU when none available 2016system.cpu1.iq.fu_full::IntMult 49305 0.04% 44.27% # attempts to use FU when none available 2017system.cpu1.iq.fu_full::IntDiv 21310 0.02% 44.29% # attempts to use FU when none available 2018system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.29% # attempts to use FU when none available 2019system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.29% # attempts to use FU when none available 2020system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.29% # attempts to use FU when none available 2021system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.29% # attempts to use FU when none available 2022system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.29% # attempts to use FU when none available 2023system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.29% # attempts to use FU when none available 2024system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.29% # attempts to use FU when none available 2025system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.29% # attempts to use FU when none available 2026system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.29% # attempts to use FU when none available 2027system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.29% # attempts to use FU when none available 2028system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.29% # attempts to use FU when none available 2029system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.29% # attempts to use FU when none available 2030system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.29% # attempts to use FU when none available 2031system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.29% # attempts to use FU when none available 2032system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.29% # attempts to use FU when none available 2033system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.29% # attempts to use FU when none available 2034system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.29% # attempts to use FU when none available 2035system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.29% # attempts to use FU when none available 2036system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.29% # attempts to use FU when none available 2037system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.29% # attempts to use FU when none available 2038system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.29% # attempts to use FU when none available 2039system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.29% # attempts to use FU when none available 2040system.cpu1.iq.fu_full::SimdFloatMisc 60 0.00% 44.29% # attempts to use FU when none available 2041system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.29% # attempts to use FU when none available 2042system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.29% # attempts to use FU when none available 2043system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.29% # attempts to use FU when none available 2044system.cpu1.iq.fu_full::MemRead 35005485 26.43% 70.71% # attempts to use FU when none available 2045system.cpu1.iq.fu_full::MemWrite 38791699 29.29% 100.00% # attempts to use FU when none available 2046system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 2047system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 2048system.cpu1.iq.FU_type_0::No_OpClass 36 0.00% 0.00% # Type of FU issued 2049system.cpu1.iq.FU_type_0::IntAlu 397008075 68.24% 68.24% # Type of FU issued 2050system.cpu1.iq.FU_type_0::IntMult 1247296 0.21% 68.46% # Type of FU issued 2051system.cpu1.iq.FU_type_0::IntDiv 70487 0.01% 68.47% # Type of FU issued 2052system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.47% # Type of FU issued 2053system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.47% # Type of FU issued 2054system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.47% # Type of FU issued 2055system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.47% # Type of FU issued 2056system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.47% # Type of FU issued 2057system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.47% # Type of FU issued 2058system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.47% # Type of FU issued 2059system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.47% # Type of FU issued 2060system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.47% # Type of FU issued 2061system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.47% # Type of FU issued 2062system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.47% # Type of FU issued 2063system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.47% # Type of FU issued 2064system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.47% # Type of FU issued 2065system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.47% # Type of FU issued 2066system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.47% # Type of FU issued 2067system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.47% # Type of FU issued 2068system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.47% # Type of FU issued 2069system.cpu1.iq.FU_type_0::SimdFloatAdd 8 0.00% 68.47% # Type of FU issued 2070system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.47% # Type of FU issued 2071system.cpu1.iq.FU_type_0::SimdFloatCmp 15 0.00% 68.47% # Type of FU issued 2072system.cpu1.iq.FU_type_0::SimdFloatCvt 24 0.00% 68.47% # Type of FU issued 2073system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.47% # Type of FU issued 2074system.cpu1.iq.FU_type_0::SimdFloatMisc 78078 0.01% 68.48% # Type of FU issued 2075system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.48% # Type of FU issued 2076system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.48% # Type of FU issued 2077system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.48% # Type of FU issued 2078system.cpu1.iq.FU_type_0::MemRead 100884939 17.34% 85.82% # Type of FU issued 2079system.cpu1.iq.FU_type_0::MemWrite 82483526 14.18% 100.00% # Type of FU issued 2080system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 2081system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 2082system.cpu1.iq.FU_type_0::total 581772484 # Type of FU issued 2083system.cpu1.iq.rate 0.801139 # Inst issue rate 2084system.cpu1.iq.fu_busy_cnt 132459594 # FU busy when requested 2085system.cpu1.iq.fu_busy_rate 0.227683 # FU busy rate (busy events/executed inst) 2086system.cpu1.iq.int_inst_queue_reads 2001993843 # Number of integer instruction queue reads 2087system.cpu1.iq.int_inst_queue_writes 645760406 # Number of integer instruction queue writes 2088system.cpu1.iq.int_inst_queue_wakeup_accesses 564750025 # Number of integer instruction queue wakeup accesses 2089system.cpu1.iq.fp_inst_queue_reads 1336243 # Number of floating instruction queue reads 2090system.cpu1.iq.fp_inst_queue_writes 531893 # Number of floating instruction queue writes 2091system.cpu1.iq.fp_inst_queue_wakeup_accesses 495883 # Number of floating instruction queue wakeup accesses 2092system.cpu1.iq.int_alu_accesses 713403384 # Number of integer alu accesses 2093system.cpu1.iq.fp_alu_accesses 828658 # Number of floating point alu accesses 2094system.cpu1.iew.lsq.thread0.forwLoads 2572358 # Number of loads that had data forwarded from stores 2095system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 2096system.cpu1.iew.lsq.thread0.squashedLoads 12226985 # Number of loads squashed 2097system.cpu1.iew.lsq.thread0.ignoredResponses 16460 # Number of memory responses ignored because the instruction is squashed 2098system.cpu1.iew.lsq.thread0.memOrderViolation 142391 # Number of memory ordering violations 2099system.cpu1.iew.lsq.thread0.squashedStores 5497757 # Number of stores squashed 2100system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 2101system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 2102system.cpu1.iew.lsq.thread0.rescheduledLoads 2564544 # Number of loads that were rescheduled 2103system.cpu1.iew.lsq.thread0.cacheBlocked 4190277 # Number of times an access to memory failed due to the cache being blocked 2104system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle 2105system.cpu1.iew.iewSquashCycles 5109225 # Number of cycles IEW is squashing 2106system.cpu1.iew.iewBlockCycles 6111838 # Number of cycles IEW is blocking 2107system.cpu1.iew.iewUnblockCycles 1648605 # Number of cycles IEW is unblocking 2108system.cpu1.iew.iewDispatchedInsts 592918318 # Number of instructions dispatched to IQ 2109system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 2110system.cpu1.iew.iewDispLoadInsts 98060208 # Number of dispatched load instructions 2111system.cpu1.iew.iewDispStoreInsts 84478655 # Number of dispatched store instructions 2112system.cpu1.iew.iewDispNonSpecInsts 13792326 # Number of dispatched non-speculative instructions 2113system.cpu1.iew.iewIQFullEvents 62841 # Number of times the IQ has become full, causing a stall 2114system.cpu1.iew.iewLSQFullEvents 1527139 # Number of times the LSQ has become full, causing a stall 2115system.cpu1.iew.memOrderViolationEvents 142391 # Number of memory order violations 2116system.cpu1.iew.predictedTakenIncorrect 1885740 # Number of branches that were predicted taken incorrectly 2117system.cpu1.iew.predictedNotTakenIncorrect 3046567 # Number of branches that were predicted not taken incorrectly 2118system.cpu1.iew.branchMispredicts 4932307 # Number of branch mispredicts detected at execute 2119system.cpu1.iew.iewExecutedInsts 573876367 # Number of executed instructions 2120system.cpu1.iew.iewExecLoadInsts 97784309 # Number of load instructions executed 2121system.cpu1.iew.iewExecSquashedInsts 7346483 # Number of squashed instructions skipped in execute 2122system.cpu1.iew.exec_swp 0 # number of swp insts executed 2123system.cpu1.iew.exec_nop 134004 # number of nop insts executed 2124system.cpu1.iew.exec_refs 179029158 # number of memory reference insts executed 2125system.cpu1.iew.exec_branches 107707763 # Number of branches executed 2126system.cpu1.iew.exec_stores 81244849 # Number of stores executed 2127system.cpu1.iew.exec_rate 0.790266 # Inst execution rate 2128system.cpu1.iew.wb_sent 565995055 # cumulative count of insts sent to commit 2129system.cpu1.iew.wb_count 565245908 # cumulative count of insts written-back 2130system.cpu1.iew.wb_producers 273023556 # num instructions producing a value 2131system.cpu1.iew.wb_consumers 448078183 # num instructions consuming a value 2132system.cpu1.iew.wb_rate 0.778381 # insts written-back per cycle 2133system.cpu1.iew.wb_fanout 0.609321 # average fanout of values written-back 2134system.cpu1.commit.commitSquashedInsts 46535716 # The number of squashed insts skipped by commit 2135system.cpu1.commit.commitNonSpecStalls 15837548 # The number of times commit has been forced to stall to communicate backwards 2136system.cpu1.commit.branchMispredicts 4592045 # The number of times a branch was mispredicted 2137system.cpu1.commit.committed_per_cycle::samples 695790390 # Number of insts commited each cycle 2138system.cpu1.commit.committed_per_cycle::mean 0.775259 # Number of insts commited each cycle 2139system.cpu1.commit.committed_per_cycle::stdev 1.568649 # Number of insts commited each cycle 2140system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 2141system.cpu1.commit.committed_per_cycle::0 457970279 65.82% 65.82% # Number of insts commited each cycle 2142system.cpu1.commit.committed_per_cycle::1 124243355 17.86% 83.68% # Number of insts commited each cycle 2143system.cpu1.commit.committed_per_cycle::2 52434114 7.54% 91.21% # Number of insts commited each cycle 2144system.cpu1.commit.committed_per_cycle::3 17645088 2.54% 93.75% # Number of insts commited each cycle 2145system.cpu1.commit.committed_per_cycle::4 12549968 1.80% 95.55% # Number of insts commited each cycle 2146system.cpu1.commit.committed_per_cycle::5 8433891 1.21% 96.76% # Number of insts commited each cycle 2147system.cpu1.commit.committed_per_cycle::6 5802471 0.83% 97.60% # Number of insts commited each cycle 2148system.cpu1.commit.committed_per_cycle::7 3503250 0.50% 98.10% # Number of insts commited each cycle 2149system.cpu1.commit.committed_per_cycle::8 13207974 1.90% 100.00% # Number of insts commited each cycle 2150system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 2151system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 2152system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 2153system.cpu1.commit.committed_per_cycle::total 695790390 # Number of insts commited each cycle 2154system.cpu1.commit.committedInsts 458018039 # Number of instructions committed 2155system.cpu1.commit.committedOps 539417542 # Number of ops (including micro ops) committed 2156system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed 2157system.cpu1.commit.refs 164814121 # Number of memory references committed 2158system.cpu1.commit.loads 85833223 # Number of loads committed 2159system.cpu1.commit.membars 3719425 # Number of memory barriers committed 2160system.cpu1.commit.branches 102343051 # Number of branches committed 2161system.cpu1.commit.fp_insts 486729 # Number of committed floating point instructions. 2162system.cpu1.commit.int_insts 494686776 # Number of committed integer instructions. 2163system.cpu1.commit.function_calls 13237013 # Number of function calls committed. 2164system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 2165system.cpu1.commit.op_class_0::IntAlu 373462182 69.23% 69.23% # Class of committed instruction 2166system.cpu1.commit.op_class_0::IntMult 1014464 0.19% 69.42% # Class of committed instruction 2167system.cpu1.commit.op_class_0::IntDiv 55738 0.01% 69.43% # Class of committed instruction 2168system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 69.43% # Class of committed instruction 2169system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 69.43% # Class of committed instruction 2170system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 69.43% # Class of committed instruction 2171system.cpu1.commit.op_class_0::FloatMult 0 0.00% 69.43% # Class of committed instruction 2172system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 69.43% # Class of committed instruction 2173system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 69.43% # Class of committed instruction 2174system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 69.43% # Class of committed instruction 2175system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 69.43% # Class of committed instruction 2176system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 69.43% # Class of committed instruction 2177system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 69.43% # Class of committed instruction 2178system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 69.43% # Class of committed instruction 2179system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 69.43% # Class of committed instruction 2180system.cpu1.commit.op_class_0::SimdMult 0 0.00% 69.43% # Class of committed instruction 2181system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 69.43% # Class of committed instruction 2182system.cpu1.commit.op_class_0::SimdShift 0 0.00% 69.43% # Class of committed instruction 2183system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 69.43% # Class of committed instruction 2184system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 69.43% # Class of committed instruction 2185system.cpu1.commit.op_class_0::SimdFloatAdd 8 0.00% 69.43% # Class of committed instruction 2186system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 69.43% # Class of committed instruction 2187system.cpu1.commit.op_class_0::SimdFloatCmp 13 0.00% 69.43% # Class of committed instruction 2188system.cpu1.commit.op_class_0::SimdFloatCvt 21 0.00% 69.43% # Class of committed instruction 2189system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 69.43% # Class of committed instruction 2190system.cpu1.commit.op_class_0::SimdFloatMisc 70995 0.01% 69.45% # Class of committed instruction 2191system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 69.45% # Class of committed instruction 2192system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.45% # Class of committed instruction 2193system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.45% # Class of committed instruction 2194system.cpu1.commit.op_class_0::MemRead 85833223 15.91% 85.36% # Class of committed instruction 2195system.cpu1.commit.op_class_0::MemWrite 78980898 14.64% 100.00% # Class of committed instruction 2196system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 2197system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 2198system.cpu1.commit.op_class_0::total 539417542 # Class of committed instruction 2199system.cpu1.commit.bw_lim_events 13207974 # number cycles where commit BW limit reached 2200system.cpu1.rob.rob_reads 1264391907 # The number of ROB reads 2201system.cpu1.rob.rob_writes 1180722952 # The number of ROB writes 2202system.cpu1.timesIdled 944459 # Number of times that the entire CPU went into an idle state and unscheduled itself 2203system.cpu1.idleCycles 21536071 # Total number of cycles that the CPU has spent unscheduled due to idling 2204system.cpu1.quiesceCycles 94043695657 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt 2205system.cpu1.committedInsts 458018039 # Number of Instructions Simulated 2206system.cpu1.committedOps 539417542 # Number of Ops (including micro ops) Simulated 2207system.cpu1.cpi 1.585487 # CPI: Cycles Per Instruction 2208system.cpu1.cpi_total 1.585487 # CPI: Total CPI of All Threads 2209system.cpu1.ipc 0.630721 # IPC: Instructions Per Cycle 2210system.cpu1.ipc_total 0.630721 # IPC: Total IPC of All Threads 2211system.cpu1.int_regfile_reads 677403787 # number of integer regfile reads 2212system.cpu1.int_regfile_writes 401367044 # number of integer regfile writes 2213system.cpu1.fp_regfile_reads 791707 # number of floating regfile reads 2214system.cpu1.fp_regfile_writes 438600 # number of floating regfile writes 2215system.cpu1.cc_regfile_reads 124889457 # number of cc regfile reads 2216system.cpu1.cc_regfile_writes 125620500 # number of cc regfile writes 2217system.cpu1.misc_regfile_reads 1260290191 # number of misc regfile reads 2218system.cpu1.misc_regfile_writes 15974322 # number of misc regfile writes 2219system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 2220system.cpu1.dcache.tags.replacements 5362331 # number of replacements 2221system.cpu1.dcache.tags.tagsinuse 456.510727 # Cycle average of tags in use 2222system.cpu1.dcache.tags.total_refs 153804268 # Total number of references to valid blocks. 2223system.cpu1.dcache.tags.sampled_refs 5362842 # Sample count of references to valid blocks. 2224system.cpu1.dcache.tags.avg_refs 28.679620 # Average number of references to valid blocks. 2225system.cpu1.dcache.tags.warmup_cycle 8517840775000 # Cycle when the warmup percentage was hit. 2226system.cpu1.dcache.tags.occ_blocks::cpu1.data 456.510727 # Average occupied blocks per requestor 2227system.cpu1.dcache.tags.occ_percent::cpu1.data 0.891623 # Average percentage of cache occupancy 2228system.cpu1.dcache.tags.occ_percent::total 0.891623 # Average percentage of cache occupancy 2229system.cpu1.dcache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id 2230system.cpu1.dcache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id 2231system.cpu1.dcache.tags.age_task_id_blocks_1024::1 382 # Occupied blocks per task id 2232system.cpu1.dcache.tags.age_task_id_blocks_1024::2 34 # Occupied blocks per task id 2233system.cpu1.dcache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id 2234system.cpu1.dcache.tags.tag_accesses 341608540 # Number of tag accesses 2235system.cpu1.dcache.tags.data_accesses 341608540 # Number of data accesses 2236system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 2237system.cpu1.dcache.ReadReq_hits::cpu1.data 79940930 # number of ReadReq hits 2238system.cpu1.dcache.ReadReq_hits::total 79940930 # number of ReadReq hits 2239system.cpu1.dcache.WriteReq_hits::cpu1.data 69078558 # number of WriteReq hits 2240system.cpu1.dcache.WriteReq_hits::total 69078558 # number of WriteReq hits 2241system.cpu1.dcache.SoftPFReq_hits::cpu1.data 191831 # number of SoftPFReq hits 2242system.cpu1.dcache.SoftPFReq_hits::total 191831 # number of SoftPFReq hits 2243system.cpu1.dcache.WriteLineReq_hits::cpu1.data 170764 # number of WriteLineReq hits 2244system.cpu1.dcache.WriteLineReq_hits::total 170764 # number of WriteLineReq hits 2245system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1820637 # number of LoadLockedReq hits 2246system.cpu1.dcache.LoadLockedReq_hits::total 1820637 # number of LoadLockedReq hits 2247system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1828950 # number of StoreCondReq hits 2248system.cpu1.dcache.StoreCondReq_hits::total 1828950 # number of StoreCondReq hits 2249system.cpu1.dcache.demand_hits::cpu1.data 149190252 # number of demand (read+write) hits 2250system.cpu1.dcache.demand_hits::total 149190252 # number of demand (read+write) hits 2251system.cpu1.dcache.overall_hits::cpu1.data 149382083 # number of overall hits 2252system.cpu1.dcache.overall_hits::total 149382083 # number of overall hits 2253system.cpu1.dcache.ReadReq_misses::cpu1.data 6220385 # number of ReadReq misses 2254system.cpu1.dcache.ReadReq_misses::total 6220385 # number of ReadReq misses 2255system.cpu1.dcache.WriteReq_misses::cpu1.data 7237581 # number of WriteReq misses 2256system.cpu1.dcache.WriteReq_misses::total 7237581 # number of WriteReq misses 2257system.cpu1.dcache.SoftPFReq_misses::cpu1.data 689658 # number of SoftPFReq misses 2258system.cpu1.dcache.SoftPFReq_misses::total 689658 # number of SoftPFReq misses 2259system.cpu1.dcache.WriteLineReq_misses::cpu1.data 463987 # number of WriteLineReq misses 2260system.cpu1.dcache.WriteLineReq_misses::total 463987 # number of WriteLineReq misses 2261system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 244543 # number of LoadLockedReq misses 2262system.cpu1.dcache.LoadLockedReq_misses::total 244543 # number of LoadLockedReq misses 2263system.cpu1.dcache.StoreCondReq_misses::cpu1.data 192296 # number of StoreCondReq misses 2264system.cpu1.dcache.StoreCondReq_misses::total 192296 # number of StoreCondReq misses 2265system.cpu1.dcache.demand_misses::cpu1.data 13921953 # number of demand (read+write) misses 2266system.cpu1.dcache.demand_misses::total 13921953 # number of demand (read+write) misses 2267system.cpu1.dcache.overall_misses::cpu1.data 14611611 # number of overall misses 2268system.cpu1.dcache.overall_misses::total 14611611 # number of overall misses 2269system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 96362388500 # number of ReadReq miss cycles 2270system.cpu1.dcache.ReadReq_miss_latency::total 96362388500 # number of ReadReq miss cycles 2271system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 134833660621 # number of WriteReq miss cycles 2272system.cpu1.dcache.WriteReq_miss_latency::total 134833660621 # number of WriteReq miss cycles 2273system.cpu1.dcache.WriteLineReq_miss_latency::cpu1.data 11613680644 # number of WriteLineReq miss cycles 2274system.cpu1.dcache.WriteLineReq_miss_latency::total 11613680644 # number of WriteLineReq miss cycles 2275system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 3499456000 # number of LoadLockedReq miss cycles 2276system.cpu1.dcache.LoadLockedReq_miss_latency::total 3499456000 # number of LoadLockedReq miss cycles 2277system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4567503000 # number of StoreCondReq miss cycles 2278system.cpu1.dcache.StoreCondReq_miss_latency::total 4567503000 # number of StoreCondReq miss cycles 2279system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 3019500 # number of StoreCondFailReq miss cycles 2280system.cpu1.dcache.StoreCondFailReq_miss_latency::total 3019500 # number of StoreCondFailReq miss cycles 2281system.cpu1.dcache.demand_miss_latency::cpu1.data 242809729765 # number of demand (read+write) miss cycles 2282system.cpu1.dcache.demand_miss_latency::total 242809729765 # number of demand (read+write) miss cycles 2283system.cpu1.dcache.overall_miss_latency::cpu1.data 242809729765 # number of overall miss cycles 2284system.cpu1.dcache.overall_miss_latency::total 242809729765 # number of overall miss cycles 2285system.cpu1.dcache.ReadReq_accesses::cpu1.data 86161315 # number of ReadReq accesses(hits+misses) 2286system.cpu1.dcache.ReadReq_accesses::total 86161315 # number of ReadReq accesses(hits+misses) 2287system.cpu1.dcache.WriteReq_accesses::cpu1.data 76316139 # number of WriteReq accesses(hits+misses) 2288system.cpu1.dcache.WriteReq_accesses::total 76316139 # number of WriteReq accesses(hits+misses) 2289system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 881489 # number of SoftPFReq accesses(hits+misses) 2290system.cpu1.dcache.SoftPFReq_accesses::total 881489 # number of SoftPFReq accesses(hits+misses) 2291system.cpu1.dcache.WriteLineReq_accesses::cpu1.data 634751 # number of WriteLineReq accesses(hits+misses) 2292system.cpu1.dcache.WriteLineReq_accesses::total 634751 # number of WriteLineReq accesses(hits+misses) 2293system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 2065180 # number of LoadLockedReq accesses(hits+misses) 2294system.cpu1.dcache.LoadLockedReq_accesses::total 2065180 # number of LoadLockedReq accesses(hits+misses) 2295system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 2021246 # number of StoreCondReq accesses(hits+misses) 2296system.cpu1.dcache.StoreCondReq_accesses::total 2021246 # number of StoreCondReq accesses(hits+misses) 2297system.cpu1.dcache.demand_accesses::cpu1.data 163112205 # number of demand (read+write) accesses 2298system.cpu1.dcache.demand_accesses::total 163112205 # number of demand (read+write) accesses 2299system.cpu1.dcache.overall_accesses::cpu1.data 163993694 # number of overall (read+write) accesses 2300system.cpu1.dcache.overall_accesses::total 163993694 # number of overall (read+write) accesses 2301system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.072195 # miss rate for ReadReq accesses 2302system.cpu1.dcache.ReadReq_miss_rate::total 0.072195 # miss rate for ReadReq accesses 2303system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.094837 # miss rate for WriteReq accesses 2304system.cpu1.dcache.WriteReq_miss_rate::total 0.094837 # miss rate for WriteReq accesses 2305system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.782378 # miss rate for SoftPFReq accesses 2306system.cpu1.dcache.SoftPFReq_miss_rate::total 0.782378 # miss rate for SoftPFReq accesses 2307system.cpu1.dcache.WriteLineReq_miss_rate::cpu1.data 0.730975 # miss rate for WriteLineReq accesses 2308system.cpu1.dcache.WriteLineReq_miss_rate::total 0.730975 # miss rate for WriteLineReq accesses 2309system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.118412 # miss rate for LoadLockedReq accesses 2310system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.118412 # miss rate for LoadLockedReq accesses 2311system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.095137 # miss rate for StoreCondReq accesses 2312system.cpu1.dcache.StoreCondReq_miss_rate::total 0.095137 # miss rate for StoreCondReq accesses 2313system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085352 # miss rate for demand accesses 2314system.cpu1.dcache.demand_miss_rate::total 0.085352 # miss rate for demand accesses 2315system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089099 # miss rate for overall accesses 2316system.cpu1.dcache.overall_miss_rate::total 0.089099 # miss rate for overall accesses 2317system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15491.386546 # average ReadReq miss latency 2318system.cpu1.dcache.ReadReq_avg_miss_latency::total 15491.386546 # average ReadReq miss latency 2319system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 18629.658255 # average WriteReq miss latency 2320system.cpu1.dcache.WriteReq_avg_miss_latency::total 18629.658255 # average WriteReq miss latency 2321system.cpu1.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25030.185423 # average WriteLineReq miss latency 2322system.cpu1.dcache.WriteLineReq_avg_miss_latency::total 25030.185423 # average WriteLineReq miss latency 2323system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14310.186757 # average LoadLockedReq miss latency 2324system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14310.186757 # average LoadLockedReq miss latency 2325system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23752.459750 # average StoreCondReq miss latency 2326system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23752.459750 # average StoreCondReq miss latency 2327system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency 2328system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency 2329system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17440.780741 # average overall miss latency 2330system.cpu1.dcache.demand_avg_miss_latency::total 17440.780741 # average overall miss latency 2331system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16617.587873 # average overall miss latency 2332system.cpu1.dcache.overall_avg_miss_latency::total 16617.587873 # average overall miss latency 2333system.cpu1.dcache.blocked_cycles::no_mshrs 3018250 # number of cycles access was blocked 2334system.cpu1.dcache.blocked_cycles::no_targets 21738633 # number of cycles access was blocked 2335system.cpu1.dcache.blocked::no_mshrs 378529 # number of cycles access was blocked 2336system.cpu1.dcache.blocked::no_targets 731712 # number of cycles access was blocked 2337system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.973629 # average number of cycles each access was blocked 2338system.cpu1.dcache.avg_blocked_cycles::no_targets 29.709275 # average number of cycles each access was blocked 2339system.cpu1.dcache.writebacks::writebacks 5362354 # number of writebacks 2340system.cpu1.dcache.writebacks::total 5362354 # number of writebacks 2341system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 3187456 # number of ReadReq MSHR hits 2342system.cpu1.dcache.ReadReq_mshr_hits::total 3187456 # number of ReadReq MSHR hits 2343system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 5861363 # number of WriteReq MSHR hits 2344system.cpu1.dcache.WriteReq_mshr_hits::total 5861363 # number of WriteReq MSHR hits 2345system.cpu1.dcache.WriteLineReq_mshr_hits::cpu1.data 3594 # number of WriteLineReq MSHR hits 2346system.cpu1.dcache.WriteLineReq_mshr_hits::total 3594 # number of WriteLineReq MSHR hits 2347system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 128092 # number of LoadLockedReq MSHR hits 2348system.cpu1.dcache.LoadLockedReq_mshr_hits::total 128092 # number of LoadLockedReq MSHR hits 2349system.cpu1.dcache.demand_mshr_hits::cpu1.data 9052413 # number of demand (read+write) MSHR hits 2350system.cpu1.dcache.demand_mshr_hits::total 9052413 # number of demand (read+write) MSHR hits 2351system.cpu1.dcache.overall_mshr_hits::cpu1.data 9052413 # number of overall MSHR hits 2352system.cpu1.dcache.overall_mshr_hits::total 9052413 # number of overall MSHR hits 2353system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3032929 # number of ReadReq MSHR misses 2354system.cpu1.dcache.ReadReq_mshr_misses::total 3032929 # number of ReadReq MSHR misses 2355system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1376218 # number of WriteReq MSHR misses 2356system.cpu1.dcache.WriteReq_mshr_misses::total 1376218 # number of WriteReq MSHR misses 2357system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 689576 # number of SoftPFReq MSHR misses 2358system.cpu1.dcache.SoftPFReq_mshr_misses::total 689576 # number of SoftPFReq MSHR misses 2359system.cpu1.dcache.WriteLineReq_mshr_misses::cpu1.data 460393 # number of WriteLineReq MSHR misses 2360system.cpu1.dcache.WriteLineReq_mshr_misses::total 460393 # number of WriteLineReq MSHR misses 2361system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 116451 # number of LoadLockedReq MSHR misses 2362system.cpu1.dcache.LoadLockedReq_mshr_misses::total 116451 # number of LoadLockedReq MSHR misses 2363system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 192288 # number of StoreCondReq MSHR misses 2364system.cpu1.dcache.StoreCondReq_mshr_misses::total 192288 # number of StoreCondReq MSHR misses 2365system.cpu1.dcache.demand_mshr_misses::cpu1.data 4869540 # number of demand (read+write) MSHR misses 2366system.cpu1.dcache.demand_mshr_misses::total 4869540 # number of demand (read+write) MSHR misses 2367system.cpu1.dcache.overall_mshr_misses::cpu1.data 5559116 # number of overall MSHR misses 2368system.cpu1.dcache.overall_mshr_misses::total 5559116 # number of overall MSHR misses 2369system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 21291 # number of ReadReq MSHR uncacheable 2370system.cpu1.dcache.ReadReq_mshr_uncacheable::total 21291 # number of ReadReq MSHR uncacheable 2371system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable 2372system.cpu1.dcache.WriteReq_mshr_uncacheable::total 19410 # number of WriteReq MSHR uncacheable 2373system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 40701 # number of overall MSHR uncacheable misses 2374system.cpu1.dcache.overall_mshr_uncacheable_misses::total 40701 # number of overall MSHR uncacheable misses 2375system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 42726170500 # number of ReadReq MSHR miss cycles 2376system.cpu1.dcache.ReadReq_mshr_miss_latency::total 42726170500 # number of ReadReq MSHR miss cycles 2377system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 26732145261 # number of WriteReq MSHR miss cycles 2378system.cpu1.dcache.WriteReq_mshr_miss_latency::total 26732145261 # number of WriteReq MSHR miss cycles 2379system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 16635879000 # number of SoftPFReq MSHR miss cycles 2380system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 16635879000 # number of SoftPFReq MSHR miss cycles 2381system.cpu1.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 11021618644 # number of WriteLineReq MSHR miss cycles 2382system.cpu1.dcache.WriteLineReq_mshr_miss_latency::total 11021618644 # number of WriteLineReq MSHR miss cycles 2383system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1587191500 # number of LoadLockedReq MSHR miss cycles 2384system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1587191500 # number of LoadLockedReq MSHR miss cycles 2385system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4375287000 # number of StoreCondReq MSHR miss cycles 2386system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4375287000 # number of StoreCondReq MSHR miss cycles 2387system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2947500 # number of StoreCondFailReq MSHR miss cycles 2388system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2947500 # number of StoreCondFailReq MSHR miss cycles 2389system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 80479934405 # number of demand (read+write) MSHR miss cycles 2390system.cpu1.dcache.demand_mshr_miss_latency::total 80479934405 # number of demand (read+write) MSHR miss cycles 2391system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 97115813405 # number of overall MSHR miss cycles 2392system.cpu1.dcache.overall_mshr_miss_latency::total 97115813405 # number of overall MSHR miss cycles 2393system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3797634000 # number of ReadReq MSHR uncacheable cycles 2394system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3797634000 # number of ReadReq MSHR uncacheable cycles 2395system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 3797634000 # number of overall MSHR uncacheable cycles 2396system.cpu1.dcache.overall_mshr_uncacheable_latency::total 3797634000 # number of overall MSHR uncacheable cycles 2397system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035201 # mshr miss rate for ReadReq accesses 2398system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035201 # mshr miss rate for ReadReq accesses 2399system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018033 # mshr miss rate for WriteReq accesses 2400system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018033 # mshr miss rate for WriteReq accesses 2401system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.782285 # mshr miss rate for SoftPFReq accesses 2402system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.782285 # mshr miss rate for SoftPFReq accesses 2403system.cpu1.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.725313 # mshr miss rate for WriteLineReq accesses 2404system.cpu1.dcache.WriteLineReq_mshr_miss_rate::total 0.725313 # mshr miss rate for WriteLineReq accesses 2405system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.056388 # mshr miss rate for LoadLockedReq accesses 2406system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.056388 # mshr miss rate for LoadLockedReq accesses 2407system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.095133 # mshr miss rate for StoreCondReq accesses 2408system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.095133 # mshr miss rate for StoreCondReq accesses 2409system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029854 # mshr miss rate for demand accesses 2410system.cpu1.dcache.demand_mshr_miss_rate::total 0.029854 # mshr miss rate for demand accesses 2411system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033898 # mshr miss rate for overall accesses 2412system.cpu1.dcache.overall_mshr_miss_rate::total 0.033898 # mshr miss rate for overall accesses 2413system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14087.428522 # average ReadReq mshr miss latency 2414system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14087.428522 # average ReadReq mshr miss latency 2415system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19424.353744 # average WriteReq mshr miss latency 2416system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19424.353744 # average WriteReq mshr miss latency 2417system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 24124.794076 # average SoftPFReq mshr miss latency 2418system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 24124.794076 # average SoftPFReq mshr miss latency 2419system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 23939.587796 # average WriteLineReq mshr miss latency 2420system.cpu1.dcache.WriteLineReq_avg_mshr_miss_latency::total 23939.587796 # average WriteLineReq mshr miss latency 2421system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 13629.694034 # average LoadLockedReq mshr miss latency 2422system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13629.694034 # average LoadLockedReq mshr miss latency 2423system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22753.822391 # average StoreCondReq mshr miss latency 2424system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22753.822391 # average StoreCondReq mshr miss latency 2425system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency 2426system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency 2427system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16527.214974 # average overall mshr miss latency 2428system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16527.214974 # average overall mshr miss latency 2429system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17469.650463 # average overall mshr miss latency 2430system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17469.650463 # average overall mshr miss latency 2431system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 178368.042835 # average ReadReq mshr uncacheable latency 2432system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 178368.042835 # average ReadReq mshr uncacheable latency 2433system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 93305.668165 # average overall mshr uncacheable latency 2434system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 93305.668165 # average overall mshr uncacheable latency 2435system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 2436system.cpu1.icache.tags.replacements 5902862 # number of replacements 2437system.cpu1.icache.tags.tagsinuse 501.529159 # Cycle average of tags in use 2438system.cpu1.icache.tags.total_refs 204324856 # Total number of references to valid blocks. 2439system.cpu1.icache.tags.sampled_refs 5903374 # Sample count of references to valid blocks. 2440system.cpu1.icache.tags.avg_refs 34.611538 # Average number of references to valid blocks. 2441system.cpu1.icache.tags.warmup_cycle 8518180301500 # Cycle when the warmup percentage was hit. 2442system.cpu1.icache.tags.occ_blocks::cpu1.inst 501.529159 # Average occupied blocks per requestor 2443system.cpu1.icache.tags.occ_percent::cpu1.inst 0.979549 # Average percentage of cache occupancy 2444system.cpu1.icache.tags.occ_percent::total 0.979549 # Average percentage of cache occupancy 2445system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 2446system.cpu1.icache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id 2447system.cpu1.icache.tags.age_task_id_blocks_1024::1 243 # Occupied blocks per task id 2448system.cpu1.icache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id 2449system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 2450system.cpu1.icache.tags.tag_accesses 427035149 # Number of tag accesses 2451system.cpu1.icache.tags.data_accesses 427035149 # Number of data accesses 2452system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 2453system.cpu1.icache.ReadReq_hits::cpu1.inst 204324856 # number of ReadReq hits 2454system.cpu1.icache.ReadReq_hits::total 204324856 # number of ReadReq hits 2455system.cpu1.icache.demand_hits::cpu1.inst 204324856 # number of demand (read+write) hits 2456system.cpu1.icache.demand_hits::total 204324856 # number of demand (read+write) hits 2457system.cpu1.icache.overall_hits::cpu1.inst 204324856 # number of overall hits 2458system.cpu1.icache.overall_hits::total 204324856 # number of overall hits 2459system.cpu1.icache.ReadReq_misses::cpu1.inst 6241016 # number of ReadReq misses 2460system.cpu1.icache.ReadReq_misses::total 6241016 # number of ReadReq misses 2461system.cpu1.icache.demand_misses::cpu1.inst 6241016 # number of demand (read+write) misses 2462system.cpu1.icache.demand_misses::total 6241016 # number of demand (read+write) misses 2463system.cpu1.icache.overall_misses::cpu1.inst 6241016 # number of overall misses 2464system.cpu1.icache.overall_misses::total 6241016 # number of overall misses 2465system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 68483006769 # number of ReadReq miss cycles 2466system.cpu1.icache.ReadReq_miss_latency::total 68483006769 # number of ReadReq miss cycles 2467system.cpu1.icache.demand_miss_latency::cpu1.inst 68483006769 # number of demand (read+write) miss cycles 2468system.cpu1.icache.demand_miss_latency::total 68483006769 # number of demand (read+write) miss cycles 2469system.cpu1.icache.overall_miss_latency::cpu1.inst 68483006769 # number of overall miss cycles 2470system.cpu1.icache.overall_miss_latency::total 68483006769 # number of overall miss cycles 2471system.cpu1.icache.ReadReq_accesses::cpu1.inst 210565872 # number of ReadReq accesses(hits+misses) 2472system.cpu1.icache.ReadReq_accesses::total 210565872 # number of ReadReq accesses(hits+misses) 2473system.cpu1.icache.demand_accesses::cpu1.inst 210565872 # number of demand (read+write) accesses 2474system.cpu1.icache.demand_accesses::total 210565872 # number of demand (read+write) accesses 2475system.cpu1.icache.overall_accesses::cpu1.inst 210565872 # number of overall (read+write) accesses 2476system.cpu1.icache.overall_accesses::total 210565872 # number of overall (read+write) accesses 2477system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029639 # miss rate for ReadReq accesses 2478system.cpu1.icache.ReadReq_miss_rate::total 0.029639 # miss rate for ReadReq accesses 2479system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029639 # miss rate for demand accesses 2480system.cpu1.icache.demand_miss_rate::total 0.029639 # miss rate for demand accesses 2481system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029639 # miss rate for overall accesses 2482system.cpu1.icache.overall_miss_rate::total 0.029639 # miss rate for overall accesses 2483system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 10973.054190 # average ReadReq miss latency 2484system.cpu1.icache.ReadReq_avg_miss_latency::total 10973.054190 # average ReadReq miss latency 2485system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 10973.054190 # average overall miss latency 2486system.cpu1.icache.demand_avg_miss_latency::total 10973.054190 # average overall miss latency 2487system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 10973.054190 # average overall miss latency 2488system.cpu1.icache.overall_avg_miss_latency::total 10973.054190 # average overall miss latency 2489system.cpu1.icache.blocked_cycles::no_mshrs 10089385 # number of cycles access was blocked 2490system.cpu1.icache.blocked_cycles::no_targets 780 # number of cycles access was blocked 2491system.cpu1.icache.blocked::no_mshrs 729550 # number of cycles access was blocked 2492system.cpu1.icache.blocked::no_targets 2 # number of cycles access was blocked 2493system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.829600 # average number of cycles each access was blocked 2494system.cpu1.icache.avg_blocked_cycles::no_targets 390 # average number of cycles each access was blocked 2495system.cpu1.icache.writebacks::writebacks 5902862 # number of writebacks 2496system.cpu1.icache.writebacks::total 5902862 # number of writebacks 2497system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 337611 # number of ReadReq MSHR hits 2498system.cpu1.icache.ReadReq_mshr_hits::total 337611 # number of ReadReq MSHR hits 2499system.cpu1.icache.demand_mshr_hits::cpu1.inst 337611 # number of demand (read+write) MSHR hits 2500system.cpu1.icache.demand_mshr_hits::total 337611 # number of demand (read+write) MSHR hits 2501system.cpu1.icache.overall_mshr_hits::cpu1.inst 337611 # number of overall MSHR hits 2502system.cpu1.icache.overall_mshr_hits::total 337611 # number of overall MSHR hits 2503system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 5903405 # number of ReadReq MSHR misses 2504system.cpu1.icache.ReadReq_mshr_misses::total 5903405 # number of ReadReq MSHR misses 2505system.cpu1.icache.demand_mshr_misses::cpu1.inst 5903405 # number of demand (read+write) MSHR misses 2506system.cpu1.icache.demand_mshr_misses::total 5903405 # number of demand (read+write) MSHR misses 2507system.cpu1.icache.overall_mshr_misses::cpu1.inst 5903405 # number of overall MSHR misses 2508system.cpu1.icache.overall_mshr_misses::total 5903405 # number of overall MSHR misses 2509system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2510system.cpu1.icache.ReadReq_mshr_uncacheable::total 67 # number of ReadReq MSHR uncacheable 2511system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2512system.cpu1.icache.overall_mshr_uncacheable_misses::total 67 # number of overall MSHR uncacheable misses 2513system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 61792345334 # number of ReadReq MSHR miss cycles 2514system.cpu1.icache.ReadReq_mshr_miss_latency::total 61792345334 # number of ReadReq MSHR miss cycles 2515system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 61792345334 # number of demand (read+write) MSHR miss cycles 2516system.cpu1.icache.demand_mshr_miss_latency::total 61792345334 # number of demand (read+write) MSHR miss cycles 2517system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 61792345334 # number of overall MSHR miss cycles 2518system.cpu1.icache.overall_mshr_miss_latency::total 61792345334 # number of overall MSHR miss cycles 2519system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7079498 # number of ReadReq MSHR uncacheable cycles 2520system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7079498 # number of ReadReq MSHR uncacheable cycles 2521system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7079498 # number of overall MSHR uncacheable cycles 2522system.cpu1.icache.overall_mshr_uncacheable_latency::total 7079498 # number of overall MSHR uncacheable cycles 2523system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for ReadReq accesses 2524system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.028036 # mshr miss rate for ReadReq accesses 2525system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for demand accesses 2526system.cpu1.icache.demand_mshr_miss_rate::total 0.028036 # mshr miss rate for demand accesses 2527system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.028036 # mshr miss rate for overall accesses 2528system.cpu1.icache.overall_mshr_miss_rate::total 0.028036 # mshr miss rate for overall accesses 2529system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average ReadReq mshr miss latency 2530system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 10467.238032 # average ReadReq mshr miss latency 2531system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average overall mshr miss latency 2532system.cpu1.icache.demand_avg_mshr_miss_latency::total 10467.238032 # average overall mshr miss latency 2533system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 10467.238032 # average overall mshr miss latency 2534system.cpu1.icache.overall_avg_mshr_miss_latency::total 10467.238032 # average overall mshr miss latency 2535system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average ReadReq mshr uncacheable latency 2536system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 105664.149254 # average ReadReq mshr uncacheable latency 2537system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 105664.149254 # average overall mshr uncacheable latency 2538system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 105664.149254 # average overall mshr uncacheable latency 2539system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 2540system.cpu1.l2cache.prefetcher.num_hwpf_issued 7372835 # number of hwpf issued 2541system.cpu1.l2cache.prefetcher.pfIdentified 7380898 # number of prefetch candidates identified 2542system.cpu1.l2cache.prefetcher.pfBufferHit 7290 # number of redundant prefetches already in prefetch queue 2543system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 2544system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 2545system.cpu1.l2cache.prefetcher.pfSpanPage 895622 # number of prefetches not generated due to page crossing 2546system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 2547system.cpu1.l2cache.tags.replacements 2111480 # number of replacements 2548system.cpu1.l2cache.tags.tagsinuse 12950.875249 # Cycle average of tags in use 2549system.cpu1.l2cache.tags.total_refs 10279593 # Total number of references to valid blocks. 2550system.cpu1.l2cache.tags.sampled_refs 2126904 # Sample count of references to valid blocks. 2551system.cpu1.l2cache.tags.avg_refs 4.833125 # Average number of references to valid blocks. 2552system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 2553system.cpu1.l2cache.tags.occ_blocks::writebacks 12615.195694 # Average occupied blocks per requestor 2554system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 33.253837 # Average occupied blocks per requestor 2555system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 24.384299 # Average occupied blocks per requestor 2556system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 278.041418 # Average occupied blocks per requestor 2557system.cpu1.l2cache.tags.occ_percent::writebacks 0.769970 # Average percentage of cache occupancy 2558system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002030 # Average percentage of cache occupancy 2559system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.001488 # Average percentage of cache occupancy 2560system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.016970 # Average percentage of cache occupancy 2561system.cpu1.l2cache.tags.occ_percent::total 0.790459 # Average percentage of cache occupancy 2562system.cpu1.l2cache.tags.occ_task_id_blocks::1022 414 # Occupied blocks per task id 2563system.cpu1.l2cache.tags.occ_task_id_blocks::1023 111 # Occupied blocks per task id 2564system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14899 # Occupied blocks per task id 2565system.cpu1.l2cache.tags.age_task_id_blocks_1022::1 65 # Occupied blocks per task id 2566system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 128 # Occupied blocks per task id 2567system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 114 # Occupied blocks per task id 2568system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 107 # Occupied blocks per task id 2569system.cpu1.l2cache.tags.age_task_id_blocks_1023::1 7 # Occupied blocks per task id 2570system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 89 # Occupied blocks per task id 2571system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id 2572system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id 2573system.cpu1.l2cache.tags.age_task_id_blocks_1024::0 279 # Occupied blocks per task id 2574system.cpu1.l2cache.tags.age_task_id_blocks_1024::1 1377 # Occupied blocks per task id 2575system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 5586 # Occupied blocks per task id 2576system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5487 # Occupied blocks per task id 2577system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2170 # Occupied blocks per task id 2578system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.025269 # Percentage of cache occupancy per task id 2579system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.006775 # Percentage of cache occupancy per task id 2580system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.909363 # Percentage of cache occupancy per task id 2581system.cpu1.l2cache.tags.tag_accesses 393006433 # Number of tag accesses 2582system.cpu1.l2cache.tags.data_accesses 393006433 # Number of data accesses 2583system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 2584system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 563217 # number of ReadReq hits 2585system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 188120 # number of ReadReq hits 2586system.cpu1.l2cache.ReadReq_hits::total 751337 # number of ReadReq hits 2587system.cpu1.l2cache.WritebackDirty_hits::writebacks 3404083 # number of WritebackDirty hits 2588system.cpu1.l2cache.WritebackDirty_hits::total 3404083 # number of WritebackDirty hits 2589system.cpu1.l2cache.WritebackClean_hits::writebacks 7859423 # number of WritebackClean hits 2590system.cpu1.l2cache.WritebackClean_hits::total 7859423 # number of WritebackClean hits 2591system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits 2592system.cpu1.l2cache.UpgradeReq_hits::total 37 # number of UpgradeReq hits 2593system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits 2594system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits 2595system.cpu1.l2cache.ReadExReq_hits::cpu1.data 897837 # number of ReadExReq hits 2596system.cpu1.l2cache.ReadExReq_hits::total 897837 # number of ReadExReq hits 2597system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 5343474 # number of ReadCleanReq hits 2598system.cpu1.l2cache.ReadCleanReq_hits::total 5343474 # number of ReadCleanReq hits 2599system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 2865962 # number of ReadSharedReq hits 2600system.cpu1.l2cache.ReadSharedReq_hits::total 2865962 # number of ReadSharedReq hits 2601system.cpu1.l2cache.InvalidateReq_hits::cpu1.data 200218 # number of InvalidateReq hits 2602system.cpu1.l2cache.InvalidateReq_hits::total 200218 # number of InvalidateReq hits 2603system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 563217 # number of demand (read+write) hits 2604system.cpu1.l2cache.demand_hits::cpu1.itb.walker 188120 # number of demand (read+write) hits 2605system.cpu1.l2cache.demand_hits::cpu1.inst 5343474 # number of demand (read+write) hits 2606system.cpu1.l2cache.demand_hits::cpu1.data 3763799 # number of demand (read+write) hits 2607system.cpu1.l2cache.demand_hits::total 9858610 # number of demand (read+write) hits 2608system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 563217 # number of overall hits 2609system.cpu1.l2cache.overall_hits::cpu1.itb.walker 188120 # number of overall hits 2610system.cpu1.l2cache.overall_hits::cpu1.inst 5343474 # number of overall hits 2611system.cpu1.l2cache.overall_hits::cpu1.data 3763799 # number of overall hits 2612system.cpu1.l2cache.overall_hits::total 9858610 # number of overall hits 2613system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 20588 # number of ReadReq misses 2614system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 9811 # number of ReadReq misses 2615system.cpu1.l2cache.ReadReq_misses::total 30399 # number of ReadReq misses 2616system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 230170 # number of UpgradeReq misses 2617system.cpu1.l2cache.UpgradeReq_misses::total 230170 # number of UpgradeReq misses 2618system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 192283 # number of SCUpgradeReq misses 2619system.cpu1.l2cache.SCUpgradeReq_misses::total 192283 # number of SCUpgradeReq misses 2620system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 4 # number of SCUpgradeFailReq misses 2621system.cpu1.l2cache.SCUpgradeFailReq_misses::total 4 # number of SCUpgradeFailReq misses 2622system.cpu1.l2cache.ReadExReq_misses::cpu1.data 257129 # number of ReadExReq misses 2623system.cpu1.l2cache.ReadExReq_misses::total 257129 # number of ReadExReq misses 2624system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 559914 # number of ReadCleanReq misses 2625system.cpu1.l2cache.ReadCleanReq_misses::total 559914 # number of ReadCleanReq misses 2626system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 968987 # number of ReadSharedReq misses 2627system.cpu1.l2cache.ReadSharedReq_misses::total 968987 # number of ReadSharedReq misses 2628system.cpu1.l2cache.InvalidateReq_misses::cpu1.data 258105 # number of InvalidateReq misses 2629system.cpu1.l2cache.InvalidateReq_misses::total 258105 # number of InvalidateReq misses 2630system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 20588 # number of demand (read+write) misses 2631system.cpu1.l2cache.demand_misses::cpu1.itb.walker 9811 # number of demand (read+write) misses 2632system.cpu1.l2cache.demand_misses::cpu1.inst 559914 # number of demand (read+write) misses 2633system.cpu1.l2cache.demand_misses::cpu1.data 1226116 # number of demand (read+write) misses 2634system.cpu1.l2cache.demand_misses::total 1816429 # number of demand (read+write) misses 2635system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 20588 # number of overall misses 2636system.cpu1.l2cache.overall_misses::cpu1.itb.walker 9811 # number of overall misses 2637system.cpu1.l2cache.overall_misses::cpu1.inst 559914 # number of overall misses 2638system.cpu1.l2cache.overall_misses::cpu1.data 1226116 # number of overall misses 2639system.cpu1.l2cache.overall_misses::total 1816429 # number of overall misses 2640system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 677842000 # number of ReadReq miss cycles 2641system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 364880500 # number of ReadReq miss cycles 2642system.cpu1.l2cache.ReadReq_miss_latency::total 1042722500 # number of ReadReq miss cycles 2643system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 983294000 # number of UpgradeReq miss cycles 2644system.cpu1.l2cache.UpgradeReq_miss_latency::total 983294000 # number of UpgradeReq miss cycles 2645system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 271676000 # number of SCUpgradeReq miss cycles 2646system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 271676000 # number of SCUpgradeReq miss cycles 2647system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 2839500 # number of SCUpgradeFailReq miss cycles 2648system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 2839500 # number of SCUpgradeFailReq miss cycles 2649system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 12532259990 # number of ReadExReq miss cycles 2650system.cpu1.l2cache.ReadExReq_miss_latency::total 12532259990 # number of ReadExReq miss cycles 2651system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 20571950500 # number of ReadCleanReq miss cycles 2652system.cpu1.l2cache.ReadCleanReq_miss_latency::total 20571950500 # number of ReadCleanReq miss cycles 2653system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 36061918479 # number of ReadSharedReq miss cycles 2654system.cpu1.l2cache.ReadSharedReq_miss_latency::total 36061918479 # number of ReadSharedReq miss cycles 2655system.cpu1.l2cache.InvalidateReq_miss_latency::cpu1.data 340389000 # number of InvalidateReq miss cycles 2656system.cpu1.l2cache.InvalidateReq_miss_latency::total 340389000 # number of InvalidateReq miss cycles 2657system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 677842000 # number of demand (read+write) miss cycles 2658system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 364880500 # number of demand (read+write) miss cycles 2659system.cpu1.l2cache.demand_miss_latency::cpu1.inst 20571950500 # number of demand (read+write) miss cycles 2660system.cpu1.l2cache.demand_miss_latency::cpu1.data 48594178469 # number of demand (read+write) miss cycles 2661system.cpu1.l2cache.demand_miss_latency::total 70208851469 # number of demand (read+write) miss cycles 2662system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 677842000 # number of overall miss cycles 2663system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 364880500 # number of overall miss cycles 2664system.cpu1.l2cache.overall_miss_latency::cpu1.inst 20571950500 # number of overall miss cycles 2665system.cpu1.l2cache.overall_miss_latency::cpu1.data 48594178469 # number of overall miss cycles 2666system.cpu1.l2cache.overall_miss_latency::total 70208851469 # number of overall miss cycles 2667system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 583805 # number of ReadReq accesses(hits+misses) 2668system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 197931 # number of ReadReq accesses(hits+misses) 2669system.cpu1.l2cache.ReadReq_accesses::total 781736 # number of ReadReq accesses(hits+misses) 2670system.cpu1.l2cache.WritebackDirty_accesses::writebacks 3404083 # number of WritebackDirty accesses(hits+misses) 2671system.cpu1.l2cache.WritebackDirty_accesses::total 3404083 # number of WritebackDirty accesses(hits+misses) 2672system.cpu1.l2cache.WritebackClean_accesses::writebacks 7859423 # number of WritebackClean accesses(hits+misses) 2673system.cpu1.l2cache.WritebackClean_accesses::total 7859423 # number of WritebackClean accesses(hits+misses) 2674system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 230207 # number of UpgradeReq accesses(hits+misses) 2675system.cpu1.l2cache.UpgradeReq_accesses::total 230207 # number of UpgradeReq accesses(hits+misses) 2676system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 192284 # number of SCUpgradeReq accesses(hits+misses) 2677system.cpu1.l2cache.SCUpgradeReq_accesses::total 192284 # number of SCUpgradeReq accesses(hits+misses) 2678system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 4 # number of SCUpgradeFailReq accesses(hits+misses) 2679system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 4 # number of SCUpgradeFailReq accesses(hits+misses) 2680system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 1154966 # number of ReadExReq accesses(hits+misses) 2681system.cpu1.l2cache.ReadExReq_accesses::total 1154966 # number of ReadExReq accesses(hits+misses) 2682system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 5903388 # number of ReadCleanReq accesses(hits+misses) 2683system.cpu1.l2cache.ReadCleanReq_accesses::total 5903388 # number of ReadCleanReq accesses(hits+misses) 2684system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 3834949 # number of ReadSharedReq accesses(hits+misses) 2685system.cpu1.l2cache.ReadSharedReq_accesses::total 3834949 # number of ReadSharedReq accesses(hits+misses) 2686system.cpu1.l2cache.InvalidateReq_accesses::cpu1.data 458323 # number of InvalidateReq accesses(hits+misses) 2687system.cpu1.l2cache.InvalidateReq_accesses::total 458323 # number of InvalidateReq accesses(hits+misses) 2688system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 583805 # number of demand (read+write) accesses 2689system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 197931 # number of demand (read+write) accesses 2690system.cpu1.l2cache.demand_accesses::cpu1.inst 5903388 # number of demand (read+write) accesses 2691system.cpu1.l2cache.demand_accesses::cpu1.data 4989915 # number of demand (read+write) accesses 2692system.cpu1.l2cache.demand_accesses::total 11675039 # number of demand (read+write) accesses 2693system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 583805 # number of overall (read+write) accesses 2694system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 197931 # number of overall (read+write) accesses 2695system.cpu1.l2cache.overall_accesses::cpu1.inst 5903388 # number of overall (read+write) accesses 2696system.cpu1.l2cache.overall_accesses::cpu1.data 4989915 # number of overall (read+write) accesses 2697system.cpu1.l2cache.overall_accesses::total 11675039 # number of overall (read+write) accesses 2698system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.035265 # miss rate for ReadReq accesses 2699system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.049568 # miss rate for ReadReq accesses 2700system.cpu1.l2cache.ReadReq_miss_rate::total 0.038887 # miss rate for ReadReq accesses 2701system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999839 # miss rate for UpgradeReq accesses 2702system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999839 # miss rate for UpgradeReq accesses 2703system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.999995 # miss rate for SCUpgradeReq accesses 2704system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.999995 # miss rate for SCUpgradeReq accesses 2705system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses 2706system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses 2707system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.222629 # miss rate for ReadExReq accesses 2708system.cpu1.l2cache.ReadExReq_miss_rate::total 0.222629 # miss rate for ReadExReq accesses 2709system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.094846 # miss rate for ReadCleanReq accesses 2710system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.094846 # miss rate for ReadCleanReq accesses 2711system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.252673 # miss rate for ReadSharedReq accesses 2712system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.252673 # miss rate for ReadSharedReq accesses 2713system.cpu1.l2cache.InvalidateReq_miss_rate::cpu1.data 0.563151 # miss rate for InvalidateReq accesses 2714system.cpu1.l2cache.InvalidateReq_miss_rate::total 0.563151 # miss rate for InvalidateReq accesses 2715system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.035265 # miss rate for demand accesses 2716system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.049568 # miss rate for demand accesses 2717system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.094846 # miss rate for demand accesses 2718system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.245719 # miss rate for demand accesses 2719system.cpu1.l2cache.demand_miss_rate::total 0.155582 # miss rate for demand accesses 2720system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.035265 # miss rate for overall accesses 2721system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.049568 # miss rate for overall accesses 2722system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.094846 # miss rate for overall accesses 2723system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.245719 # miss rate for overall accesses 2724system.cpu1.l2cache.overall_miss_rate::total 0.155582 # miss rate for overall accesses 2725system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 32924.130561 # average ReadReq miss latency 2726system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 37190.959128 # average ReadReq miss latency 2727system.cpu1.l2cache.ReadReq_avg_miss_latency::total 34301.210566 # average ReadReq miss latency 2728system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 4272.033714 # average UpgradeReq miss latency 2729system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 4272.033714 # average UpgradeReq miss latency 2730system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 1412.896616 # average SCUpgradeReq miss latency 2731system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 1412.896616 # average SCUpgradeReq miss latency 2732system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 709875 # average SCUpgradeFailReq miss latency 2733system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 709875 # average SCUpgradeFailReq miss latency 2734system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 48739.193129 # average ReadExReq miss latency 2735system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 48739.193129 # average ReadExReq miss latency 2736system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 36741.268302 # average ReadCleanReq miss latency 2737system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 36741.268302 # average ReadCleanReq miss latency 2738system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 37216.101433 # average ReadSharedReq miss latency 2739system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 37216.101433 # average ReadSharedReq miss latency 2740system.cpu1.l2cache.InvalidateReq_avg_miss_latency::cpu1.data 1318.800488 # average InvalidateReq miss latency 2741system.cpu1.l2cache.InvalidateReq_avg_miss_latency::total 1318.800488 # average InvalidateReq miss latency 2742system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 32924.130561 # average overall miss latency 2743system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 37190.959128 # average overall miss latency 2744system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 36741.268302 # average overall miss latency 2745system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 39632.611000 # average overall miss latency 2746system.cpu1.l2cache.demand_avg_miss_latency::total 38652.130895 # average overall miss latency 2747system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 32924.130561 # average overall miss latency 2748system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 37190.959128 # average overall miss latency 2749system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 36741.268302 # average overall miss latency 2750system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 39632.611000 # average overall miss latency 2751system.cpu1.l2cache.overall_avg_miss_latency::total 38652.130895 # average overall miss latency 2752system.cpu1.l2cache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked 2753system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 2754system.cpu1.l2cache.blocked::no_mshrs 11 # number of cycles access was blocked 2755system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked 2756system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 28 # average number of cycles each access was blocked 2757system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 2758system.cpu1.l2cache.unused_prefetches 42085 # number of HardPF blocks evicted w/o reference 2759system.cpu1.l2cache.writebacks::writebacks 1170856 # number of writebacks 2760system.cpu1.l2cache.writebacks::total 1170856 # number of writebacks 2761system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 68 # number of ReadReq MSHR hits 2762system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 195 # number of ReadReq MSHR hits 2763system.cpu1.l2cache.ReadReq_mshr_hits::total 263 # number of ReadReq MSHR hits 2764system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 13529 # number of ReadExReq MSHR hits 2765system.cpu1.l2cache.ReadExReq_mshr_hits::total 13529 # number of ReadExReq MSHR hits 2766system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 3 # number of ReadCleanReq MSHR hits 2767system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 3 # number of ReadCleanReq MSHR hits 2768system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 4671 # number of ReadSharedReq MSHR hits 2769system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 4671 # number of ReadSharedReq MSHR hits 2770system.cpu1.l2cache.InvalidateReq_mshr_hits::cpu1.data 5 # number of InvalidateReq MSHR hits 2771system.cpu1.l2cache.InvalidateReq_mshr_hits::total 5 # number of InvalidateReq MSHR hits 2772system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 68 # number of demand (read+write) MSHR hits 2773system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 195 # number of demand (read+write) MSHR hits 2774system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 3 # number of demand (read+write) MSHR hits 2775system.cpu1.l2cache.demand_mshr_hits::cpu1.data 18200 # number of demand (read+write) MSHR hits 2776system.cpu1.l2cache.demand_mshr_hits::total 18466 # number of demand (read+write) MSHR hits 2777system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 68 # number of overall MSHR hits 2778system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 195 # number of overall MSHR hits 2779system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 3 # number of overall MSHR hits 2780system.cpu1.l2cache.overall_mshr_hits::cpu1.data 18200 # number of overall MSHR hits 2781system.cpu1.l2cache.overall_mshr_hits::total 18466 # number of overall MSHR hits 2782system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 20520 # number of ReadReq MSHR misses 2783system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 9616 # number of ReadReq MSHR misses 2784system.cpu1.l2cache.ReadReq_mshr_misses::total 30136 # number of ReadReq MSHR misses 2785system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 763352 # number of HardPFReq MSHR misses 2786system.cpu1.l2cache.HardPFReq_mshr_misses::total 763352 # number of HardPFReq MSHR misses 2787system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 230170 # number of UpgradeReq MSHR misses 2788system.cpu1.l2cache.UpgradeReq_mshr_misses::total 230170 # number of UpgradeReq MSHR misses 2789system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 192283 # number of SCUpgradeReq MSHR misses 2790system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 192283 # number of SCUpgradeReq MSHR misses 2791system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 4 # number of SCUpgradeFailReq MSHR misses 2792system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 4 # number of SCUpgradeFailReq MSHR misses 2793system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 243600 # number of ReadExReq MSHR misses 2794system.cpu1.l2cache.ReadExReq_mshr_misses::total 243600 # number of ReadExReq MSHR misses 2795system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 559911 # number of ReadCleanReq MSHR misses 2796system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 559911 # number of ReadCleanReq MSHR misses 2797system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 964316 # number of ReadSharedReq MSHR misses 2798system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 964316 # number of ReadSharedReq MSHR misses 2799system.cpu1.l2cache.InvalidateReq_mshr_misses::cpu1.data 258100 # number of InvalidateReq MSHR misses 2800system.cpu1.l2cache.InvalidateReq_mshr_misses::total 258100 # number of InvalidateReq MSHR misses 2801system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 20520 # number of demand (read+write) MSHR misses 2802system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 9616 # number of demand (read+write) MSHR misses 2803system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 559911 # number of demand (read+write) MSHR misses 2804system.cpu1.l2cache.demand_mshr_misses::cpu1.data 1207916 # number of demand (read+write) MSHR misses 2805system.cpu1.l2cache.demand_mshr_misses::total 1797963 # number of demand (read+write) MSHR misses 2806system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 20520 # number of overall MSHR misses 2807system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 9616 # number of overall MSHR misses 2808system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 559911 # number of overall MSHR misses 2809system.cpu1.l2cache.overall_mshr_misses::cpu1.data 1207916 # number of overall MSHR misses 2810system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 763352 # number of overall MSHR misses 2811system.cpu1.l2cache.overall_mshr_misses::total 2561315 # number of overall MSHR misses 2812system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 2813system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 21291 # number of ReadReq MSHR uncacheable 2814system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 21358 # number of ReadReq MSHR uncacheable 2815system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable 2816system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 19410 # number of WriteReq MSHR uncacheable 2817system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 2818system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 40701 # number of overall MSHR uncacheable misses 2819system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 40768 # number of overall MSHR uncacheable misses 2820system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 553404000 # number of ReadReq MSHR miss cycles 2821system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 304119000 # number of ReadReq MSHR miss cycles 2822system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 857523000 # number of ReadReq MSHR miss cycles 2823system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 42319154022 # number of HardPFReq MSHR miss cycles 2824system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 42319154022 # number of HardPFReq MSHR miss cycles 2825system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 4307815491 # number of UpgradeReq MSHR miss cycles 2826system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 4307815491 # number of UpgradeReq MSHR miss cycles 2827system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 2930523994 # number of SCUpgradeReq MSHR miss cycles 2828system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 2930523994 # number of SCUpgradeReq MSHR miss cycles 2829system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 2407500 # number of SCUpgradeFailReq MSHR miss cycles 2830system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 2407500 # number of SCUpgradeFailReq MSHR miss cycles 2831system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 8988147495 # number of ReadExReq MSHR miss cycles 2832system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 8988147495 # number of ReadExReq MSHR miss cycles 2833system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 17212365000 # number of ReadCleanReq MSHR miss cycles 2834system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 17212365000 # number of ReadCleanReq MSHR miss cycles 2835system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 29935787486 # number of ReadSharedReq MSHR miss cycles 2836system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 29935787486 # number of ReadSharedReq MSHR miss cycles 2837system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::cpu1.data 6963364497 # number of InvalidateReq MSHR miss cycles 2838system.cpu1.l2cache.InvalidateReq_mshr_miss_latency::total 6963364497 # number of InvalidateReq MSHR miss cycles 2839system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 553404000 # number of demand (read+write) MSHR miss cycles 2840system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 304119000 # number of demand (read+write) MSHR miss cycles 2841system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 17212365000 # number of demand (read+write) MSHR miss cycles 2842system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 38923934981 # number of demand (read+write) MSHR miss cycles 2843system.cpu1.l2cache.demand_mshr_miss_latency::total 56993822981 # number of demand (read+write) MSHR miss cycles 2844system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 553404000 # number of overall MSHR miss cycles 2845system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 304119000 # number of overall MSHR miss cycles 2846system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 17212365000 # number of overall MSHR miss cycles 2847system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 38923934981 # number of overall MSHR miss cycles 2848system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 42319154022 # number of overall MSHR miss cycles 2849system.cpu1.l2cache.overall_mshr_miss_latency::total 99312977003 # number of overall MSHR miss cycles 2850system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 6576000 # number of ReadReq MSHR uncacheable cycles 2851system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3627092000 # number of ReadReq MSHR uncacheable cycles 2852system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3633668000 # number of ReadReq MSHR uncacheable cycles 2853system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 6576000 # number of overall MSHR uncacheable cycles 2854system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3627092000 # number of overall MSHR uncacheable cycles 2855system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3633668000 # number of overall MSHR uncacheable cycles 2856system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for ReadReq accesses 2857system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for ReadReq accesses 2858system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.038550 # mshr miss rate for ReadReq accesses 2859system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 2860system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 2861system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.999839 # mshr miss rate for UpgradeReq accesses 2862system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.999839 # mshr miss rate for UpgradeReq accesses 2863system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999995 # mshr miss rate for SCUpgradeReq accesses 2864system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999995 # mshr miss rate for SCUpgradeReq accesses 2865system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses 2866system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses 2867system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.210915 # mshr miss rate for ReadExReq accesses 2868system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.210915 # mshr miss rate for ReadExReq accesses 2869system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for ReadCleanReq accesses 2870system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.094846 # mshr miss rate for ReadCleanReq accesses 2871system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.251455 # mshr miss rate for ReadSharedReq accesses 2872system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.251455 # mshr miss rate for ReadSharedReq accesses 2873system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::cpu1.data 0.563140 # mshr miss rate for InvalidateReq accesses 2874system.cpu1.l2cache.InvalidateReq_mshr_miss_rate::total 0.563140 # mshr miss rate for InvalidateReq accesses 2875system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for demand accesses 2876system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for demand accesses 2877system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for demand accesses 2878system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.242071 # mshr miss rate for demand accesses 2879system.cpu1.l2cache.demand_mshr_miss_rate::total 0.154001 # mshr miss rate for demand accesses 2880system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.035149 # mshr miss rate for overall accesses 2881system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.048583 # mshr miss rate for overall accesses 2882system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.094846 # mshr miss rate for overall accesses 2883system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.242071 # mshr miss rate for overall accesses 2884system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses 2885system.cpu1.l2cache.overall_mshr_miss_rate::total 0.219384 # mshr miss rate for overall accesses 2886system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average ReadReq mshr miss latency 2887system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average ReadReq mshr miss latency 2888system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 28455.103531 # average ReadReq mshr miss latency 2889system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063 # average HardPFReq mshr miss latency 2890system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 55438.584063 # average HardPFReq mshr miss latency 2891system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 18715.799153 # average UpgradeReq mshr miss latency 2892system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18715.799153 # average UpgradeReq mshr miss latency 2893system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15240.681672 # average SCUpgradeReq mshr miss latency 2894system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15240.681672 # average SCUpgradeReq mshr miss latency 2895system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 601875 # average SCUpgradeFailReq mshr miss latency 2896system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 601875 # average SCUpgradeFailReq mshr miss latency 2897system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36897.157204 # average ReadExReq mshr miss latency 2898system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36897.157204 # average ReadExReq mshr miss latency 2899system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average ReadCleanReq mshr miss latency 2900system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 30741.251735 # average ReadCleanReq mshr miss latency 2901system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 31043.545359 # average ReadSharedReq mshr miss latency 2902system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 31043.545359 # average ReadSharedReq mshr miss latency 2903system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::cpu1.data 26979.327768 # average InvalidateReq mshr miss latency 2904system.cpu1.l2cache.InvalidateReq_avg_mshr_miss_latency::total 26979.327768 # average InvalidateReq mshr miss latency 2905system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average overall mshr miss latency 2906system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average overall mshr miss latency 2907system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average overall mshr miss latency 2908system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 32224.041226 # average overall mshr miss latency 2909system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 31699.107813 # average overall mshr miss latency 2910system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 26969.005848 # average overall mshr miss latency 2911system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 31626.351913 # average overall mshr miss latency 2912system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 30741.251735 # average overall mshr miss latency 2913system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 32224.041226 # average overall mshr miss latency 2914system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 55438.584063 # average overall mshr miss latency 2915system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 38774.214418 # average overall mshr miss latency 2916system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average ReadReq mshr uncacheable latency 2917system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170357.991640 # average ReadReq mshr uncacheable latency 2918system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 170131.472984 # average ReadReq mshr uncacheable latency 2919system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98149.253731 # average overall mshr uncacheable latency 2920system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 89115.549986 # average overall mshr uncacheable latency 2921system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 89130.396389 # average overall mshr uncacheable latency 2922system.cpu1.toL2Bus.snoop_filter.tot_requests 23401917 # Total number of requests made to the snoop filter. 2923system.cpu1.toL2Bus.snoop_filter.hit_single_requests 12050394 # Number of requests hitting in the snoop filter with a single holder of the requested data. 2924system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 1685 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 2925system.cpu1.toL2Bus.snoop_filter.tot_snoops 583324 # Total number of snoops made to the snoop filter. 2926system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 583320 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 2927system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 4 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 2928system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 2929system.cpu1.toL2Bus.trans_dist::ReadReq 895492 # Transaction distribution 2930system.cpu1.toL2Bus.trans_dist::ReadResp 10720388 # Transaction distribution 2931system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 2 # Transaction distribution 2932system.cpu1.toL2Bus.trans_dist::WriteReq 19410 # Transaction distribution 2933system.cpu1.toL2Bus.trans_dist::WriteResp 19410 # Transaction distribution 2934system.cpu1.toL2Bus.trans_dist::WritebackDirty 4582624 # Transaction distribution 2935system.cpu1.toL2Bus.trans_dist::WritebackClean 7861129 # Transaction distribution 2936system.cpu1.toL2Bus.trans_dist::CleanEvict 1298468 # Transaction distribution 2937system.cpu1.toL2Bus.trans_dist::HardPFReq 967756 # Transaction distribution 2938system.cpu1.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution 2939system.cpu1.toL2Bus.trans_dist::UpgradeReq 436519 # Transaction distribution 2940system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 348532 # Transaction distribution 2941system.cpu1.toL2Bus.trans_dist::UpgradeResp 480708 # Transaction distribution 2942system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 65 # Transaction distribution 2943system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 2944system.cpu1.toL2Bus.trans_dist::ReadExReq 1183332 # Transaction distribution 2945system.cpu1.toL2Bus.trans_dist::ReadExResp 1160512 # Transaction distribution 2946system.cpu1.toL2Bus.trans_dist::ReadCleanReq 5903405 # Transaction distribution 2947system.cpu1.toL2Bus.trans_dist::ReadSharedReq 4845353 # Transaction distribution 2948system.cpu1.toL2Bus.trans_dist::InvalidateReq 522418 # Transaction distribution 2949system.cpu1.toL2Bus.trans_dist::InvalidateResp 458323 # Transaction distribution 2950system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 17709789 # Packet count per connected master and slave (bytes) 2951system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 17335665 # Packet count per connected master and slave (bytes) 2952system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 416038 # Packet count per connected master and slave (bytes) 2953system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1239832 # Packet count per connected master and slave (bytes) 2954system.cpu1.toL2Bus.pkt_count::total 36701324 # Packet count per connected master and slave (bytes) 2955system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 755601072 # Cumulative packet size per connected master and slave (bytes) 2956system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 668583302 # Cumulative packet size per connected master and slave (bytes) 2957system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1583448 # Cumulative packet size per connected master and slave (bytes) 2958system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 4670440 # Cumulative packet size per connected master and slave (bytes) 2959system.cpu1.toL2Bus.pkt_size::total 1430438262 # Cumulative packet size per connected master and slave (bytes) 2960system.cpu1.toL2Bus.snoops 5153113 # Total snoops (count) 2961system.cpu1.toL2Bus.snoopTraffic 82064432 # Total snoop traffic (bytes) 2962system.cpu1.toL2Bus.snoop_fanout::samples 17599300 # Request fanout histogram 2963system.cpu1.toL2Bus.snoop_fanout::mean 0.053842 # Request fanout histogram 2964system.cpu1.toL2Bus.snoop_fanout::stdev 0.225707 # Request fanout histogram 2965system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 2966system.cpu1.toL2Bus.snoop_fanout::0 16651717 94.62% 94.62% # Request fanout histogram 2967system.cpu1.toL2Bus.snoop_fanout::1 947579 5.38% 100.00% # Request fanout histogram 2968system.cpu1.toL2Bus.snoop_fanout::2 4 0.00% 100.00% # Request fanout histogram 2969system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 2970system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 2971system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 2972system.cpu1.toL2Bus.snoop_fanout::total 17599300 # Request fanout histogram 2973system.cpu1.toL2Bus.reqLayer0.occupancy 23252082447 # Layer occupancy (ticks) 2974system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 2975system.cpu1.toL2Bus.snoopLayer0.occupancy 167523282 # Layer occupancy (ticks) 2976system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 2977system.cpu1.toL2Bus.respLayer0.occupancy 8861086123 # Layer occupancy (ticks) 2978system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 2979system.cpu1.toL2Bus.respLayer1.occupancy 7965231666 # Layer occupancy (ticks) 2980system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 2981system.cpu1.toL2Bus.respLayer2.occupancy 218506693 # Layer occupancy (ticks) 2982system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) 2983system.cpu1.toL2Bus.respLayer3.occupancy 656902733 # Layer occupancy (ticks) 2984system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) 2985system.iobus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 2986system.iobus.trans_dist::ReadReq 40332 # Transaction distribution 2987system.iobus.trans_dist::ReadResp 40332 # Transaction distribution 2988system.iobus.trans_dist::WriteReq 136631 # Transaction distribution 2989system.iobus.trans_dist::WriteResp 136631 # Transaction distribution 2990system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47650 # Packet count per connected master and slave (bytes) 2991system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes) 2992system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) 2993system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes) 2994system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes) 2995system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) 2996system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) 2997system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) 2998system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) 2999system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes) 3000system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) 3001system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes) 3002system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes) 3003system.iobus.pkt_count_system.bridge.master::total 122584 # Packet count per connected master and slave (bytes) 3004system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231262 # Packet count per connected master and slave (bytes) 3005system.iobus.pkt_count_system.realview.ide.dma::total 231262 # Packet count per connected master and slave (bytes) 3006system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes) 3007system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes) 3008system.iobus.pkt_count::total 353926 # Packet count per connected master and slave (bytes) 3009system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47670 # Cumulative packet size per connected master and slave (bytes) 3010system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes) 3011system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 634 # Cumulative packet size per connected master and slave (bytes) 3012system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes) 3013system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes) 3014system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) 3015system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3016system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3017system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3018system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes) 3019system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) 3020system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes) 3021system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes) 3022system.iobus.pkt_size_system.bridge.master::total 155691 # Cumulative packet size per connected master and slave (bytes) 3023system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339064 # Cumulative packet size per connected master and slave (bytes) 3024system.iobus.pkt_size_system.realview.ide.dma::total 7339064 # Cumulative packet size per connected master and slave (bytes) 3025system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes) 3026system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes) 3027system.iobus.pkt_size::total 7496841 # Cumulative packet size per connected master and slave (bytes) 3028system.iobus.reqLayer0.occupancy 36933004 # Layer occupancy (ticks) 3029system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) 3030system.iobus.reqLayer1.occupancy 9500 # Layer occupancy (ticks) 3031system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) 3032system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) 3033system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) 3034system.iobus.reqLayer3.occupancy 10500 # Layer occupancy (ticks) 3035system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) 3036system.iobus.reqLayer4.occupancy 10500 # Layer occupancy (ticks) 3037system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) 3038system.iobus.reqLayer10.occupancy 10500 # Layer occupancy (ticks) 3039system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) 3040system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) 3041system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) 3042system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) 3043system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) 3044system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) 3045system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) 3046system.iobus.reqLayer16.occupancy 13000 # Layer occupancy (ticks) 3047system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) 3048system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) 3049system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) 3050system.iobus.reqLayer23.occupancy 24511500 # Layer occupancy (ticks) 3051system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) 3052system.iobus.reqLayer24.occupancy 36406001 # Layer occupancy (ticks) 3053system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) 3054system.iobus.reqLayer25.occupancy 569333352 # Layer occupancy (ticks) 3055system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) 3056system.iobus.respLayer0.occupancy 92684000 # Layer occupancy (ticks) 3057system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) 3058system.iobus.respLayer3.occupancy 147958000 # Layer occupancy (ticks) 3059system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) 3060system.iobus.respLayer4.occupancy 170000 # Layer occupancy (ticks) 3061system.iobus.respLayer4.utilization 0.0 # Layer utilization (%) 3062system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3063system.iocache.tags.replacements 115627 # number of replacements 3064system.iocache.tags.tagsinuse 11.209625 # Cycle average of tags in use 3065system.iocache.tags.total_refs 3 # Total number of references to valid blocks. 3066system.iocache.tags.sampled_refs 115643 # Sample count of references to valid blocks. 3067system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks. 3068system.iocache.tags.warmup_cycle 9156281985000 # Cycle when the warmup percentage was hit. 3069system.iocache.tags.occ_blocks::realview.ethernet 7.417323 # Average occupied blocks per requestor 3070system.iocache.tags.occ_blocks::realview.ide 3.792302 # Average occupied blocks per requestor 3071system.iocache.tags.occ_percent::realview.ethernet 0.463583 # Average percentage of cache occupancy 3072system.iocache.tags.occ_percent::realview.ide 0.237019 # Average percentage of cache occupancy 3073system.iocache.tags.occ_percent::total 0.700602 # Average percentage of cache occupancy 3074system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 3075system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id 3076system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 3077system.iocache.tags.tag_accesses 1041036 # Number of tag accesses 3078system.iocache.tags.data_accesses 1041036 # Number of data accesses 3079system.iocache.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3080system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses 3081system.iocache.ReadReq_misses::realview.ide 8903 # number of ReadReq misses 3082system.iocache.ReadReq_misses::total 8940 # number of ReadReq misses 3083system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses 3084system.iocache.WriteReq_misses::total 3 # number of WriteReq misses 3085system.iocache.WriteLineReq_misses::realview.ide 106728 # number of WriteLineReq misses 3086system.iocache.WriteLineReq_misses::total 106728 # number of WriteLineReq misses 3087system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses 3088system.iocache.demand_misses::realview.ide 115631 # number of demand (read+write) misses 3089system.iocache.demand_misses::total 115671 # number of demand (read+write) misses 3090system.iocache.overall_misses::realview.ethernet 40 # number of overall misses 3091system.iocache.overall_misses::realview.ide 115631 # number of overall misses 3092system.iocache.overall_misses::total 115671 # number of overall misses 3093system.iocache.ReadReq_miss_latency::realview.ethernet 5200000 # number of ReadReq miss cycles 3094system.iocache.ReadReq_miss_latency::realview.ide 1786499757 # number of ReadReq miss cycles 3095system.iocache.ReadReq_miss_latency::total 1791699757 # number of ReadReq miss cycles 3096system.iocache.WriteReq_miss_latency::realview.ethernet 369000 # number of WriteReq miss cycles 3097system.iocache.WriteReq_miss_latency::total 369000 # number of WriteReq miss cycles 3098system.iocache.WriteLineReq_miss_latency::realview.ide 13185420595 # number of WriteLineReq miss cycles 3099system.iocache.WriteLineReq_miss_latency::total 13185420595 # number of WriteLineReq miss cycles 3100system.iocache.demand_miss_latency::realview.ethernet 5569000 # number of demand (read+write) miss cycles 3101system.iocache.demand_miss_latency::realview.ide 14971920352 # number of demand (read+write) miss cycles 3102system.iocache.demand_miss_latency::total 14977489352 # number of demand (read+write) miss cycles 3103system.iocache.overall_miss_latency::realview.ethernet 5569000 # number of overall miss cycles 3104system.iocache.overall_miss_latency::realview.ide 14971920352 # number of overall miss cycles 3105system.iocache.overall_miss_latency::total 14977489352 # number of overall miss cycles 3106system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses) 3107system.iocache.ReadReq_accesses::realview.ide 8903 # number of ReadReq accesses(hits+misses) 3108system.iocache.ReadReq_accesses::total 8940 # number of ReadReq accesses(hits+misses) 3109system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses) 3110system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses) 3111system.iocache.WriteLineReq_accesses::realview.ide 106728 # number of WriteLineReq accesses(hits+misses) 3112system.iocache.WriteLineReq_accesses::total 106728 # number of WriteLineReq accesses(hits+misses) 3113system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses 3114system.iocache.demand_accesses::realview.ide 115631 # number of demand (read+write) accesses 3115system.iocache.demand_accesses::total 115671 # number of demand (read+write) accesses 3116system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses 3117system.iocache.overall_accesses::realview.ide 115631 # number of overall (read+write) accesses 3118system.iocache.overall_accesses::total 115671 # number of overall (read+write) accesses 3119system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses 3120system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses 3121system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 3122system.iocache.WriteReq_miss_rate::realview.ethernet 1 # miss rate for WriteReq accesses 3123system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses 3124system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses 3125system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 3126system.iocache.demand_miss_rate::realview.ethernet 1 # miss rate for demand accesses 3127system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses 3128system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 3129system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses 3130system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses 3131system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 3132system.iocache.ReadReq_avg_miss_latency::realview.ethernet 140540.540541 # average ReadReq miss latency 3133system.iocache.ReadReq_avg_miss_latency::realview.ide 200662.670673 # average ReadReq miss latency 3134system.iocache.ReadReq_avg_miss_latency::total 200413.843065 # average ReadReq miss latency 3135system.iocache.WriteReq_avg_miss_latency::realview.ethernet 123000 # average WriteReq miss latency 3136system.iocache.WriteReq_avg_miss_latency::total 123000 # average WriteReq miss latency 3137system.iocache.WriteLineReq_avg_miss_latency::realview.ide 123542.281266 # average WriteLineReq miss latency 3138system.iocache.WriteLineReq_avg_miss_latency::total 123542.281266 # average WriteLineReq miss latency 3139system.iocache.demand_avg_miss_latency::realview.ethernet 139225 # average overall miss latency 3140system.iocache.demand_avg_miss_latency::realview.ide 129480.159750 # average overall miss latency 3141system.iocache.demand_avg_miss_latency::total 129483.529597 # average overall miss latency 3142system.iocache.overall_avg_miss_latency::realview.ethernet 139225 # average overall miss latency 3143system.iocache.overall_avg_miss_latency::realview.ide 129480.159750 # average overall miss latency 3144system.iocache.overall_avg_miss_latency::total 129483.529597 # average overall miss latency 3145system.iocache.blocked_cycles::no_mshrs 39692 # number of cycles access was blocked 3146system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 3147system.iocache.blocked::no_mshrs 3537 # number of cycles access was blocked 3148system.iocache.blocked::no_targets 0 # number of cycles access was blocked 3149system.iocache.avg_blocked_cycles::no_mshrs 11.221939 # average number of cycles each access was blocked 3150system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3151system.iocache.writebacks::writebacks 106694 # number of writebacks 3152system.iocache.writebacks::total 106694 # number of writebacks 3153system.iocache.ReadReq_mshr_misses::realview.ethernet 37 # number of ReadReq MSHR misses 3154system.iocache.ReadReq_mshr_misses::realview.ide 8903 # number of ReadReq MSHR misses 3155system.iocache.ReadReq_mshr_misses::total 8940 # number of ReadReq MSHR misses 3156system.iocache.WriteReq_mshr_misses::realview.ethernet 3 # number of WriteReq MSHR misses 3157system.iocache.WriteReq_mshr_misses::total 3 # number of WriteReq MSHR misses 3158system.iocache.WriteLineReq_mshr_misses::realview.ide 106728 # number of WriteLineReq MSHR misses 3159system.iocache.WriteLineReq_mshr_misses::total 106728 # number of WriteLineReq MSHR misses 3160system.iocache.demand_mshr_misses::realview.ethernet 40 # number of demand (read+write) MSHR misses 3161system.iocache.demand_mshr_misses::realview.ide 115631 # number of demand (read+write) MSHR misses 3162system.iocache.demand_mshr_misses::total 115671 # number of demand (read+write) MSHR misses 3163system.iocache.overall_mshr_misses::realview.ethernet 40 # number of overall MSHR misses 3164system.iocache.overall_mshr_misses::realview.ide 115631 # number of overall MSHR misses 3165system.iocache.overall_mshr_misses::total 115671 # number of overall MSHR misses 3166system.iocache.ReadReq_mshr_miss_latency::realview.ethernet 3350000 # number of ReadReq MSHR miss cycles 3167system.iocache.ReadReq_mshr_miss_latency::realview.ide 1341349757 # number of ReadReq MSHR miss cycles 3168system.iocache.ReadReq_mshr_miss_latency::total 1344699757 # number of ReadReq MSHR miss cycles 3169system.iocache.WriteReq_mshr_miss_latency::realview.ethernet 219000 # number of WriteReq MSHR miss cycles 3170system.iocache.WriteReq_mshr_miss_latency::total 219000 # number of WriteReq MSHR miss cycles 3171system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 7839860905 # number of WriteLineReq MSHR miss cycles 3172system.iocache.WriteLineReq_mshr_miss_latency::total 7839860905 # number of WriteLineReq MSHR miss cycles 3173system.iocache.demand_mshr_miss_latency::realview.ethernet 3569000 # number of demand (read+write) MSHR miss cycles 3174system.iocache.demand_mshr_miss_latency::realview.ide 9181210662 # number of demand (read+write) MSHR miss cycles 3175system.iocache.demand_mshr_miss_latency::total 9184779662 # number of demand (read+write) MSHR miss cycles 3176system.iocache.overall_mshr_miss_latency::realview.ethernet 3569000 # number of overall MSHR miss cycles 3177system.iocache.overall_mshr_miss_latency::realview.ide 9181210662 # number of overall MSHR miss cycles 3178system.iocache.overall_mshr_miss_latency::total 9184779662 # number of overall MSHR miss cycles 3179system.iocache.ReadReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for ReadReq accesses 3180system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses 3181system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses 3182system.iocache.WriteReq_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for WriteReq accesses 3183system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses 3184system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses 3185system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses 3186system.iocache.demand_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for demand accesses 3187system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses 3188system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 3189system.iocache.overall_mshr_miss_rate::realview.ethernet 1 # mshr miss rate for overall accesses 3190system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses 3191system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 3192system.iocache.ReadReq_avg_mshr_miss_latency::realview.ethernet 90540.540541 # average ReadReq mshr miss latency 3193system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 150662.670673 # average ReadReq mshr miss latency 3194system.iocache.ReadReq_avg_mshr_miss_latency::total 150413.843065 # average ReadReq mshr miss latency 3195system.iocache.WriteReq_avg_mshr_miss_latency::realview.ethernet 73000 # average WriteReq mshr miss latency 3196system.iocache.WriteReq_avg_mshr_miss_latency::total 73000 # average WriteReq mshr miss latency 3197system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 73456.458521 # average WriteLineReq mshr miss latency 3198system.iocache.WriteLineReq_avg_mshr_miss_latency::total 73456.458521 # average WriteLineReq mshr miss latency 3199system.iocache.demand_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency 3200system.iocache.demand_avg_mshr_miss_latency::realview.ide 79400.944920 # average overall mshr miss latency 3201system.iocache.demand_avg_mshr_miss_latency::total 79404.342160 # average overall mshr miss latency 3202system.iocache.overall_avg_mshr_miss_latency::realview.ethernet 89225 # average overall mshr miss latency 3203system.iocache.overall_avg_mshr_miss_latency::realview.ide 79400.944920 # average overall mshr miss latency 3204system.iocache.overall_avg_mshr_miss_latency::total 79404.342160 # average overall mshr miss latency 3205system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3206system.l2c.tags.replacements 1712520 # number of replacements 3207system.l2c.tags.tagsinuse 65207.555116 # Cycle average of tags in use 3208system.l2c.tags.total_refs 7020190 # Total number of references to valid blocks. 3209system.l2c.tags.sampled_refs 1774780 # Sample count of references to valid blocks. 3210system.l2c.tags.avg_refs 3.955527 # Average number of references to valid blocks. 3211system.l2c.tags.warmup_cycle 3083323500 # Cycle when the warmup percentage was hit. 3212system.l2c.tags.occ_blocks::writebacks 10815.100932 # Average occupied blocks per requestor 3213system.l2c.tags.occ_blocks::cpu0.dtb.walker 305.602667 # Average occupied blocks per requestor 3214system.l2c.tags.occ_blocks::cpu0.itb.walker 366.195320 # Average occupied blocks per requestor 3215system.l2c.tags.occ_blocks::cpu0.inst 3964.024216 # Average occupied blocks per requestor 3216system.l2c.tags.occ_blocks::cpu0.data 19638.791484 # Average occupied blocks per requestor 3217system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 14261.868883 # Average occupied blocks per requestor 3218system.l2c.tags.occ_blocks::cpu1.dtb.walker 151.853339 # Average occupied blocks per requestor 3219system.l2c.tags.occ_blocks::cpu1.itb.walker 181.379081 # Average occupied blocks per requestor 3220system.l2c.tags.occ_blocks::cpu1.inst 3223.101636 # Average occupied blocks per requestor 3221system.l2c.tags.occ_blocks::cpu1.data 5938.767305 # Average occupied blocks per requestor 3222system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6360.870252 # Average occupied blocks per requestor 3223system.l2c.tags.occ_percent::writebacks 0.165025 # Average percentage of cache occupancy 3224system.l2c.tags.occ_percent::cpu0.dtb.walker 0.004663 # Average percentage of cache occupancy 3225system.l2c.tags.occ_percent::cpu0.itb.walker 0.005588 # Average percentage of cache occupancy 3226system.l2c.tags.occ_percent::cpu0.inst 0.060486 # Average percentage of cache occupancy 3227system.l2c.tags.occ_percent::cpu0.data 0.299664 # Average percentage of cache occupancy 3228system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.217619 # Average percentage of cache occupancy 3229system.l2c.tags.occ_percent::cpu1.dtb.walker 0.002317 # Average percentage of cache occupancy 3230system.l2c.tags.occ_percent::cpu1.itb.walker 0.002768 # Average percentage of cache occupancy 3231system.l2c.tags.occ_percent::cpu1.inst 0.049181 # Average percentage of cache occupancy 3232system.l2c.tags.occ_percent::cpu1.data 0.090618 # Average percentage of cache occupancy 3233system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.097059 # Average percentage of cache occupancy 3234system.l2c.tags.occ_percent::total 0.994988 # Average percentage of cache occupancy 3235system.l2c.tags.occ_task_id_blocks::1022 11498 # Occupied blocks per task id 3236system.l2c.tags.occ_task_id_blocks::1023 249 # Occupied blocks per task id 3237system.l2c.tags.occ_task_id_blocks::1024 50513 # Occupied blocks per task id 3238system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id 3239system.l2c.tags.age_task_id_blocks_1022::2 1395 # Occupied blocks per task id 3240system.l2c.tags.age_task_id_blocks_1022::3 577 # Occupied blocks per task id 3241system.l2c.tags.age_task_id_blocks_1022::4 9525 # Occupied blocks per task id 3242system.l2c.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id 3243system.l2c.tags.age_task_id_blocks_1023::4 246 # Occupied blocks per task id 3244system.l2c.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 3245system.l2c.tags.age_task_id_blocks_1024::1 271 # Occupied blocks per task id 3246system.l2c.tags.age_task_id_blocks_1024::2 2497 # Occupied blocks per task id 3247system.l2c.tags.age_task_id_blocks_1024::3 4893 # Occupied blocks per task id 3248system.l2c.tags.age_task_id_blocks_1024::4 42814 # Occupied blocks per task id 3249system.l2c.tags.occ_task_id_percent::1022 0.175446 # Percentage of cache occupancy per task id 3250system.l2c.tags.occ_task_id_percent::1023 0.003799 # Percentage of cache occupancy per task id 3251system.l2c.tags.occ_task_id_percent::1024 0.770767 # Percentage of cache occupancy per task id 3252system.l2c.tags.tag_accesses 80570058 # Number of tag accesses 3253system.l2c.tags.data_accesses 80570058 # Number of data accesses 3254system.l2c.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3255system.l2c.WritebackDirty_hits::writebacks 2973062 # number of WritebackDirty hits 3256system.l2c.WritebackDirty_hits::total 2973062 # number of WritebackDirty hits 3257system.l2c.UpgradeReq_hits::cpu0.data 212913 # number of UpgradeReq hits 3258system.l2c.UpgradeReq_hits::cpu1.data 179277 # number of UpgradeReq hits 3259system.l2c.UpgradeReq_hits::total 392190 # number of UpgradeReq hits 3260system.l2c.SCUpgradeReq_hits::cpu0.data 55777 # number of SCUpgradeReq hits 3261system.l2c.SCUpgradeReq_hits::cpu1.data 49656 # number of SCUpgradeReq hits 3262system.l2c.SCUpgradeReq_hits::total 105433 # number of SCUpgradeReq hits 3263system.l2c.ReadExReq_hits::cpu0.data 53324 # number of ReadExReq hits 3264system.l2c.ReadExReq_hits::cpu1.data 56619 # number of ReadExReq hits 3265system.l2c.ReadExReq_hits::total 109943 # number of ReadExReq hits 3266system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 12274 # number of ReadSharedReq hits 3267system.l2c.ReadSharedReq_hits::cpu0.itb.walker 4633 # number of ReadSharedReq hits 3268system.l2c.ReadSharedReq_hits::cpu0.inst 532793 # number of ReadSharedReq hits 3269system.l2c.ReadSharedReq_hits::cpu0.data 642111 # number of ReadSharedReq hits 3270system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 285366 # number of ReadSharedReq hits 3271system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 12502 # number of ReadSharedReq hits 3272system.l2c.ReadSharedReq_hits::cpu1.itb.walker 5292 # number of ReadSharedReq hits 3273system.l2c.ReadSharedReq_hits::cpu1.inst 506134 # number of ReadSharedReq hits 3274system.l2c.ReadSharedReq_hits::cpu1.data 588825 # number of ReadSharedReq hits 3275system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 298655 # number of ReadSharedReq hits 3276system.l2c.ReadSharedReq_hits::total 2888585 # number of ReadSharedReq hits 3277system.l2c.InvalidateReq_hits::cpu0.data 133712 # number of InvalidateReq hits 3278system.l2c.InvalidateReq_hits::cpu1.data 132940 # number of InvalidateReq hits 3279system.l2c.InvalidateReq_hits::total 266652 # number of InvalidateReq hits 3280system.l2c.demand_hits::cpu0.dtb.walker 12274 # number of demand (read+write) hits 3281system.l2c.demand_hits::cpu0.itb.walker 4633 # number of demand (read+write) hits 3282system.l2c.demand_hits::cpu0.inst 532793 # number of demand (read+write) hits 3283system.l2c.demand_hits::cpu0.data 695435 # number of demand (read+write) hits 3284system.l2c.demand_hits::cpu0.l2cache.prefetcher 285366 # number of demand (read+write) hits 3285system.l2c.demand_hits::cpu1.dtb.walker 12502 # number of demand (read+write) hits 3286system.l2c.demand_hits::cpu1.itb.walker 5292 # number of demand (read+write) hits 3287system.l2c.demand_hits::cpu1.inst 506134 # number of demand (read+write) hits 3288system.l2c.demand_hits::cpu1.data 645444 # number of demand (read+write) hits 3289system.l2c.demand_hits::cpu1.l2cache.prefetcher 298655 # number of demand (read+write) hits 3290system.l2c.demand_hits::total 2998528 # number of demand (read+write) hits 3291system.l2c.overall_hits::cpu0.dtb.walker 12274 # number of overall hits 3292system.l2c.overall_hits::cpu0.itb.walker 4633 # number of overall hits 3293system.l2c.overall_hits::cpu0.inst 532793 # number of overall hits 3294system.l2c.overall_hits::cpu0.data 695435 # number of overall hits 3295system.l2c.overall_hits::cpu0.l2cache.prefetcher 285366 # number of overall hits 3296system.l2c.overall_hits::cpu1.dtb.walker 12502 # number of overall hits 3297system.l2c.overall_hits::cpu1.itb.walker 5292 # number of overall hits 3298system.l2c.overall_hits::cpu1.inst 506134 # number of overall hits 3299system.l2c.overall_hits::cpu1.data 645444 # number of overall hits 3300system.l2c.overall_hits::cpu1.l2cache.prefetcher 298655 # number of overall hits 3301system.l2c.overall_hits::total 2998528 # number of overall hits 3302system.l2c.UpgradeReq_misses::cpu0.data 25668 # number of UpgradeReq misses 3303system.l2c.UpgradeReq_misses::cpu1.data 25681 # number of UpgradeReq misses 3304system.l2c.UpgradeReq_misses::total 51349 # number of UpgradeReq misses 3305system.l2c.SCUpgradeReq_misses::cpu0.data 646 # number of SCUpgradeReq misses 3306system.l2c.SCUpgradeReq_misses::cpu1.data 809 # number of SCUpgradeReq misses 3307system.l2c.SCUpgradeReq_misses::total 1455 # number of SCUpgradeReq misses 3308system.l2c.ReadExReq_misses::cpu0.data 94289 # number of ReadExReq misses 3309system.l2c.ReadExReq_misses::cpu1.data 48061 # number of ReadExReq misses 3310system.l2c.ReadExReq_misses::total 142350 # number of ReadExReq misses 3311system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 3531 # number of ReadSharedReq misses 3312system.l2c.ReadSharedReq_misses::cpu0.itb.walker 3298 # number of ReadSharedReq misses 3313system.l2c.ReadSharedReq_misses::cpu0.inst 60576 # number of ReadSharedReq misses 3314system.l2c.ReadSharedReq_misses::cpu0.data 185593 # number of ReadSharedReq misses 3315system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 348444 # number of ReadSharedReq misses 3316system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 2063 # number of ReadSharedReq misses 3317system.l2c.ReadSharedReq_misses::cpu1.itb.walker 1546 # number of ReadSharedReq misses 3318system.l2c.ReadSharedReq_misses::cpu1.inst 53773 # number of ReadSharedReq misses 3319system.l2c.ReadSharedReq_misses::cpu1.data 117277 # number of ReadSharedReq misses 3320system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 240910 # number of ReadSharedReq misses 3321system.l2c.ReadSharedReq_misses::total 1017011 # number of ReadSharedReq misses 3322system.l2c.InvalidateReq_misses::cpu0.data 478287 # number of InvalidateReq misses 3323system.l2c.InvalidateReq_misses::cpu1.data 112149 # number of InvalidateReq misses 3324system.l2c.InvalidateReq_misses::total 590436 # number of InvalidateReq misses 3325system.l2c.demand_misses::cpu0.dtb.walker 3531 # number of demand (read+write) misses 3326system.l2c.demand_misses::cpu0.itb.walker 3298 # number of demand (read+write) misses 3327system.l2c.demand_misses::cpu0.inst 60576 # number of demand (read+write) misses 3328system.l2c.demand_misses::cpu0.data 279882 # number of demand (read+write) misses 3329system.l2c.demand_misses::cpu0.l2cache.prefetcher 348444 # number of demand (read+write) misses 3330system.l2c.demand_misses::cpu1.dtb.walker 2063 # number of demand (read+write) misses 3331system.l2c.demand_misses::cpu1.itb.walker 1546 # number of demand (read+write) misses 3332system.l2c.demand_misses::cpu1.inst 53773 # number of demand (read+write) misses 3333system.l2c.demand_misses::cpu1.data 165338 # number of demand (read+write) misses 3334system.l2c.demand_misses::cpu1.l2cache.prefetcher 240910 # number of demand (read+write) misses 3335system.l2c.demand_misses::total 1159361 # number of demand (read+write) misses 3336system.l2c.overall_misses::cpu0.dtb.walker 3531 # number of overall misses 3337system.l2c.overall_misses::cpu0.itb.walker 3298 # number of overall misses 3338system.l2c.overall_misses::cpu0.inst 60576 # number of overall misses 3339system.l2c.overall_misses::cpu0.data 279882 # number of overall misses 3340system.l2c.overall_misses::cpu0.l2cache.prefetcher 348444 # number of overall misses 3341system.l2c.overall_misses::cpu1.dtb.walker 2063 # number of overall misses 3342system.l2c.overall_misses::cpu1.itb.walker 1546 # number of overall misses 3343system.l2c.overall_misses::cpu1.inst 53773 # number of overall misses 3344system.l2c.overall_misses::cpu1.data 165338 # number of overall misses 3345system.l2c.overall_misses::cpu1.l2cache.prefetcher 240910 # number of overall misses 3346system.l2c.overall_misses::total 1159361 # number of overall misses 3347system.l2c.UpgradeReq_miss_latency::cpu0.data 172222000 # number of UpgradeReq miss cycles 3348system.l2c.UpgradeReq_miss_latency::cpu1.data 155225500 # number of UpgradeReq miss cycles 3349system.l2c.UpgradeReq_miss_latency::total 327447500 # number of UpgradeReq miss cycles 3350system.l2c.SCUpgradeReq_miss_latency::cpu0.data 9175000 # number of SCUpgradeReq miss cycles 3351system.l2c.SCUpgradeReq_miss_latency::cpu1.data 5803000 # number of SCUpgradeReq miss cycles 3352system.l2c.SCUpgradeReq_miss_latency::total 14978000 # number of SCUpgradeReq miss cycles 3353system.l2c.ReadExReq_miss_latency::cpu0.data 10233917991 # number of ReadExReq miss cycles 3354system.l2c.ReadExReq_miss_latency::cpu1.data 5260660499 # number of ReadExReq miss cycles 3355system.l2c.ReadExReq_miss_latency::total 15494578490 # number of ReadExReq miss cycles 3356system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 356299000 # number of ReadSharedReq miss cycles 3357system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 337167500 # number of ReadSharedReq miss cycles 3358system.l2c.ReadSharedReq_miss_latency::cpu0.inst 6654556500 # number of ReadSharedReq miss cycles 3359system.l2c.ReadSharedReq_miss_latency::cpu0.data 20784674000 # number of ReadSharedReq miss cycles 3360system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 53218202875 # number of ReadSharedReq miss cycles 3361system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 218154000 # number of ReadSharedReq miss cycles 3362system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 160424000 # number of ReadSharedReq miss cycles 3363system.l2c.ReadSharedReq_miss_latency::cpu1.inst 6046329000 # number of ReadSharedReq miss cycles 3364system.l2c.ReadSharedReq_miss_latency::cpu1.data 13882177499 # number of ReadSharedReq miss cycles 3365system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 36908535986 # number of ReadSharedReq miss cycles 3366system.l2c.ReadSharedReq_miss_latency::total 138566520360 # number of ReadSharedReq miss cycles 3367system.l2c.InvalidateReq_miss_latency::cpu0.data 31590000 # number of InvalidateReq miss cycles 3368system.l2c.InvalidateReq_miss_latency::cpu1.data 32968000 # number of InvalidateReq miss cycles 3369system.l2c.InvalidateReq_miss_latency::total 64558000 # number of InvalidateReq miss cycles 3370system.l2c.demand_miss_latency::cpu0.dtb.walker 356299000 # number of demand (read+write) miss cycles 3371system.l2c.demand_miss_latency::cpu0.itb.walker 337167500 # number of demand (read+write) miss cycles 3372system.l2c.demand_miss_latency::cpu0.inst 6654556500 # number of demand (read+write) miss cycles 3373system.l2c.demand_miss_latency::cpu0.data 31018591991 # number of demand (read+write) miss cycles 3374system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 53218202875 # number of demand (read+write) miss cycles 3375system.l2c.demand_miss_latency::cpu1.dtb.walker 218154000 # number of demand (read+write) miss cycles 3376system.l2c.demand_miss_latency::cpu1.itb.walker 160424000 # number of demand (read+write) miss cycles 3377system.l2c.demand_miss_latency::cpu1.inst 6046329000 # number of demand (read+write) miss cycles 3378system.l2c.demand_miss_latency::cpu1.data 19142837998 # number of demand (read+write) miss cycles 3379system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 36908535986 # number of demand (read+write) miss cycles 3380system.l2c.demand_miss_latency::total 154061098850 # number of demand (read+write) miss cycles 3381system.l2c.overall_miss_latency::cpu0.dtb.walker 356299000 # number of overall miss cycles 3382system.l2c.overall_miss_latency::cpu0.itb.walker 337167500 # number of overall miss cycles 3383system.l2c.overall_miss_latency::cpu0.inst 6654556500 # number of overall miss cycles 3384system.l2c.overall_miss_latency::cpu0.data 31018591991 # number of overall miss cycles 3385system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 53218202875 # number of overall miss cycles 3386system.l2c.overall_miss_latency::cpu1.dtb.walker 218154000 # number of overall miss cycles 3387system.l2c.overall_miss_latency::cpu1.itb.walker 160424000 # number of overall miss cycles 3388system.l2c.overall_miss_latency::cpu1.inst 6046329000 # number of overall miss cycles 3389system.l2c.overall_miss_latency::cpu1.data 19142837998 # number of overall miss cycles 3390system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 36908535986 # number of overall miss cycles 3391system.l2c.overall_miss_latency::total 154061098850 # number of overall miss cycles 3392system.l2c.WritebackDirty_accesses::writebacks 2973062 # number of WritebackDirty accesses(hits+misses) 3393system.l2c.WritebackDirty_accesses::total 2973062 # number of WritebackDirty accesses(hits+misses) 3394system.l2c.UpgradeReq_accesses::cpu0.data 238581 # number of UpgradeReq accesses(hits+misses) 3395system.l2c.UpgradeReq_accesses::cpu1.data 204958 # number of UpgradeReq accesses(hits+misses) 3396system.l2c.UpgradeReq_accesses::total 443539 # number of UpgradeReq accesses(hits+misses) 3397system.l2c.SCUpgradeReq_accesses::cpu0.data 56423 # number of SCUpgradeReq accesses(hits+misses) 3398system.l2c.SCUpgradeReq_accesses::cpu1.data 50465 # number of SCUpgradeReq accesses(hits+misses) 3399system.l2c.SCUpgradeReq_accesses::total 106888 # number of SCUpgradeReq accesses(hits+misses) 3400system.l2c.ReadExReq_accesses::cpu0.data 147613 # number of ReadExReq accesses(hits+misses) 3401system.l2c.ReadExReq_accesses::cpu1.data 104680 # number of ReadExReq accesses(hits+misses) 3402system.l2c.ReadExReq_accesses::total 252293 # number of ReadExReq accesses(hits+misses) 3403system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 15805 # number of ReadSharedReq accesses(hits+misses) 3404system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 7931 # number of ReadSharedReq accesses(hits+misses) 3405system.l2c.ReadSharedReq_accesses::cpu0.inst 593369 # number of ReadSharedReq accesses(hits+misses) 3406system.l2c.ReadSharedReq_accesses::cpu0.data 827704 # number of ReadSharedReq accesses(hits+misses) 3407system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 633810 # number of ReadSharedReq accesses(hits+misses) 3408system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 14565 # number of ReadSharedReq accesses(hits+misses) 3409system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 6838 # number of ReadSharedReq accesses(hits+misses) 3410system.l2c.ReadSharedReq_accesses::cpu1.inst 559907 # number of ReadSharedReq accesses(hits+misses) 3411system.l2c.ReadSharedReq_accesses::cpu1.data 706102 # number of ReadSharedReq accesses(hits+misses) 3412system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 539565 # number of ReadSharedReq accesses(hits+misses) 3413system.l2c.ReadSharedReq_accesses::total 3905596 # number of ReadSharedReq accesses(hits+misses) 3414system.l2c.InvalidateReq_accesses::cpu0.data 611999 # number of InvalidateReq accesses(hits+misses) 3415system.l2c.InvalidateReq_accesses::cpu1.data 245089 # number of InvalidateReq accesses(hits+misses) 3416system.l2c.InvalidateReq_accesses::total 857088 # number of InvalidateReq accesses(hits+misses) 3417system.l2c.demand_accesses::cpu0.dtb.walker 15805 # number of demand (read+write) accesses 3418system.l2c.demand_accesses::cpu0.itb.walker 7931 # number of demand (read+write) accesses 3419system.l2c.demand_accesses::cpu0.inst 593369 # number of demand (read+write) accesses 3420system.l2c.demand_accesses::cpu0.data 975317 # number of demand (read+write) accesses 3421system.l2c.demand_accesses::cpu0.l2cache.prefetcher 633810 # number of demand (read+write) accesses 3422system.l2c.demand_accesses::cpu1.dtb.walker 14565 # number of demand (read+write) accesses 3423system.l2c.demand_accesses::cpu1.itb.walker 6838 # number of demand (read+write) accesses 3424system.l2c.demand_accesses::cpu1.inst 559907 # number of demand (read+write) accesses 3425system.l2c.demand_accesses::cpu1.data 810782 # number of demand (read+write) accesses 3426system.l2c.demand_accesses::cpu1.l2cache.prefetcher 539565 # number of demand (read+write) accesses 3427system.l2c.demand_accesses::total 4157889 # number of demand (read+write) accesses 3428system.l2c.overall_accesses::cpu0.dtb.walker 15805 # number of overall (read+write) accesses 3429system.l2c.overall_accesses::cpu0.itb.walker 7931 # number of overall (read+write) accesses 3430system.l2c.overall_accesses::cpu0.inst 593369 # number of overall (read+write) accesses 3431system.l2c.overall_accesses::cpu0.data 975317 # number of overall (read+write) accesses 3432system.l2c.overall_accesses::cpu0.l2cache.prefetcher 633810 # number of overall (read+write) accesses 3433system.l2c.overall_accesses::cpu1.dtb.walker 14565 # number of overall (read+write) accesses 3434system.l2c.overall_accesses::cpu1.itb.walker 6838 # number of overall (read+write) accesses 3435system.l2c.overall_accesses::cpu1.inst 559907 # number of overall (read+write) accesses 3436system.l2c.overall_accesses::cpu1.data 810782 # number of overall (read+write) accesses 3437system.l2c.overall_accesses::cpu1.l2cache.prefetcher 539565 # number of overall (read+write) accesses 3438system.l2c.overall_accesses::total 4157889 # number of overall (read+write) accesses 3439system.l2c.UpgradeReq_miss_rate::cpu0.data 0.107586 # miss rate for UpgradeReq accesses 3440system.l2c.UpgradeReq_miss_rate::cpu1.data 0.125299 # miss rate for UpgradeReq accesses 3441system.l2c.UpgradeReq_miss_rate::total 0.115771 # miss rate for UpgradeReq accesses 3442system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.011449 # miss rate for SCUpgradeReq accesses 3443system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.016031 # miss rate for SCUpgradeReq accesses 3444system.l2c.SCUpgradeReq_miss_rate::total 0.013612 # miss rate for SCUpgradeReq accesses 3445system.l2c.ReadExReq_miss_rate::cpu0.data 0.638758 # miss rate for ReadExReq accesses 3446system.l2c.ReadExReq_miss_rate::cpu1.data 0.459123 # miss rate for ReadExReq accesses 3447system.l2c.ReadExReq_miss_rate::total 0.564225 # miss rate for ReadExReq accesses 3448system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.223410 # miss rate for ReadSharedReq accesses 3449system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.415837 # miss rate for ReadSharedReq accesses 3450system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.102088 # miss rate for ReadSharedReq accesses 3451system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.224226 # miss rate for ReadSharedReq accesses 3452system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.549761 # miss rate for ReadSharedReq accesses 3453system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.141641 # miss rate for ReadSharedReq accesses 3454system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.226089 # miss rate for ReadSharedReq accesses 3455system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.096039 # miss rate for ReadSharedReq accesses 3456system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.166091 # miss rate for ReadSharedReq accesses 3457system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.446489 # miss rate for ReadSharedReq accesses 3458system.l2c.ReadSharedReq_miss_rate::total 0.260398 # miss rate for ReadSharedReq accesses 3459system.l2c.InvalidateReq_miss_rate::cpu0.data 0.781516 # miss rate for InvalidateReq accesses 3460system.l2c.InvalidateReq_miss_rate::cpu1.data 0.457585 # miss rate for InvalidateReq accesses 3461system.l2c.InvalidateReq_miss_rate::total 0.688886 # miss rate for InvalidateReq accesses 3462system.l2c.demand_miss_rate::cpu0.dtb.walker 0.223410 # miss rate for demand accesses 3463system.l2c.demand_miss_rate::cpu0.itb.walker 0.415837 # miss rate for demand accesses 3464system.l2c.demand_miss_rate::cpu0.inst 0.102088 # miss rate for demand accesses 3465system.l2c.demand_miss_rate::cpu0.data 0.286965 # miss rate for demand accesses 3466system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.549761 # miss rate for demand accesses 3467system.l2c.demand_miss_rate::cpu1.dtb.walker 0.141641 # miss rate for demand accesses 3468system.l2c.demand_miss_rate::cpu1.itb.walker 0.226089 # miss rate for demand accesses 3469system.l2c.demand_miss_rate::cpu1.inst 0.096039 # miss rate for demand accesses 3470system.l2c.demand_miss_rate::cpu1.data 0.203924 # miss rate for demand accesses 3471system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.446489 # miss rate for demand accesses 3472system.l2c.demand_miss_rate::total 0.278834 # miss rate for demand accesses 3473system.l2c.overall_miss_rate::cpu0.dtb.walker 0.223410 # miss rate for overall accesses 3474system.l2c.overall_miss_rate::cpu0.itb.walker 0.415837 # miss rate for overall accesses 3475system.l2c.overall_miss_rate::cpu0.inst 0.102088 # miss rate for overall accesses 3476system.l2c.overall_miss_rate::cpu0.data 0.286965 # miss rate for overall accesses 3477system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.549761 # miss rate for overall accesses 3478system.l2c.overall_miss_rate::cpu1.dtb.walker 0.141641 # miss rate for overall accesses 3479system.l2c.overall_miss_rate::cpu1.itb.walker 0.226089 # miss rate for overall accesses 3480system.l2c.overall_miss_rate::cpu1.inst 0.096039 # miss rate for overall accesses 3481system.l2c.overall_miss_rate::cpu1.data 0.203924 # miss rate for overall accesses 3482system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.446489 # miss rate for overall accesses 3483system.l2c.overall_miss_rate::total 0.278834 # miss rate for overall accesses 3484system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 6709.599501 # average UpgradeReq miss latency 3485system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6044.371325 # average UpgradeReq miss latency 3486system.l2c.UpgradeReq_avg_miss_latency::total 6376.901205 # average UpgradeReq miss latency 3487system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 14202.786378 # average SCUpgradeReq miss latency 3488system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 7173.053152 # average SCUpgradeReq miss latency 3489system.l2c.SCUpgradeReq_avg_miss_latency::total 10294.158076 # average SCUpgradeReq miss latency 3490system.l2c.ReadExReq_avg_miss_latency::cpu0.data 108537.772073 # average ReadExReq miss latency 3491system.l2c.ReadExReq_avg_miss_latency::cpu1.data 109457.990866 # average ReadExReq miss latency 3492system.l2c.ReadExReq_avg_miss_latency::total 108848.461468 # average ReadExReq miss latency 3493system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 100905.975644 # average ReadSharedReq miss latency 3494system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 102233.929654 # average ReadSharedReq miss latency 3495system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 109854.670166 # average ReadSharedReq miss latency 3496system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 111990.613870 # average ReadSharedReq miss latency 3497system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632 # average ReadSharedReq miss latency 3498system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 105746.000969 # average ReadSharedReq miss latency 3499system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 103767.141009 # average ReadSharedReq miss latency 3500system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 112441.727261 # average ReadSharedReq miss latency 3501system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 118370.844232 # average ReadSharedReq miss latency 3502system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585 # average ReadSharedReq miss latency 3503system.l2c.ReadSharedReq_avg_miss_latency::total 136248.792157 # average ReadSharedReq miss latency 3504system.l2c.InvalidateReq_avg_miss_latency::cpu0.data 66.048210 # average InvalidateReq miss latency 3505system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 293.966063 # average InvalidateReq miss latency 3506system.l2c.InvalidateReq_avg_miss_latency::total 109.339539 # average InvalidateReq miss latency 3507system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 100905.975644 # average overall miss latency 3508system.l2c.demand_avg_miss_latency::cpu0.itb.walker 102233.929654 # average overall miss latency 3509system.l2c.demand_avg_miss_latency::cpu0.inst 109854.670166 # average overall miss latency 3510system.l2c.demand_avg_miss_latency::cpu0.data 110827.391511 # average overall miss latency 3511system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632 # average overall miss latency 3512system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 105746.000969 # average overall miss latency 3513system.l2c.demand_avg_miss_latency::cpu1.itb.walker 103767.141009 # average overall miss latency 3514system.l2c.demand_avg_miss_latency::cpu1.inst 112441.727261 # average overall miss latency 3515system.l2c.demand_avg_miss_latency::cpu1.data 115780.026358 # average overall miss latency 3516system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585 # average overall miss latency 3517system.l2c.demand_avg_miss_latency::total 132884.493139 # average overall miss latency 3518system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 100905.975644 # average overall miss latency 3519system.l2c.overall_avg_miss_latency::cpu0.itb.walker 102233.929654 # average overall miss latency 3520system.l2c.overall_avg_miss_latency::cpu0.inst 109854.670166 # average overall miss latency 3521system.l2c.overall_avg_miss_latency::cpu0.data 110827.391511 # average overall miss latency 3522system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 152731.006632 # average overall miss latency 3523system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 105746.000969 # average overall miss latency 3524system.l2c.overall_avg_miss_latency::cpu1.itb.walker 103767.141009 # average overall miss latency 3525system.l2c.overall_avg_miss_latency::cpu1.inst 112441.727261 # average overall miss latency 3526system.l2c.overall_avg_miss_latency::cpu1.data 115780.026358 # average overall miss latency 3527system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 153204.665585 # average overall miss latency 3528system.l2c.overall_avg_miss_latency::total 132884.493139 # average overall miss latency 3529system.l2c.blocked_cycles::no_mshrs 11042 # number of cycles access was blocked 3530system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 3531system.l2c.blocked::no_mshrs 109 # number of cycles access was blocked 3532system.l2c.blocked::no_targets 0 # number of cycles access was blocked 3533system.l2c.avg_blocked_cycles::no_mshrs 101.302752 # average number of cycles each access was blocked 3534system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 3535system.l2c.writebacks::writebacks 1306567 # number of writebacks 3536system.l2c.writebacks::total 1306567 # number of writebacks 3537system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 94 # number of ReadSharedReq MSHR hits 3538system.l2c.ReadSharedReq_mshr_hits::cpu0.data 23 # number of ReadSharedReq MSHR hits 3539system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 174 # number of ReadSharedReq MSHR hits 3540system.l2c.ReadSharedReq_mshr_hits::cpu1.data 24 # number of ReadSharedReq MSHR hits 3541system.l2c.ReadSharedReq_mshr_hits::total 315 # number of ReadSharedReq MSHR hits 3542system.l2c.demand_mshr_hits::cpu0.inst 94 # number of demand (read+write) MSHR hits 3543system.l2c.demand_mshr_hits::cpu0.data 23 # number of demand (read+write) MSHR hits 3544system.l2c.demand_mshr_hits::cpu1.inst 174 # number of demand (read+write) MSHR hits 3545system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits 3546system.l2c.demand_mshr_hits::total 315 # number of demand (read+write) MSHR hits 3547system.l2c.overall_mshr_hits::cpu0.inst 94 # number of overall MSHR hits 3548system.l2c.overall_mshr_hits::cpu0.data 23 # number of overall MSHR hits 3549system.l2c.overall_mshr_hits::cpu1.inst 174 # number of overall MSHR hits 3550system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits 3551system.l2c.overall_mshr_hits::total 315 # number of overall MSHR hits 3552system.l2c.CleanEvict_mshr_misses::writebacks 73117 # number of CleanEvict MSHR misses 3553system.l2c.CleanEvict_mshr_misses::total 73117 # number of CleanEvict MSHR misses 3554system.l2c.UpgradeReq_mshr_misses::cpu0.data 25668 # number of UpgradeReq MSHR misses 3555system.l2c.UpgradeReq_mshr_misses::cpu1.data 25681 # number of UpgradeReq MSHR misses 3556system.l2c.UpgradeReq_mshr_misses::total 51349 # number of UpgradeReq MSHR misses 3557system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 646 # number of SCUpgradeReq MSHR misses 3558system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 809 # number of SCUpgradeReq MSHR misses 3559system.l2c.SCUpgradeReq_mshr_misses::total 1455 # number of SCUpgradeReq MSHR misses 3560system.l2c.ReadExReq_mshr_misses::cpu0.data 94289 # number of ReadExReq MSHR misses 3561system.l2c.ReadExReq_mshr_misses::cpu1.data 48061 # number of ReadExReq MSHR misses 3562system.l2c.ReadExReq_mshr_misses::total 142350 # number of ReadExReq MSHR misses 3563system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 3531 # number of ReadSharedReq MSHR misses 3564system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 3298 # number of ReadSharedReq MSHR misses 3565system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 60482 # number of ReadSharedReq MSHR misses 3566system.l2c.ReadSharedReq_mshr_misses::cpu0.data 185570 # number of ReadSharedReq MSHR misses 3567system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 348444 # number of ReadSharedReq MSHR misses 3568system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 2063 # number of ReadSharedReq MSHR misses 3569system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 1546 # number of ReadSharedReq MSHR misses 3570system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 53599 # number of ReadSharedReq MSHR misses 3571system.l2c.ReadSharedReq_mshr_misses::cpu1.data 117253 # number of ReadSharedReq MSHR misses 3572system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 240910 # number of ReadSharedReq MSHR misses 3573system.l2c.ReadSharedReq_mshr_misses::total 1016696 # number of ReadSharedReq MSHR misses 3574system.l2c.InvalidateReq_mshr_misses::cpu0.data 478287 # number of InvalidateReq MSHR misses 3575system.l2c.InvalidateReq_mshr_misses::cpu1.data 112149 # number of InvalidateReq MSHR misses 3576system.l2c.InvalidateReq_mshr_misses::total 590436 # number of InvalidateReq MSHR misses 3577system.l2c.demand_mshr_misses::cpu0.dtb.walker 3531 # number of demand (read+write) MSHR misses 3578system.l2c.demand_mshr_misses::cpu0.itb.walker 3298 # number of demand (read+write) MSHR misses 3579system.l2c.demand_mshr_misses::cpu0.inst 60482 # number of demand (read+write) MSHR misses 3580system.l2c.demand_mshr_misses::cpu0.data 279859 # number of demand (read+write) MSHR misses 3581system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 348444 # number of demand (read+write) MSHR misses 3582system.l2c.demand_mshr_misses::cpu1.dtb.walker 2063 # number of demand (read+write) MSHR misses 3583system.l2c.demand_mshr_misses::cpu1.itb.walker 1546 # number of demand (read+write) MSHR misses 3584system.l2c.demand_mshr_misses::cpu1.inst 53599 # number of demand (read+write) MSHR misses 3585system.l2c.demand_mshr_misses::cpu1.data 165314 # number of demand (read+write) MSHR misses 3586system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 240910 # number of demand (read+write) MSHR misses 3587system.l2c.demand_mshr_misses::total 1159046 # number of demand (read+write) MSHR misses 3588system.l2c.overall_mshr_misses::cpu0.dtb.walker 3531 # number of overall MSHR misses 3589system.l2c.overall_mshr_misses::cpu0.itb.walker 3298 # number of overall MSHR misses 3590system.l2c.overall_mshr_misses::cpu0.inst 60482 # number of overall MSHR misses 3591system.l2c.overall_mshr_misses::cpu0.data 279859 # number of overall MSHR misses 3592system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 348444 # number of overall MSHR misses 3593system.l2c.overall_mshr_misses::cpu1.dtb.walker 2063 # number of overall MSHR misses 3594system.l2c.overall_mshr_misses::cpu1.itb.walker 1546 # number of overall MSHR misses 3595system.l2c.overall_mshr_misses::cpu1.inst 53599 # number of overall MSHR misses 3596system.l2c.overall_mshr_misses::cpu1.data 165314 # number of overall MSHR misses 3597system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 240910 # number of overall MSHR misses 3598system.l2c.overall_mshr_misses::total 1159046 # number of overall MSHR misses 3599system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 21293 # number of ReadReq MSHR uncacheable 3600system.l2c.ReadReq_mshr_uncacheable::cpu0.data 16980 # number of ReadReq MSHR uncacheable 3601system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 67 # number of ReadReq MSHR uncacheable 3602system.l2c.ReadReq_mshr_uncacheable::cpu1.data 21289 # number of ReadReq MSHR uncacheable 3603system.l2c.ReadReq_mshr_uncacheable::total 59629 # number of ReadReq MSHR uncacheable 3604system.l2c.WriteReq_mshr_uncacheable::cpu0.data 18801 # number of WriteReq MSHR uncacheable 3605system.l2c.WriteReq_mshr_uncacheable::cpu1.data 19410 # number of WriteReq MSHR uncacheable 3606system.l2c.WriteReq_mshr_uncacheable::total 38211 # number of WriteReq MSHR uncacheable 3607system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 21293 # number of overall MSHR uncacheable misses 3608system.l2c.overall_mshr_uncacheable_misses::cpu0.data 35781 # number of overall MSHR uncacheable misses 3609system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 67 # number of overall MSHR uncacheable misses 3610system.l2c.overall_mshr_uncacheable_misses::cpu1.data 40699 # number of overall MSHR uncacheable misses 3611system.l2c.overall_mshr_uncacheable_misses::total 97840 # number of overall MSHR uncacheable misses 3612system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 520949500 # number of UpgradeReq MSHR miss cycles 3613system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 534002500 # number of UpgradeReq MSHR miss cycles 3614system.l2c.UpgradeReq_mshr_miss_latency::total 1054952000 # number of UpgradeReq MSHR miss cycles 3615system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 15625500 # number of SCUpgradeReq MSHR miss cycles 3616system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 19999000 # number of SCUpgradeReq MSHR miss cycles 3617system.l2c.SCUpgradeReq_mshr_miss_latency::total 35624500 # number of SCUpgradeReq MSHR miss cycles 3618system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 9290880791 # number of ReadExReq MSHR miss cycles 3619system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 4779832460 # number of ReadExReq MSHR miss cycles 3620system.l2c.ReadExReq_mshr_miss_latency::total 14070713251 # number of ReadExReq MSHR miss cycles 3621system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 320987004 # number of ReadSharedReq MSHR miss cycles 3622system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 304187500 # number of ReadSharedReq MSHR miss cycles 3623system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 6041672064 # number of ReadSharedReq MSHR miss cycles 3624system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 18926430190 # number of ReadSharedReq MSHR miss cycles 3625system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 49733607723 # number of ReadSharedReq MSHR miss cycles 3626system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 197523002 # number of ReadSharedReq MSHR miss cycles 3627system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 144964000 # number of ReadSharedReq MSHR miss cycles 3628system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 5494647043 # number of ReadSharedReq MSHR miss cycles 3629system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 12706523221 # number of ReadSharedReq MSHR miss cycles 3630system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 34499199531 # number of ReadSharedReq MSHR miss cycles 3631system.l2c.ReadSharedReq_mshr_miss_latency::total 128369741278 # number of ReadSharedReq MSHR miss cycles 3632system.l2c.InvalidateReq_mshr_miss_latency::cpu0.data 11811554063 # number of InvalidateReq MSHR miss cycles 3633system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 2326727500 # number of InvalidateReq MSHR miss cycles 3634system.l2c.InvalidateReq_mshr_miss_latency::total 14138281563 # number of InvalidateReq MSHR miss cycles 3635system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 320987004 # number of demand (read+write) MSHR miss cycles 3636system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 304187500 # number of demand (read+write) MSHR miss cycles 3637system.l2c.demand_mshr_miss_latency::cpu0.inst 6041672064 # number of demand (read+write) MSHR miss cycles 3638system.l2c.demand_mshr_miss_latency::cpu0.data 28217310981 # number of demand (read+write) MSHR miss cycles 3639system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 49733607723 # number of demand (read+write) MSHR miss cycles 3640system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 197523002 # number of demand (read+write) MSHR miss cycles 3641system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 144964000 # number of demand (read+write) MSHR miss cycles 3642system.l2c.demand_mshr_miss_latency::cpu1.inst 5494647043 # number of demand (read+write) MSHR miss cycles 3643system.l2c.demand_mshr_miss_latency::cpu1.data 17486355681 # number of demand (read+write) MSHR miss cycles 3644system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 34499199531 # number of demand (read+write) MSHR miss cycles 3645system.l2c.demand_mshr_miss_latency::total 142440454529 # number of demand (read+write) MSHR miss cycles 3646system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 320987004 # number of overall MSHR miss cycles 3647system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 304187500 # number of overall MSHR miss cycles 3648system.l2c.overall_mshr_miss_latency::cpu0.inst 6041672064 # number of overall MSHR miss cycles 3649system.l2c.overall_mshr_miss_latency::cpu0.data 28217310981 # number of overall MSHR miss cycles 3650system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 49733607723 # number of overall MSHR miss cycles 3651system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 197523002 # number of overall MSHR miss cycles 3652system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 144964000 # number of overall MSHR miss cycles 3653system.l2c.overall_mshr_miss_latency::cpu1.inst 5494647043 # number of overall MSHR miss cycles 3654system.l2c.overall_mshr_miss_latency::cpu1.data 17486355681 # number of overall MSHR miss cycles 3655system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 34499199531 # number of overall MSHR miss cycles 3656system.l2c.overall_mshr_miss_latency::total 142440454529 # number of overall MSHR miss cycles 3657system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of ReadReq MSHR uncacheable cycles 3658system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2691376000 # number of ReadReq MSHR uncacheable cycles 3659system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5368000 # number of ReadReq MSHR uncacheable cycles 3660system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 3243740000 # number of ReadReq MSHR uncacheable cycles 3661system.l2c.ReadReq_mshr_uncacheable_latency::total 7424669500 # number of ReadReq MSHR uncacheable cycles 3662system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 1484185500 # number of overall MSHR uncacheable cycles 3663system.l2c.overall_mshr_uncacheable_latency::cpu0.data 2691376000 # number of overall MSHR uncacheable cycles 3664system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5368000 # number of overall MSHR uncacheable cycles 3665system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3243740000 # number of overall MSHR uncacheable cycles 3666system.l2c.overall_mshr_uncacheable_latency::total 7424669500 # number of overall MSHR uncacheable cycles 3667system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 3668system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 3669system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.107586 # mshr miss rate for UpgradeReq accesses 3670system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.125299 # mshr miss rate for UpgradeReq accesses 3671system.l2c.UpgradeReq_mshr_miss_rate::total 0.115771 # mshr miss rate for UpgradeReq accesses 3672system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.011449 # mshr miss rate for SCUpgradeReq accesses 3673system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.016031 # mshr miss rate for SCUpgradeReq accesses 3674system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.013612 # mshr miss rate for SCUpgradeReq accesses 3675system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.638758 # mshr miss rate for ReadExReq accesses 3676system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.459123 # mshr miss rate for ReadExReq accesses 3677system.l2c.ReadExReq_mshr_miss_rate::total 0.564225 # mshr miss rate for ReadExReq accesses 3678system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for ReadSharedReq accesses 3679system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for ReadSharedReq accesses 3680system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for ReadSharedReq accesses 3681system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.224199 # mshr miss rate for ReadSharedReq accesses 3682system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for ReadSharedReq accesses 3683system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for ReadSharedReq accesses 3684system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for ReadSharedReq accesses 3685system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for ReadSharedReq accesses 3686system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.166057 # mshr miss rate for ReadSharedReq accesses 3687system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for ReadSharedReq accesses 3688system.l2c.ReadSharedReq_mshr_miss_rate::total 0.260318 # mshr miss rate for ReadSharedReq accesses 3689system.l2c.InvalidateReq_mshr_miss_rate::cpu0.data 0.781516 # mshr miss rate for InvalidateReq accesses 3690system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.457585 # mshr miss rate for InvalidateReq accesses 3691system.l2c.InvalidateReq_mshr_miss_rate::total 0.688886 # mshr miss rate for InvalidateReq accesses 3692system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for demand accesses 3693system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for demand accesses 3694system.l2c.demand_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for demand accesses 3695system.l2c.demand_mshr_miss_rate::cpu0.data 0.286942 # mshr miss rate for demand accesses 3696system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for demand accesses 3697system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for demand accesses 3698system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for demand accesses 3699system.l2c.demand_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for demand accesses 3700system.l2c.demand_mshr_miss_rate::cpu1.data 0.203895 # mshr miss rate for demand accesses 3701system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for demand accesses 3702system.l2c.demand_mshr_miss_rate::total 0.278758 # mshr miss rate for demand accesses 3703system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.223410 # mshr miss rate for overall accesses 3704system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.415837 # mshr miss rate for overall accesses 3705system.l2c.overall_mshr_miss_rate::cpu0.inst 0.101930 # mshr miss rate for overall accesses 3706system.l2c.overall_mshr_miss_rate::cpu0.data 0.286942 # mshr miss rate for overall accesses 3707system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.549761 # mshr miss rate for overall accesses 3708system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.141641 # mshr miss rate for overall accesses 3709system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.226089 # mshr miss rate for overall accesses 3710system.l2c.overall_mshr_miss_rate::cpu1.inst 0.095728 # mshr miss rate for overall accesses 3711system.l2c.overall_mshr_miss_rate::cpu1.data 0.203895 # mshr miss rate for overall accesses 3712system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.446489 # mshr miss rate for overall accesses 3713system.l2c.overall_mshr_miss_rate::total 0.278758 # mshr miss rate for overall accesses 3714system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20295.679445 # average UpgradeReq mshr miss latency 3715system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20793.680153 # average UpgradeReq mshr miss latency 3716system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20544.742838 # average UpgradeReq mshr miss latency 3717system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 24188.080495 # average SCUpgradeReq mshr miss latency 3718system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24720.642769 # average SCUpgradeReq mshr miss latency 3719system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24484.192440 # average SCUpgradeReq mshr miss latency 3720system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 98536.210915 # average ReadExReq mshr miss latency 3721system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 99453.454152 # average ReadExReq mshr miss latency 3722system.l2c.ReadExReq_avg_mshr_miss_latency::total 98845.895687 # average ReadExReq mshr miss latency 3723system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average ReadSharedReq mshr miss latency 3724system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average ReadSharedReq mshr miss latency 3725system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average ReadSharedReq mshr miss latency 3726system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 101990.786172 # average ReadSharedReq mshr miss latency 3727system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average ReadSharedReq mshr miss latency 3728system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average ReadSharedReq mshr miss latency 3729system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average ReadSharedReq mshr miss latency 3730system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average ReadSharedReq mshr miss latency 3731system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 108368.427426 # average ReadSharedReq mshr miss latency 3732system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average ReadSharedReq mshr miss latency 3733system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 126261.676330 # average ReadSharedReq mshr miss latency 3734system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu0.data 24695.536494 # average InvalidateReq mshr miss latency 3735system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 20746.752089 # average InvalidateReq mshr miss latency 3736system.l2c.InvalidateReq_avg_mshr_miss_latency::total 23945.493776 # average InvalidateReq mshr miss latency 3737system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average overall mshr miss latency 3738system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average overall mshr miss latency 3739system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average overall mshr miss latency 3740system.l2c.demand_avg_mshr_miss_latency::cpu0.data 100826.884185 # average overall mshr miss latency 3741system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average overall mshr miss latency 3742system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average overall mshr miss latency 3743system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average overall mshr miss latency 3744system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average overall mshr miss latency 3745system.l2c.demand_avg_mshr_miss_latency::cpu1.data 105776.617110 # average overall mshr miss latency 3746system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average overall mshr miss latency 3747system.l2c.demand_avg_mshr_miss_latency::total 122894.565469 # average overall mshr miss latency 3748system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 90905.410365 # average overall mshr miss latency 3749system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 92233.929654 # average overall mshr miss latency 3750system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 99892.068119 # average overall mshr miss latency 3751system.l2c.overall_avg_mshr_miss_latency::cpu0.data 100826.884185 # average overall mshr miss latency 3752system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 142730.561361 # average overall mshr miss latency 3753system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 95745.517208 # average overall mshr miss latency 3754system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 93767.141009 # average overall mshr miss latency 3755system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 102513.984272 # average overall mshr miss latency 3756system.l2c.overall_avg_mshr_miss_latency::cpu1.data 105776.617110 # average overall mshr miss latency 3757system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 143203.684077 # average overall mshr miss latency 3758system.l2c.overall_avg_mshr_miss_latency::total 122894.565469 # average overall mshr miss latency 3759system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average ReadReq mshr uncacheable latency 3760system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 158502.709069 # average ReadReq mshr uncacheable latency 3761system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average ReadReq mshr uncacheable latency 3762system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 152366.950068 # average ReadReq mshr uncacheable latency 3763system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 124514.405742 # average ReadReq mshr uncacheable latency 3764system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69702.977504 # average overall mshr uncacheable latency 3765system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 75218.020737 # average overall mshr uncacheable latency 3766system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 80119.402985 # average overall mshr uncacheable latency 3767system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 79700.729748 # average overall mshr uncacheable latency 3768system.l2c.overall_avg_mshr_uncacheable_latency::total 75885.828904 # average overall mshr uncacheable latency 3769system.membus.snoop_filter.tot_requests 4262418 # Total number of requests made to the snoop filter. 3770system.membus.snoop_filter.hit_single_requests 2509154 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3771system.membus.snoop_filter.hit_multi_requests 3063 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3772system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 3773system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3774system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3775system.membus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3776system.membus.trans_dist::ReadReq 59629 # Transaction distribution 3777system.membus.trans_dist::ReadResp 1085265 # Transaction distribution 3778system.membus.trans_dist::WriteReq 38211 # Transaction distribution 3779system.membus.trans_dist::WriteResp 38211 # Transaction distribution 3780system.membus.trans_dist::WritebackDirty 1413261 # Transaction distribution 3781system.membus.trans_dist::CleanEvict 284296 # Transaction distribution 3782system.membus.trans_dist::UpgradeReq 353595 # Transaction distribution 3783system.membus.trans_dist::SCUpgradeReq 284030 # Transaction distribution 3784system.membus.trans_dist::UpgradeResp 23 # Transaction distribution 3785system.membus.trans_dist::ReadExReq 155418 # Transaction distribution 3786system.membus.trans_dist::ReadExResp 141619 # Transaction distribution 3787system.membus.trans_dist::ReadSharedReq 1025636 # Transaction distribution 3788system.membus.trans_dist::InvalidateReq 695069 # Transaction distribution 3789system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122584 # Packet count per connected master and slave (bytes) 3790system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 76 # Packet count per connected master and slave (bytes) 3791system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25156 # Packet count per connected master and slave (bytes) 3792system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 5185454 # Packet count per connected master and slave (bytes) 3793system.membus.pkt_count_system.l2c.mem_side::total 5333270 # Packet count per connected master and slave (bytes) 3794system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 238137 # Packet count per connected master and slave (bytes) 3795system.membus.pkt_count_system.iocache.mem_side::total 238137 # Packet count per connected master and slave (bytes) 3796system.membus.pkt_count::total 5571407 # Packet count per connected master and slave (bytes) 3797system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155691 # Cumulative packet size per connected master and slave (bytes) 3798system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 556 # Cumulative packet size per connected master and slave (bytes) 3799system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50312 # Cumulative packet size per connected master and slave (bytes) 3800system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 158067712 # Cumulative packet size per connected master and slave (bytes) 3801system.membus.pkt_size_system.l2c.mem_side::total 158274271 # Cumulative packet size per connected master and slave (bytes) 3802system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7266112 # Cumulative packet size per connected master and slave (bytes) 3803system.membus.pkt_size_system.iocache.mem_side::total 7266112 # Cumulative packet size per connected master and slave (bytes) 3804system.membus.pkt_size::total 165540383 # Cumulative packet size per connected master and slave (bytes) 3805system.membus.snoops 598647 # Total snoops (count) 3806system.membus.snoopTraffic 181312 # Total snoop traffic (bytes) 3807system.membus.snoop_fanout::samples 2611590 # Request fanout histogram 3808system.membus.snoop_fanout::mean 0.013385 # Request fanout histogram 3809system.membus.snoop_fanout::stdev 0.114916 # Request fanout histogram 3810system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3811system.membus.snoop_fanout::0 2576634 98.66% 98.66% # Request fanout histogram 3812system.membus.snoop_fanout::1 34956 1.34% 100.00% # Request fanout histogram 3813system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 3814system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3815system.membus.snoop_fanout::min_value 0 # Request fanout histogram 3816system.membus.snoop_fanout::max_value 1 # Request fanout histogram 3817system.membus.snoop_fanout::total 2611590 # Request fanout histogram 3818system.membus.reqLayer0.occupancy 98274995 # Layer occupancy (ticks) 3819system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) 3820system.membus.reqLayer1.occupancy 52000 # Layer occupancy (ticks) 3821system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) 3822system.membus.reqLayer2.occupancy 20993495 # Layer occupancy (ticks) 3823system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) 3824system.membus.reqLayer5.occupancy 9731390131 # Layer occupancy (ticks) 3825system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) 3826system.membus.respLayer2.occupancy 6232103011 # Layer occupancy (ticks) 3827system.membus.respLayer2.utilization 0.0 # Layer utilization (%) 3828system.membus.respLayer3.occupancy 45620246 # Layer occupancy (ticks) 3829system.membus.respLayer3.utilization 0.0 # Layer utilization (%) 3830system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3831system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3832system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3833system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3834system.realview.gic.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3835system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3836system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3837system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks 3838system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks 3839system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks 3840system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks 3841system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks 3842system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks 3843system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3844system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3845system.realview.ethernet.txBytes 966 # Bytes Transmitted 3846system.realview.ethernet.txPackets 3 # Number of Packets Transmitted 3847system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device 3848system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device 3849system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device 3850system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 3851system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 3852system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 3853system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 3854system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s) 3855system.realview.ethernet.totPackets 3 # Total Packets 3856system.realview.ethernet.totBytes 966 # Total Bytes 3857system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s) 3858system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s) 3859system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s) 3860system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU 3861system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post 3862system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR 3863system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 3864system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post 3865system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 3866system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 3867system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post 3868system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR 3869system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 3870system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post 3871system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 3872system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 3873system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post 3874system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR 3875system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 3876system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post 3877system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 3878system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 3879system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post 3880system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 3881system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 3882system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post 3883system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 3884system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post 3885system.realview.ethernet.postedInterrupts 13 # number of posts to CPU 3886system.realview.ethernet.droppedPackets 0 # number of packets dropped 3887system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3888system.realview.ide.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3889system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3890system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3891system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3892system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3893system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3894system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks 3895system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks 3896system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks 3897system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks 3898system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3899system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3900system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3901system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3902system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3903system.realview.uart.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3904system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3905system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3906system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3907system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3908system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3909system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3910system.toL2Bus.snoop_filter.tot_requests 12430379 # Total number of requests made to the snoop filter. 3911system.toL2Bus.snoop_filter.hit_single_requests 6756092 # Number of requests hitting in the snoop filter with a single holder of the requested data. 3912system.toL2Bus.snoop_filter.hit_multi_requests 1976828 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 3913system.toL2Bus.snoop_filter.tot_snoops 231635 # Total number of snoops made to the snoop filter. 3914system.toL2Bus.snoop_filter.hit_single_snoops 213178 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 3915system.toL2Bus.snoop_filter.hit_multi_snoops 18457 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 3916system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 47384942719000 # Cumulative time (in ticks) in various power states 3917system.toL2Bus.trans_dist::ReadReq 59631 # Transaction distribution 3918system.toL2Bus.trans_dist::ReadResp 4752657 # Transaction distribution 3919system.toL2Bus.trans_dist::WriteReq 38211 # Transaction distribution 3920system.toL2Bus.trans_dist::WriteResp 38211 # Transaction distribution 3921system.toL2Bus.trans_dist::WritebackDirty 4279629 # Transaction distribution 3922system.toL2Bus.trans_dist::CleanEvict 2861492 # Transaction distribution 3923system.toL2Bus.trans_dist::UpgradeReq 742959 # Transaction distribution 3924system.toL2Bus.trans_dist::SCUpgradeReq 389463 # Transaction distribution 3925system.toL2Bus.trans_dist::UpgradeResp 1132422 # Transaction distribution 3926system.toL2Bus.trans_dist::SCUpgradeFailReq 133 # Transaction distribution 3927system.toL2Bus.trans_dist::UpgradeFailResp 133 # Transaction distribution 3928system.toL2Bus.trans_dist::ReadExReq 304770 # Transaction distribution 3929system.toL2Bus.trans_dist::ReadExResp 304770 # Transaction distribution 3930system.toL2Bus.trans_dist::ReadSharedReq 4693673 # Transaction distribution 3931system.toL2Bus.trans_dist::InvalidateReq 888953 # Transaction distribution 3932system.toL2Bus.trans_dist::InvalidateResp 857088 # Transaction distribution 3933system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10167135 # Packet count per connected master and slave (bytes) 3934system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8009990 # Packet count per connected master and slave (bytes) 3935system.toL2Bus.pkt_count::total 18177125 # Packet count per connected master and slave (bytes) 3936system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 258318649 # Cumulative packet size per connected master and slave (bytes) 3937system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 198738470 # Cumulative packet size per connected master and slave (bytes) 3938system.toL2Bus.pkt_size::total 457057119 # Cumulative packet size per connected master and slave (bytes) 3939system.toL2Bus.snoops 3168754 # Total snoops (count) 3940system.toL2Bus.snoopTraffic 137382864 # Total snoop traffic (bytes) 3941system.toL2Bus.snoop_fanout::samples 8831298 # Request fanout histogram 3942system.toL2Bus.snoop_fanout::mean 0.353414 # Request fanout histogram 3943system.toL2Bus.snoop_fanout::stdev 0.482382 # Request fanout histogram 3944system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 3945system.toL2Bus.snoop_fanout::0 5728650 64.87% 64.87% # Request fanout histogram 3946system.toL2Bus.snoop_fanout::1 3084191 34.92% 99.79% # Request fanout histogram 3947system.toL2Bus.snoop_fanout::2 18457 0.21% 100.00% # Request fanout histogram 3948system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 3949system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 3950system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 3951system.toL2Bus.snoop_fanout::total 8831298 # Request fanout histogram 3952system.toL2Bus.reqLayer0.occupancy 9716591105 # Layer occupancy (ticks) 3953system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 3954system.toL2Bus.snoopLayer0.occupancy 2596400 # Layer occupancy (ticks) 3955system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 3956system.toL2Bus.respLayer0.occupancy 4626263938 # Layer occupancy (ticks) 3957system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 3958system.toL2Bus.respLayer1.occupancy 3958447661 # Layer occupancy (ticks) 3959system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) 3960system.cpu0.kern.inst.arm 0 # number of arm instructions executed 3961system.cpu0.kern.inst.quiesce 5035 # number of quiesce instructions executed 3962system.cpu1.kern.inst.arm 0 # number of arm instructions executed 3963system.cpu1.kern.inst.quiesce 13834 # number of quiesce instructions executed 3964 3965---------- End Simulation Statistics ---------- 3966