tgen-dram-ctrl.py revision 9728
172SN/A# Copyright (c) 2012 ARM Limited
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3512SN/A#
3612SN/A# Authors: Andreas Hansson
3712SN/A
3812SN/Aimport m5
39125SN/Afrom m5.objects import *
40125SN/A
41125SN/A# both traffic generator and communication monitor are only available
42125SN/A# if we have protobuf support, so potentially skip this test
43125SN/Arequire_sim_object("TrafficGen")
44125SN/Arequire_sim_object("CommMonitor")
45125SN/A
46125SN/A# even if this is only a traffic generator, call it cpu to make sure
47125SN/A# the scripts are happy
48125SN/Acpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg")
49125SN/A
50125SN/A# system simulated
51125SN/Asystem = System(cpu = cpu, physmem = DDR3_1600_x64(),
52125SN/A                membus = NoncoherentBus(clock="1GHz", width = 16))
5312SN/A
5412SN/A# add a communication monitor
5512SN/Asystem.monitor = CommMonitor()
5612SN/A
5712SN/A# connect the traffic generator to the bus via a communication monitor
5812SN/Asystem.cpu.port = system.monitor.slave
5912SN/Asystem.monitor.master = system.membus.slave
6012SN/A
6112SN/A# connect the system port even if it is not used in this example
6212SN/Asystem.system_port = system.membus.slave
6312SN/A
6412SN/A# connect memory to the membus
6512SN/Asystem.physmem.port = system.membus.master
6612SN/A
6712SN/A# -----------------------
6812SN/A# run simulation
6912SN/A# -----------------------
7012SN/A
71root = Root(full_system = False, system = system)
72root.system.mem_mode = 'timing'
73