tgen-dram-ctrl.py revision 9728
172SN/A# Copyright (c) 2012 ARM Limited 21762SN/A# All rights reserved. 372SN/A# 472SN/A# The license below extends only to copyright in the software and shall 572SN/A# not be construed as granting a license to any other intellectual 672SN/A# property including but not limited to intellectual property relating 772SN/A# to a hardware implementation of the functionality of the software 872SN/A# licensed hereunder. You may use the software subject to the license 972SN/A# terms below provided that you ensure that this notice is replicated 1072SN/A# unmodified and in its entirety in all distributions of the software, 1172SN/A# modified or unmodified, in source code or in binary form. 1272SN/A# 1372SN/A# Redistribution and use in source and binary forms, with or without 1472SN/A# modification, are permitted provided that the following conditions are 1572SN/A# met: redistributions of source code must retain the above copyright 1672SN/A# notice, this list of conditions and the following disclaimer; 1772SN/A# redistributions in binary form must reproduce the above copyright 1872SN/A# notice, this list of conditions and the following disclaimer in the 1972SN/A# documentation and/or other materials provided with the distribution; 2072SN/A# neither the name of the copyright holders nor the names of its 2172SN/A# contributors may be used to endorse or promote products derived from 2272SN/A# this software without specific prior written permission. 2372SN/A# 2472SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2572SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2672SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 272665Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 282665Ssaidi@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292665Ssaidi@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3072SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3112SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3212SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3312SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3412SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3512SN/A# 3612SN/A# Authors: Andreas Hansson 3712SN/A 3812SN/Aimport m5 39125SN/Afrom m5.objects import * 40125SN/A 41125SN/A# both traffic generator and communication monitor are only available 42125SN/A# if we have protobuf support, so potentially skip this test 43125SN/Arequire_sim_object("TrafficGen") 44125SN/Arequire_sim_object("CommMonitor") 45125SN/A 46125SN/A# even if this is only a traffic generator, call it cpu to make sure 47125SN/A# the scripts are happy 48125SN/Acpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-dram.cfg") 49125SN/A 50125SN/A# system simulated 51125SN/Asystem = System(cpu = cpu, physmem = DDR3_1600_x64(), 52125SN/A membus = NoncoherentBus(clock="1GHz", width = 16)) 5312SN/A 5412SN/A# add a communication monitor 5512SN/Asystem.monitor = CommMonitor() 5612SN/A 5712SN/A# connect the traffic generator to the bus via a communication monitor 5812SN/Asystem.cpu.port = system.monitor.slave 5912SN/Asystem.monitor.master = system.membus.slave 6012SN/A 6112SN/A# connect the system port even if it is not used in this example 6212SN/Asystem.system_port = system.membus.slave 6312SN/A 6412SN/A# connect memory to the membus 6512SN/Asystem.physmem.port = system.membus.master 6612SN/A 6712SN/A# ----------------------- 6812SN/A# run simulation 6912SN/A# ----------------------- 7012SN/A 71root = Root(full_system = False, system = system) 72root.system.mem_mode = 'timing' 73