tgen-dram-ctrl.py revision 10720
19242SN/A# Copyright (c) 2012 ARM Limited
29242SN/A# All rights reserved.
39242SN/A#
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79242SN/A# to a hardware implementation of the functionality of the software
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129242SN/A#
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359242SN/A#
369242SN/A# Authors: Andreas Hansson
379242SN/A
389242SN/Aimport m5
399242SN/Afrom m5.objects import *
409242SN/A
419402SN/A# both traffic generator and communication monitor are only available
429402SN/A# if we have protobuf support, so potentially skip this test
439402SN/Arequire_sim_object("TrafficGen")
449402SN/Arequire_sim_object("CommMonitor")
459402SN/A
469242SN/A# even if this is only a traffic generator, call it cpu to make sure
479242SN/A# the scripts are happy
4810218Sandreas.hansson@arm.comcpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-dram-ctrl.cfg")
499242SN/A
509242SN/A# system simulated
519728SN/Asystem = System(cpu = cpu, physmem = DDR3_1600_x64(),
5210720Sandreas.hansson@arm.com                membus = IOXBar(width = 16),
539827SN/A                clk_domain = SrcClockDomain(clock = '1GHz',
549827SN/A                                            voltage_domain =
559827SN/A                                            VoltageDomain()))
569242SN/A
579242SN/A# add a communication monitor
589242SN/Asystem.monitor = CommMonitor()
599242SN/A
609242SN/A# connect the traffic generator to the bus via a communication monitor
619242SN/Asystem.cpu.port = system.monitor.slave
629242SN/Asystem.monitor.master = system.membus.slave
639242SN/A
649242SN/A# connect the system port even if it is not used in this example
659242SN/Asystem.system_port = system.membus.slave
669242SN/A
679242SN/A# connect memory to the membus
689242SN/Asystem.physmem.port = system.membus.master
699242SN/A
709242SN/A# -----------------------
719242SN/A# run simulation
729242SN/A# -----------------------
739242SN/A
749242SN/Aroot = Root(full_system = False, system = system)
759242SN/Aroot.system.mem_mode = 'timing'
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