simple-timing.py revision 2998
12968SN/Aimport m5 22968SN/Afrom m5.objects import * 310409Sandreas.hansson@arm.comm5.AddToPath('../configs/common') 410585Sandreas.hansson@arm.comfrom SEConfig import * 510585Sandreas.hansson@arm.com 68721SN/Aclass MyCache(BaseCache): 711245Sandreas.sandberg@arm.com assoc = 2 811245Sandreas.sandberg@arm.com block_size = 64 911245Sandreas.sandberg@arm.com latency = 1 1011245Sandreas.sandberg@arm.com mshrs = 10 1111245Sandreas.sandberg@arm.com tgts_per_mshr = 5 1210585Sandreas.hansson@arm.com 1310585Sandreas.hansson@arm.comcpu = TimingSimpleCPU() 1410036SAli.Saidi@ARM.comcpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), 1510036SAli.Saidi@ARM.com MyCache(size = '2MB')) 1611201Sandreas.hansson@arm.com 1711201Sandreas.hansson@arm.comsystem = System(cpu = cpu, 1811201Sandreas.hansson@arm.com physmem = PhysicalMemory(), 1911201Sandreas.hansson@arm.com membus = Bus()) 2010352Sandreas.hansson@arm.comsystem.physmem.port = system.membus.port 2111201Sandreas.hansson@arm.comcpu.connectMemPorts(system.membus) 2211201Sandreas.hansson@arm.com 2311201Sandreas.hansson@arm.comroot = Root(system = system) 2411201Sandreas.hansson@arm.com