RubyPort.cc revision 8923
16876Ssteve.reinhardt@amd.com/* 28922Swilliam.wang@arm.com * Copyright (c) 2012 ARM Limited 38922Swilliam.wang@arm.com * All rights reserved. 48922Swilliam.wang@arm.com * 58922Swilliam.wang@arm.com * The license below extends only to copyright in the software and shall 68922Swilliam.wang@arm.com * not be construed as granting a license to any other intellectual 78922Swilliam.wang@arm.com * property including but not limited to intellectual property relating 88922Swilliam.wang@arm.com * to a hardware implementation of the functionality of the software 98922Swilliam.wang@arm.com * licensed hereunder. You may use the software subject to the license 108922Swilliam.wang@arm.com * terms below provided that you ensure that this notice is replicated 118922Swilliam.wang@arm.com * unmodified and in its entirety in all distributions of the software, 128922Swilliam.wang@arm.com * modified or unmodified, in source code or in binary form. 138922Swilliam.wang@arm.com * 146876Ssteve.reinhardt@amd.com * Copyright (c) 2009 Advanced Micro Devices, Inc. 158717Snilay@cs.wisc.edu * Copyright (c) 2011 Mark D. Hill and David A. Wood 166876Ssteve.reinhardt@amd.com * All rights reserved. 176876Ssteve.reinhardt@amd.com * 186876Ssteve.reinhardt@amd.com * Redistribution and use in source and binary forms, with or without 196876Ssteve.reinhardt@amd.com * modification, are permitted provided that the following conditions are 206876Ssteve.reinhardt@amd.com * met: redistributions of source code must retain the above copyright 216876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer; 226876Ssteve.reinhardt@amd.com * redistributions in binary form must reproduce the above copyright 236876Ssteve.reinhardt@amd.com * notice, this list of conditions and the following disclaimer in the 246876Ssteve.reinhardt@amd.com * documentation and/or other materials provided with the distribution; 256876Ssteve.reinhardt@amd.com * neither the name of the copyright holders nor the names of its 266876Ssteve.reinhardt@amd.com * contributors may be used to endorse or promote products derived from 276876Ssteve.reinhardt@amd.com * this software without specific prior written permission. 286876Ssteve.reinhardt@amd.com * 296876Ssteve.reinhardt@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306876Ssteve.reinhardt@amd.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316876Ssteve.reinhardt@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326876Ssteve.reinhardt@amd.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336876Ssteve.reinhardt@amd.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346876Ssteve.reinhardt@amd.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356876Ssteve.reinhardt@amd.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366876Ssteve.reinhardt@amd.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376876Ssteve.reinhardt@amd.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386876Ssteve.reinhardt@amd.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396876Ssteve.reinhardt@amd.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406876Ssteve.reinhardt@amd.com */ 416876Ssteve.reinhardt@amd.com 427632SBrad.Beckmann@amd.com#include "cpu/testers/rubytest/RubyTester.hh" 438688Snilay@cs.wisc.edu#include "debug/Config.hh" 448232Snate@binkert.org#include "debug/Ruby.hh" 458436SBrad.Beckmann@amd.com#include "mem/protocol/AccessPermission.hh" 467039Snate@binkert.org#include "mem/ruby/slicc_interface/AbstractController.hh" 476285Snate@binkert.org#include "mem/ruby/system/RubyPort.hh" 488923Sandreas.hansson@arm.com#include "sim/system.hh" 496285Snate@binkert.org 506876Ssteve.reinhardt@amd.comRubyPort::RubyPort(const Params *p) 518922Swilliam.wang@arm.com : MemObject(p), m_version(p->version), m_controller(NULL), 528922Swilliam.wang@arm.com m_mandatory_q_ptr(NULL), 538922Swilliam.wang@arm.com pio_port(csprintf("%s-pio-port", name()), this), 548922Swilliam.wang@arm.com m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0), 558923Sandreas.hansson@arm.com drainEvent(NULL), ruby_system(p->ruby_system), system(p->system), 568922Swilliam.wang@arm.com waitingOnSequencer(false), access_phys_mem(p->access_phys_mem) 576876Ssteve.reinhardt@amd.com{ 586876Ssteve.reinhardt@amd.com assert(m_version != -1); 596876Ssteve.reinhardt@amd.com 608922Swilliam.wang@arm.com // create the slave ports based on the number of connected ports 618922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 628922Swilliam.wang@arm.com slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i), 638922Swilliam.wang@arm.com this, ruby_system, access_phys_mem)); 648922Swilliam.wang@arm.com } 657039Snate@binkert.org 668922Swilliam.wang@arm.com // create the master ports based on the number of connected ports 678922Swilliam.wang@arm.com for (size_t i = 0; i < p->port_master_connection_count; ++i) { 688922Swilliam.wang@arm.com master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i), 698922Swilliam.wang@arm.com this)); 708922Swilliam.wang@arm.com } 716876Ssteve.reinhardt@amd.com} 726876Ssteve.reinhardt@amd.com 737039Snate@binkert.orgvoid 747039Snate@binkert.orgRubyPort::init() 756882SBrad.Beckmann@amd.com{ 766882SBrad.Beckmann@amd.com assert(m_controller != NULL); 776882SBrad.Beckmann@amd.com m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 786882SBrad.Beckmann@amd.com} 796882SBrad.Beckmann@amd.com 808922Swilliam.wang@arm.comMasterPort & 818922Swilliam.wang@arm.comRubyPort::getMasterPort(const std::string &if_name, int idx) 826876Ssteve.reinhardt@amd.com{ 838922Swilliam.wang@arm.com if (if_name == "pio_port") { 848922Swilliam.wang@arm.com return pio_port; 858922Swilliam.wang@arm.com } 868922Swilliam.wang@arm.com 878839Sandreas.hansson@arm.com // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 888839Sandreas.hansson@arm.com // port 898922Swilliam.wang@arm.com if (if_name != "master") { 908922Swilliam.wang@arm.com // pass it along to our super class 918922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 928922Swilliam.wang@arm.com } else { 938922Swilliam.wang@arm.com if (idx >= static_cast<int>(master_ports.size())) { 948922Swilliam.wang@arm.com panic("RubyPort::getMasterPort: unknown index %d\n", idx); 958922Swilliam.wang@arm.com } 968839Sandreas.hansson@arm.com 978922Swilliam.wang@arm.com return *master_ports[idx]; 988839Sandreas.hansson@arm.com } 998922Swilliam.wang@arm.com} 1008839Sandreas.hansson@arm.com 1018922Swilliam.wang@arm.comSlavePort & 1028922Swilliam.wang@arm.comRubyPort::getSlavePort(const std::string &if_name, int idx) 1038922Swilliam.wang@arm.com{ 1048922Swilliam.wang@arm.com // used by the CPUs to connect the caches to the interconnect, and 1058922Swilliam.wang@arm.com // for the x86 case also the interrupt master 1068922Swilliam.wang@arm.com if (if_name != "slave") { 1078922Swilliam.wang@arm.com // pass it along to our super class 1088922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1098922Swilliam.wang@arm.com } else { 1108922Swilliam.wang@arm.com if (idx >= static_cast<int>(slave_ports.size())) { 1118922Swilliam.wang@arm.com panic("RubyPort::getSlavePort: unknown index %d\n", idx); 1128922Swilliam.wang@arm.com } 1138922Swilliam.wang@arm.com 1148922Swilliam.wang@arm.com return *slave_ports[idx]; 1157039Snate@binkert.org } 1166876Ssteve.reinhardt@amd.com} 1176882SBrad.Beckmann@amd.com 1187039Snate@binkert.orgRubyPort::PioPort::PioPort(const std::string &_name, 1196882SBrad.Beckmann@amd.com RubyPort *_port) 1208922Swilliam.wang@arm.com : QueuedMasterPort(_name, _port, queue), queue(*_port, *this), 1218922Swilliam.wang@arm.com ruby_port(_port) 1226882SBrad.Beckmann@amd.com{ 1238922Swilliam.wang@arm.com DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name); 1246882SBrad.Beckmann@amd.com} 1256882SBrad.Beckmann@amd.com 1268436SBrad.Beckmann@amd.comRubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port, 1278436SBrad.Beckmann@amd.com RubySystem *_system, bool _access_phys_mem) 1288922Swilliam.wang@arm.com : QueuedSlavePort(_name, _port, queue), queue(*_port, *this), 1298914Sandreas.hansson@arm.com ruby_port(_port), ruby_system(_system), 1308914Sandreas.hansson@arm.com _onRetryList(false), access_phys_mem(_access_phys_mem) 1316882SBrad.Beckmann@amd.com{ 1328922Swilliam.wang@arm.com DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name); 1336882SBrad.Beckmann@amd.com} 1346882SBrad.Beckmann@amd.com 1356882SBrad.Beckmann@amd.comTick 1366882SBrad.Beckmann@amd.comRubyPort::PioPort::recvAtomic(PacketPtr pkt) 1376882SBrad.Beckmann@amd.com{ 1386882SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvAtomic() not implemented!\n"); 1396882SBrad.Beckmann@amd.com return 0; 1406882SBrad.Beckmann@amd.com} 1416882SBrad.Beckmann@amd.com 1426882SBrad.Beckmann@amd.comTick 1436882SBrad.Beckmann@amd.comRubyPort::M5Port::recvAtomic(PacketPtr pkt) 1446882SBrad.Beckmann@amd.com{ 1456882SBrad.Beckmann@amd.com panic("RubyPort::M5Port::recvAtomic() not implemented!\n"); 1466882SBrad.Beckmann@amd.com return 0; 1476882SBrad.Beckmann@amd.com} 1486882SBrad.Beckmann@amd.com 1496882SBrad.Beckmann@amd.com 1506882SBrad.Beckmann@amd.combool 1516882SBrad.Beckmann@amd.comRubyPort::PioPort::recvTiming(PacketPtr pkt) 1526882SBrad.Beckmann@amd.com{ 1537039Snate@binkert.org // In FS mode, ruby memory will receive pio responses from devices 1547039Snate@binkert.org // and it must forward these responses back to the particular CPU. 1558161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr()); 1566882SBrad.Beckmann@amd.com 1576882SBrad.Beckmann@amd.com assert(pkt->isResponse()); 1586882SBrad.Beckmann@amd.com 1596882SBrad.Beckmann@amd.com // First we must retrieve the request port from the sender State 1607039Snate@binkert.org RubyPort::SenderState *senderState = 1616882SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 1626882SBrad.Beckmann@amd.com M5Port *port = senderState->port; 1636882SBrad.Beckmann@amd.com assert(port != NULL); 1647039Snate@binkert.org 1656882SBrad.Beckmann@amd.com // pop the sender state from the packet 1666882SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 1676882SBrad.Beckmann@amd.com delete senderState; 1687039Snate@binkert.org 1696882SBrad.Beckmann@amd.com port->sendTiming(pkt); 1707039Snate@binkert.org 1716882SBrad.Beckmann@amd.com return true; 1726882SBrad.Beckmann@amd.com} 1736882SBrad.Beckmann@amd.com 1746882SBrad.Beckmann@amd.combool 1756882SBrad.Beckmann@amd.comRubyPort::M5Port::recvTiming(PacketPtr pkt) 1766882SBrad.Beckmann@amd.com{ 1778161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 1787039Snate@binkert.org "Timing access caught for address %#x\n", pkt->getAddr()); 1796882SBrad.Beckmann@amd.com 1806882SBrad.Beckmann@amd.com //dsm: based on SimpleTimingPort::recvTiming(pkt); 1816882SBrad.Beckmann@amd.com 1827039Snate@binkert.org // The received packets should only be M5 requests, which should never 1837039Snate@binkert.org // get nacked. There used to be code to hanldle nacks here, but 1847039Snate@binkert.org // I'm pretty sure it didn't work correctly with the drain code, 1856882SBrad.Beckmann@amd.com // so that would need to be fixed if we ever added it back. 1866882SBrad.Beckmann@amd.com assert(pkt->isRequest()); 1876882SBrad.Beckmann@amd.com 1886882SBrad.Beckmann@amd.com if (pkt->memInhibitAsserted()) { 1896882SBrad.Beckmann@amd.com warn("memInhibitAsserted???"); 1906882SBrad.Beckmann@amd.com // snooper will supply based on copy of packet 1916882SBrad.Beckmann@amd.com // still target's responsibility to delete packet 1926882SBrad.Beckmann@amd.com delete pkt; 1936882SBrad.Beckmann@amd.com return true; 1946882SBrad.Beckmann@amd.com } 1956882SBrad.Beckmann@amd.com 1966922SBrad.Beckmann@amd.com // Save the port in the sender state object to be used later to 1976922SBrad.Beckmann@amd.com // route the response 1986922SBrad.Beckmann@amd.com pkt->senderState = new SenderState(this, pkt->senderState); 1996922SBrad.Beckmann@amd.com 2006882SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 2016882SBrad.Beckmann@amd.com // pio port. 2026882SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 2038851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 2048161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 2056922SBrad.Beckmann@amd.com "Request for address 0x%#x is assumed to be a pio request\n", 2066922SBrad.Beckmann@amd.com pkt->getAddr()); 2076882SBrad.Beckmann@amd.com 2088874Sandreas.hansson@arm.com return ruby_port->pio_port.sendNextCycle(pkt); 2096882SBrad.Beckmann@amd.com } 2106882SBrad.Beckmann@amd.com 2118615Snilay@cs.wisc.edu assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <= 2128615Snilay@cs.wisc.edu RubySystem::getBlockSizeBytes()); 2137906SBrad.Beckmann@amd.com 2146882SBrad.Beckmann@amd.com // Submit the ruby request 2158615Snilay@cs.wisc.edu RequestStatus requestStatus = ruby_port->makeRequest(pkt); 2167023SBrad.Beckmann@amd.com 2177550SBrad.Beckmann@amd.com // If the request successfully issued then we should return true. 2187023SBrad.Beckmann@amd.com // Otherwise, we need to delete the senderStatus we just created and return 2197023SBrad.Beckmann@amd.com // false. 2207550SBrad.Beckmann@amd.com if (requestStatus == RequestStatus_Issued) { 2218161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr()); 2226922SBrad.Beckmann@amd.com return true; 2236882SBrad.Beckmann@amd.com } 2247023SBrad.Beckmann@amd.com 2257910SBrad.Beckmann@amd.com // 2267910SBrad.Beckmann@amd.com // Unless one is using the ruby tester, record the stalled M5 port for 2277910SBrad.Beckmann@amd.com // later retry when the sequencer becomes free. 2287910SBrad.Beckmann@amd.com // 2297910SBrad.Beckmann@amd.com if (!ruby_port->m_usingRubyTester) { 2307910SBrad.Beckmann@amd.com ruby_port->addToRetryList(this); 2317910SBrad.Beckmann@amd.com } 2327910SBrad.Beckmann@amd.com 2338161SBrad.Beckmann@amd.com DPRINTF(RubyPort, 2347906SBrad.Beckmann@amd.com "Request for address %#x did not issue because %s\n", 2357039Snate@binkert.org pkt->getAddr(), RequestStatus_to_string(requestStatus)); 2367039Snate@binkert.org 2376922SBrad.Beckmann@amd.com SenderState* senderState = safe_cast<SenderState*>(pkt->senderState); 2386922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 2396922SBrad.Beckmann@amd.com delete senderState; 2406922SBrad.Beckmann@amd.com return false; 2416882SBrad.Beckmann@amd.com} 2426882SBrad.Beckmann@amd.com 2438436SBrad.Beckmann@amd.combool 2448436SBrad.Beckmann@amd.comRubyPort::M5Port::doFunctionalRead(PacketPtr pkt) 2458436SBrad.Beckmann@amd.com{ 2468436SBrad.Beckmann@amd.com Address address(pkt->getAddr()); 2478436SBrad.Beckmann@amd.com Address line_address(address); 2488436SBrad.Beckmann@amd.com line_address.makeLineAddress(); 2498436SBrad.Beckmann@amd.com 2508532SLisa.Hsu@amd.com AccessPermission access_perm = AccessPermission_NotPresent; 2518436SBrad.Beckmann@amd.com int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 2528436SBrad.Beckmann@amd.com 2538532SLisa.Hsu@amd.com DPRINTF(RubyPort, "Functional Read request for %s\n",address); 2548436SBrad.Beckmann@amd.com 2558532SLisa.Hsu@amd.com unsigned int num_ro = 0; 2568532SLisa.Hsu@amd.com unsigned int num_rw = 0; 2578532SLisa.Hsu@amd.com unsigned int num_busy = 0; 2588532SLisa.Hsu@amd.com unsigned int num_backing_store = 0; 2598532SLisa.Hsu@amd.com unsigned int num_invalid = 0; 2608532SLisa.Hsu@amd.com 2618532SLisa.Hsu@amd.com // In this loop we count the number of controllers that have the given 2628532SLisa.Hsu@amd.com // address in read only, read write and busy states. 2638532SLisa.Hsu@amd.com for (int i = 0; i < num_controllers; ++i) { 2648532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 2658532SLisa.Hsu@amd.com getAccessPermission(line_address); 2668532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Read_Only) 2678532SLisa.Hsu@amd.com num_ro++; 2688532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Read_Write) 2698532SLisa.Hsu@amd.com num_rw++; 2708532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Busy) 2718532SLisa.Hsu@amd.com num_busy++; 2728532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Backing_Store) 2738532SLisa.Hsu@amd.com // See RubySlicc_Exports.sm for details, but Backing_Store is meant 2748532SLisa.Hsu@amd.com // to represent blocks in memory *for Broadcast/Snooping protocols*, 2758532SLisa.Hsu@amd.com // where memory has no idea whether it has an exclusive copy of data 2768532SLisa.Hsu@amd.com // or not. 2778532SLisa.Hsu@amd.com num_backing_store++; 2788532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Invalid || 2798532SLisa.Hsu@amd.com access_perm == AccessPermission_NotPresent) 2808532SLisa.Hsu@amd.com num_invalid++; 2818532SLisa.Hsu@amd.com } 2828532SLisa.Hsu@amd.com assert(num_rw <= 1); 2838532SLisa.Hsu@amd.com 2848532SLisa.Hsu@amd.com uint8* data = pkt->getPtr<uint8_t>(true); 2858532SLisa.Hsu@amd.com unsigned int size_in_bytes = pkt->getSize(); 2868532SLisa.Hsu@amd.com unsigned startByte = address.getAddress() - line_address.getAddress(); 2878532SLisa.Hsu@amd.com 2888532SLisa.Hsu@amd.com // This if case is meant to capture what happens in a Broadcast/Snoop 2898532SLisa.Hsu@amd.com // protocol where the block does not exist in the cache hierarchy. You 2908532SLisa.Hsu@amd.com // only want to read from the Backing_Store memory if there is no copy in 2918532SLisa.Hsu@amd.com // the cache hierarchy, otherwise you want to try to read the RO or RW 2928532SLisa.Hsu@amd.com // copies existing in the cache hierarchy (covered by the else statement). 2938532SLisa.Hsu@amd.com // The reason is because the Backing_Store memory could easily be stale, if 2948532SLisa.Hsu@amd.com // there are copies floating around the cache hierarchy, so you want to read 2958532SLisa.Hsu@amd.com // it only if it's not in the cache hierarchy at all. 2968532SLisa.Hsu@amd.com if (num_invalid == (num_controllers - 1) && 2978532SLisa.Hsu@amd.com num_backing_store == 1) 2988436SBrad.Beckmann@amd.com { 2998532SLisa.Hsu@amd.com DPRINTF(RubyPort, "only copy in Backing_Store memory, read from it\n"); 3008532SLisa.Hsu@amd.com for (int i = 0; i < num_controllers; ++i) { 3018532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i] 3028532SLisa.Hsu@amd.com ->getAccessPermission(line_address); 3038532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Backing_Store) { 3048532SLisa.Hsu@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 3058436SBrad.Beckmann@amd.com ->getDataBlock(line_address); 3068436SBrad.Beckmann@amd.com 3078532SLisa.Hsu@amd.com DPRINTF(RubyPort, "reading from %s block %s\n", 3088532SLisa.Hsu@amd.com ruby_system->m_abs_cntrl_vec[i]->name(), block); 3098532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 3108532SLisa.Hsu@amd.com data[i] = block.getByte(i + startByte); 3118532SLisa.Hsu@amd.com } 3128532SLisa.Hsu@amd.com return true; 3138532SLisa.Hsu@amd.com } 3148532SLisa.Hsu@amd.com } 3158532SLisa.Hsu@amd.com } else { 3168532SLisa.Hsu@amd.com // In Broadcast/Snoop protocols, this covers if you know the block 3178532SLisa.Hsu@amd.com // exists somewhere in the caching hierarchy, then you want to read any 3188532SLisa.Hsu@amd.com // valid RO or RW block. In directory protocols, same thing, you want 3198532SLisa.Hsu@amd.com // to read any valid readable copy of the block. 3208532SLisa.Hsu@amd.com DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 3218532SLisa.Hsu@amd.com num_busy, num_ro, num_rw); 3228532SLisa.Hsu@amd.com // In this loop, we try to figure which controller has a read only or 3238532SLisa.Hsu@amd.com // a read write copy of the given address. Any valid copy would suffice 3248532SLisa.Hsu@amd.com // for a functional read. 3258532SLisa.Hsu@amd.com for(int i = 0;i < num_controllers;++i) { 3268532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i] 3278532SLisa.Hsu@amd.com ->getAccessPermission(line_address); 3288532SLisa.Hsu@amd.com if(access_perm == AccessPermission_Read_Only || 3298532SLisa.Hsu@amd.com access_perm == AccessPermission_Read_Write) 3308436SBrad.Beckmann@amd.com { 3318532SLisa.Hsu@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 3328532SLisa.Hsu@amd.com ->getDataBlock(line_address); 3338532SLisa.Hsu@amd.com 3348532SLisa.Hsu@amd.com DPRINTF(RubyPort, "reading from %s block %s\n", 3358532SLisa.Hsu@amd.com ruby_system->m_abs_cntrl_vec[i]->name(), block); 3368532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 3378532SLisa.Hsu@amd.com data[i] = block.getByte(i + startByte); 3388532SLisa.Hsu@amd.com } 3398532SLisa.Hsu@amd.com return true; 3408436SBrad.Beckmann@amd.com } 3418436SBrad.Beckmann@amd.com } 3428436SBrad.Beckmann@amd.com } 3438436SBrad.Beckmann@amd.com return false; 3448436SBrad.Beckmann@amd.com} 3458436SBrad.Beckmann@amd.com 3468436SBrad.Beckmann@amd.combool 3478436SBrad.Beckmann@amd.comRubyPort::M5Port::doFunctionalWrite(PacketPtr pkt) 3488436SBrad.Beckmann@amd.com{ 3498436SBrad.Beckmann@amd.com Address addr(pkt->getAddr()); 3508436SBrad.Beckmann@amd.com Address line_addr = line_address(addr); 3518532SLisa.Hsu@amd.com AccessPermission access_perm = AccessPermission_NotPresent; 3528436SBrad.Beckmann@amd.com int num_controllers = ruby_system->m_abs_cntrl_vec.size(); 3538436SBrad.Beckmann@amd.com 3548436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional Write request for %s\n",addr); 3558436SBrad.Beckmann@amd.com 3568436SBrad.Beckmann@amd.com unsigned int num_ro = 0; 3578436SBrad.Beckmann@amd.com unsigned int num_rw = 0; 3588436SBrad.Beckmann@amd.com unsigned int num_busy = 0; 3598532SLisa.Hsu@amd.com unsigned int num_backing_store = 0; 3608532SLisa.Hsu@amd.com unsigned int num_invalid = 0; 3618436SBrad.Beckmann@amd.com 3628436SBrad.Beckmann@amd.com // In this loop we count the number of controllers that have the given 3638436SBrad.Beckmann@amd.com // address in read only, read write and busy states. 3648532SLisa.Hsu@amd.com for(int i = 0;i < num_controllers;++i) { 3658532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 3668436SBrad.Beckmann@amd.com getAccessPermission(line_addr); 3678532SLisa.Hsu@amd.com if (access_perm == AccessPermission_Read_Only) 3688532SLisa.Hsu@amd.com num_ro++; 3698532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Read_Write) 3708532SLisa.Hsu@amd.com num_rw++; 3718532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Busy) 3728532SLisa.Hsu@amd.com num_busy++; 3738532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Backing_Store) 3748532SLisa.Hsu@amd.com // See RubySlicc_Exports.sm for details, but Backing_Store is meant 3758532SLisa.Hsu@amd.com // to represent blocks in memory *for Broadcast/Snooping protocols*, 3768532SLisa.Hsu@amd.com // where memory has no idea whether it has an exclusive copy of data 3778532SLisa.Hsu@amd.com // or not. 3788532SLisa.Hsu@amd.com num_backing_store++; 3798532SLisa.Hsu@amd.com else if (access_perm == AccessPermission_Invalid || 3808532SLisa.Hsu@amd.com access_perm == AccessPermission_NotPresent) 3818532SLisa.Hsu@amd.com num_invalid++; 3828436SBrad.Beckmann@amd.com } 3838436SBrad.Beckmann@amd.com 3848436SBrad.Beckmann@amd.com // If the number of read write copies is more than 1, then there is bug in 3858436SBrad.Beckmann@amd.com // coherence protocol. Otherwise, if all copies are in stable states, i.e. 3868436SBrad.Beckmann@amd.com // num_busy == 0, we update all the copies. If there is at least one copy 3878436SBrad.Beckmann@amd.com // in busy state, then we check if there is read write copy. If yes, then 3888532SLisa.Hsu@amd.com // also we let the access go through. Or, if there is no copy in the cache 3898532SLisa.Hsu@amd.com // hierarchy at all, we still want to do the write to the memory 3908532SLisa.Hsu@amd.com // (Backing_Store) instead of failing. 3918436SBrad.Beckmann@amd.com 3928436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n", 3938436SBrad.Beckmann@amd.com num_busy, num_ro, num_rw); 3948436SBrad.Beckmann@amd.com assert(num_rw <= 1); 3958532SLisa.Hsu@amd.com 3968532SLisa.Hsu@amd.com uint8* data = pkt->getPtr<uint8_t>(true); 3978532SLisa.Hsu@amd.com unsigned int size_in_bytes = pkt->getSize(); 3988532SLisa.Hsu@amd.com unsigned startByte = addr.getAddress() - line_addr.getAddress(); 3998532SLisa.Hsu@amd.com 4008532SLisa.Hsu@amd.com if ((num_busy == 0 && num_ro > 0) || num_rw == 1 || 4018532SLisa.Hsu@amd.com (num_invalid == (num_controllers - 1) && num_backing_store == 1)) 4028436SBrad.Beckmann@amd.com { 4038532SLisa.Hsu@amd.com for(int i = 0; i < num_controllers;++i) { 4048532SLisa.Hsu@amd.com access_perm = ruby_system->m_abs_cntrl_vec[i]-> 4058436SBrad.Beckmann@amd.com getAccessPermission(line_addr); 4068532SLisa.Hsu@amd.com if(access_perm == AccessPermission_Read_Only || 4078532SLisa.Hsu@amd.com access_perm == AccessPermission_Read_Write|| 4088532SLisa.Hsu@amd.com access_perm == AccessPermission_Maybe_Stale || 4098532SLisa.Hsu@amd.com access_perm == AccessPermission_Backing_Store) 4108436SBrad.Beckmann@amd.com { 4118436SBrad.Beckmann@amd.com DataBlock& block = ruby_system->m_abs_cntrl_vec[i] 4128436SBrad.Beckmann@amd.com ->getDataBlock(line_addr); 4138436SBrad.Beckmann@amd.com 4148436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "%s\n",block); 4158532SLisa.Hsu@amd.com for (unsigned i = 0; i < size_in_bytes; ++i) { 4168436SBrad.Beckmann@amd.com block.setByte(i + startByte, data[i]); 4178436SBrad.Beckmann@amd.com } 4188436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "%s\n",block); 4198436SBrad.Beckmann@amd.com } 4208436SBrad.Beckmann@amd.com } 4218436SBrad.Beckmann@amd.com return true; 4228436SBrad.Beckmann@amd.com } 4238436SBrad.Beckmann@amd.com return false; 4248436SBrad.Beckmann@amd.com} 4258436SBrad.Beckmann@amd.com 4268436SBrad.Beckmann@amd.comvoid 4278436SBrad.Beckmann@amd.comRubyPort::M5Port::recvFunctional(PacketPtr pkt) 4288436SBrad.Beckmann@amd.com{ 4298436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access caught for address %#x\n", 4308436SBrad.Beckmann@amd.com pkt->getAddr()); 4318436SBrad.Beckmann@amd.com 4328436SBrad.Beckmann@amd.com // Check for pio requests and directly send them to the dedicated 4338436SBrad.Beckmann@amd.com // pio port. 4348436SBrad.Beckmann@amd.com if (!isPhysMemAddress(pkt->getAddr())) { 4358851Sandreas.hansson@arm.com assert(ruby_port->pio_port.isConnected()); 4368436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n", 4378436SBrad.Beckmann@amd.com pkt->getAddr()); 4388436SBrad.Beckmann@amd.com panic("RubyPort::PioPort::recvFunctional() not implemented!\n"); 4398436SBrad.Beckmann@amd.com } 4408436SBrad.Beckmann@amd.com 4418436SBrad.Beckmann@amd.com assert(pkt->getAddr() + pkt->getSize() <= 4428436SBrad.Beckmann@amd.com line_address(Address(pkt->getAddr())).getAddress() + 4438436SBrad.Beckmann@amd.com RubySystem::getBlockSizeBytes()); 4448436SBrad.Beckmann@amd.com 4458436SBrad.Beckmann@amd.com bool accessSucceeded = false; 4468436SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 4478436SBrad.Beckmann@amd.com 4488436SBrad.Beckmann@amd.com // Do the functional access on ruby memory 4498436SBrad.Beckmann@amd.com if (pkt->isRead()) { 4508436SBrad.Beckmann@amd.com accessSucceeded = doFunctionalRead(pkt); 4518436SBrad.Beckmann@amd.com } else if (pkt->isWrite()) { 4528436SBrad.Beckmann@amd.com accessSucceeded = doFunctionalWrite(pkt); 4538436SBrad.Beckmann@amd.com } else { 4548436SBrad.Beckmann@amd.com panic("RubyPort: unsupported functional command %s\n", 4558436SBrad.Beckmann@amd.com pkt->cmdString()); 4568436SBrad.Beckmann@amd.com } 4578436SBrad.Beckmann@amd.com 4588436SBrad.Beckmann@amd.com // Unless the requester explicitly said otherwise, generate an error if 4598436SBrad.Beckmann@amd.com // the functional request failed 4608436SBrad.Beckmann@amd.com if (!accessSucceeded && !pkt->suppressFuncError()) { 4618436SBrad.Beckmann@amd.com fatal("Ruby functional %s failed for address %#x\n", 4628436SBrad.Beckmann@amd.com pkt->isWrite() ? "write" : "read", pkt->getAddr()); 4638436SBrad.Beckmann@amd.com } 4648436SBrad.Beckmann@amd.com 4658436SBrad.Beckmann@amd.com if (access_phys_mem) { 4668436SBrad.Beckmann@amd.com // The attached physmem contains the official version of data. 4678436SBrad.Beckmann@amd.com // The following command performs the real functional access. 4688436SBrad.Beckmann@amd.com // This line should be removed once Ruby supplies the official version 4698436SBrad.Beckmann@amd.com // of data. 4708923Sandreas.hansson@arm.com ruby_port->system->physmem->doFunctionalAccess(pkt); 4718436SBrad.Beckmann@amd.com } 4728436SBrad.Beckmann@amd.com 4738436SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 4748436SBrad.Beckmann@amd.com if (needsResponse) { 4758436SBrad.Beckmann@amd.com pkt->setFunctionalResponseStatus(accessSucceeded); 4768706Sandreas.hansson@arm.com 4778706Sandreas.hansson@arm.com // @todo There should not be a reverse call since the response is 4788706Sandreas.hansson@arm.com // communicated through the packet pointer 4798706Sandreas.hansson@arm.com // DPRINTF(RubyPort, "Sending packet back over port\n"); 4808706Sandreas.hansson@arm.com // sendFunctional(pkt); 4818436SBrad.Beckmann@amd.com } 4828436SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Functional access %s!\n", 4838436SBrad.Beckmann@amd.com accessSucceeded ? "successful":"failed"); 4848436SBrad.Beckmann@amd.com} 4858436SBrad.Beckmann@amd.com 4866882SBrad.Beckmann@amd.comvoid 4876922SBrad.Beckmann@amd.comRubyPort::ruby_hit_callback(PacketPtr pkt) 4886882SBrad.Beckmann@amd.com{ 4896922SBrad.Beckmann@amd.com // Retrieve the request port from the sender State 4907039Snate@binkert.org RubyPort::SenderState *senderState = 4916922SBrad.Beckmann@amd.com safe_cast<RubyPort::SenderState *>(pkt->senderState); 4926922SBrad.Beckmann@amd.com M5Port *port = senderState->port; 4936922SBrad.Beckmann@amd.com assert(port != NULL); 4947039Snate@binkert.org 4956922SBrad.Beckmann@amd.com // pop the sender state from the packet 4966922SBrad.Beckmann@amd.com pkt->senderState = senderState->saved; 4976922SBrad.Beckmann@amd.com delete senderState; 4986882SBrad.Beckmann@amd.com 4996882SBrad.Beckmann@amd.com port->hitCallback(pkt); 5007910SBrad.Beckmann@amd.com 5017910SBrad.Beckmann@amd.com // 5027910SBrad.Beckmann@amd.com // If we had to stall the M5Ports, wake them up because the sequencer 5037910SBrad.Beckmann@amd.com // likely has free resources now. 5047910SBrad.Beckmann@amd.com // 5057910SBrad.Beckmann@amd.com if (waitingOnSequencer) { 5068162SBrad.Beckmann@amd.com // 5078162SBrad.Beckmann@amd.com // Record the current list of ports to retry on a temporary list before 5088162SBrad.Beckmann@amd.com // calling sendRetry on those ports. sendRetry will cause an 5098162SBrad.Beckmann@amd.com // immediate retry, which may result in the ports being put back on the 5108162SBrad.Beckmann@amd.com // list. Therefore we want to clear the retryList before calling 5118162SBrad.Beckmann@amd.com // sendRetry. 5128162SBrad.Beckmann@amd.com // 5138162SBrad.Beckmann@amd.com std::list<M5Port*> curRetryList(retryList); 5148162SBrad.Beckmann@amd.com 5158162SBrad.Beckmann@amd.com retryList.clear(); 5168162SBrad.Beckmann@amd.com waitingOnSequencer = false; 5178162SBrad.Beckmann@amd.com 5188162SBrad.Beckmann@amd.com for (std::list<M5Port*>::iterator i = curRetryList.begin(); 5198162SBrad.Beckmann@amd.com i != curRetryList.end(); ++i) { 5208162SBrad.Beckmann@amd.com DPRINTF(RubyPort, 5217910SBrad.Beckmann@amd.com "Sequencer may now be free. SendRetry to port %s\n", 5227910SBrad.Beckmann@amd.com (*i)->name()); 5238162SBrad.Beckmann@amd.com (*i)->onRetryList(false); 5248162SBrad.Beckmann@amd.com (*i)->sendRetry(); 5257910SBrad.Beckmann@amd.com } 5267910SBrad.Beckmann@amd.com } 5278688Snilay@cs.wisc.edu 5288688Snilay@cs.wisc.edu testDrainComplete(); 5298688Snilay@cs.wisc.edu} 5308688Snilay@cs.wisc.edu 5318688Snilay@cs.wisc.eduvoid 5328688Snilay@cs.wisc.eduRubyPort::testDrainComplete() 5338688Snilay@cs.wisc.edu{ 5348688Snilay@cs.wisc.edu //If we weren't able to drain before, we might be able to now. 5358688Snilay@cs.wisc.edu if (drainEvent != NULL) { 5368688Snilay@cs.wisc.edu unsigned int drainCount = getDrainCount(drainEvent); 5378688Snilay@cs.wisc.edu DPRINTF(Config, "Drain count: %u\n", drainCount); 5388688Snilay@cs.wisc.edu if (drainCount == 0) { 5398688Snilay@cs.wisc.edu drainEvent->process(); 5408688Snilay@cs.wisc.edu // Clear the drain event once we're done with it. 5418688Snilay@cs.wisc.edu drainEvent = NULL; 5428688Snilay@cs.wisc.edu } 5438688Snilay@cs.wisc.edu } 5448688Snilay@cs.wisc.edu} 5458688Snilay@cs.wisc.edu 5468688Snilay@cs.wisc.eduunsigned int 5478688Snilay@cs.wisc.eduRubyPort::getDrainCount(Event *de) 5488688Snilay@cs.wisc.edu{ 5498688Snilay@cs.wisc.edu int count = 0; 5508688Snilay@cs.wisc.edu // 5518688Snilay@cs.wisc.edu // If the sequencer is not empty, then requests need to drain. 5528688Snilay@cs.wisc.edu // The outstandingCount is the number of requests outstanding and thus the 5538688Snilay@cs.wisc.edu // number of times M5's timing port will process the drain event. 5548688Snilay@cs.wisc.edu // 5558688Snilay@cs.wisc.edu count += outstandingCount(); 5568688Snilay@cs.wisc.edu 5578688Snilay@cs.wisc.edu DPRINTF(Config, "outstanding count %d\n", outstandingCount()); 5588688Snilay@cs.wisc.edu 5598688Snilay@cs.wisc.edu // To simplify the draining process, the sequencer's deadlock detection 5608688Snilay@cs.wisc.edu // event should have been descheduled. 5618688Snilay@cs.wisc.edu assert(isDeadlockEventScheduled() == false); 5628688Snilay@cs.wisc.edu 5638851Sandreas.hansson@arm.com if (pio_port.isConnected()) { 5648851Sandreas.hansson@arm.com count += pio_port.drain(de); 5658688Snilay@cs.wisc.edu DPRINTF(Config, "count after pio check %d\n", count); 5668688Snilay@cs.wisc.edu } 5678688Snilay@cs.wisc.edu 5688922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 5698922Swilliam.wang@arm.com count += (*p)->drain(de); 5708922Swilliam.wang@arm.com DPRINTF(Config, "count after slave port check %d\n", count); 5718922Swilliam.wang@arm.com } 5728922Swilliam.wang@arm.com 5738922Swilliam.wang@arm.com for (std::vector<PioPort*>::iterator p = master_ports.begin(); 5748922Swilliam.wang@arm.com p != master_ports.end(); ++p) { 5758922Swilliam.wang@arm.com count += (*p)->drain(de); 5768922Swilliam.wang@arm.com DPRINTF(Config, "count after master port check %d\n", count); 5778688Snilay@cs.wisc.edu } 5788688Snilay@cs.wisc.edu 5798688Snilay@cs.wisc.edu DPRINTF(Config, "final count %d\n", count); 5808688Snilay@cs.wisc.edu 5818688Snilay@cs.wisc.edu return count; 5828688Snilay@cs.wisc.edu} 5838688Snilay@cs.wisc.edu 5848688Snilay@cs.wisc.eduunsigned int 5858688Snilay@cs.wisc.eduRubyPort::drain(Event *de) 5868688Snilay@cs.wisc.edu{ 5878688Snilay@cs.wisc.edu if (isDeadlockEventScheduled()) { 5888688Snilay@cs.wisc.edu descheduleDeadlockEvent(); 5898688Snilay@cs.wisc.edu } 5908688Snilay@cs.wisc.edu 5918688Snilay@cs.wisc.edu int count = getDrainCount(de); 5928688Snilay@cs.wisc.edu 5938688Snilay@cs.wisc.edu // Set status 5948688Snilay@cs.wisc.edu if (count != 0) { 5958688Snilay@cs.wisc.edu drainEvent = de; 5968688Snilay@cs.wisc.edu 5978688Snilay@cs.wisc.edu changeState(SimObject::Draining); 5988688Snilay@cs.wisc.edu return count; 5998688Snilay@cs.wisc.edu } 6008688Snilay@cs.wisc.edu 6018688Snilay@cs.wisc.edu changeState(SimObject::Drained); 6028688Snilay@cs.wisc.edu return 0; 6036882SBrad.Beckmann@amd.com} 6046882SBrad.Beckmann@amd.com 6056882SBrad.Beckmann@amd.comvoid 6066882SBrad.Beckmann@amd.comRubyPort::M5Port::hitCallback(PacketPtr pkt) 6076882SBrad.Beckmann@amd.com{ 6086882SBrad.Beckmann@amd.com bool needsResponse = pkt->needsResponse(); 6096882SBrad.Beckmann@amd.com 6107550SBrad.Beckmann@amd.com // 6117915SBrad.Beckmann@amd.com // Unless specified at configuraiton, all responses except failed SC 6128184Ssomayeh@cs.wisc.edu // and Flush operations access M5 physical memory. 6137550SBrad.Beckmann@amd.com // 6147915SBrad.Beckmann@amd.com bool accessPhysMem = access_phys_mem; 6157550SBrad.Beckmann@amd.com 6167550SBrad.Beckmann@amd.com if (pkt->isLLSC()) { 6177550SBrad.Beckmann@amd.com if (pkt->isWrite()) { 6187550SBrad.Beckmann@amd.com if (pkt->req->getExtraData() != 0) { 6197550SBrad.Beckmann@amd.com // 6207550SBrad.Beckmann@amd.com // Successful SC packets convert to normal writes 6217550SBrad.Beckmann@amd.com // 6227550SBrad.Beckmann@amd.com pkt->convertScToWrite(); 6237550SBrad.Beckmann@amd.com } else { 6247550SBrad.Beckmann@amd.com // 6257550SBrad.Beckmann@amd.com // Failed SC packets don't access physical memory and thus 6267550SBrad.Beckmann@amd.com // the RubyPort itself must convert it to a response. 6277550SBrad.Beckmann@amd.com // 6287550SBrad.Beckmann@amd.com accessPhysMem = false; 6297550SBrad.Beckmann@amd.com } 6307550SBrad.Beckmann@amd.com } else { 6317550SBrad.Beckmann@amd.com // 6327550SBrad.Beckmann@amd.com // All LL packets convert to normal loads so that M5 PhysMem does 6337550SBrad.Beckmann@amd.com // not lock the blocks. 6347550SBrad.Beckmann@amd.com // 6357550SBrad.Beckmann@amd.com pkt->convertLlToRead(); 6367550SBrad.Beckmann@amd.com } 6377550SBrad.Beckmann@amd.com } 6388184Ssomayeh@cs.wisc.edu 6398184Ssomayeh@cs.wisc.edu // 6408184Ssomayeh@cs.wisc.edu // Flush requests don't access physical memory 6418184Ssomayeh@cs.wisc.edu // 6428184Ssomayeh@cs.wisc.edu if (pkt->isFlush()) { 6438184Ssomayeh@cs.wisc.edu accessPhysMem = false; 6448184Ssomayeh@cs.wisc.edu } 6458184Ssomayeh@cs.wisc.edu 6468161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 6476882SBrad.Beckmann@amd.com 6487550SBrad.Beckmann@amd.com if (accessPhysMem) { 6498923Sandreas.hansson@arm.com ruby_port->system->physmem->doAtomicAccess(pkt); 6508184Ssomayeh@cs.wisc.edu } else if (needsResponse) { 6517915SBrad.Beckmann@amd.com pkt->makeResponse(); 6527550SBrad.Beckmann@amd.com } 6536882SBrad.Beckmann@amd.com 6546882SBrad.Beckmann@amd.com // turn packet around to go back to requester if response expected 6556882SBrad.Beckmann@amd.com if (needsResponse) { 6568161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Sending packet back over port\n"); 6578874Sandreas.hansson@arm.com sendNextCycle(pkt); 6586882SBrad.Beckmann@amd.com } else { 6596882SBrad.Beckmann@amd.com delete pkt; 6606882SBrad.Beckmann@amd.com } 6618161SBrad.Beckmann@amd.com DPRINTF(RubyPort, "Hit callback done!\n"); 6626882SBrad.Beckmann@amd.com} 6636882SBrad.Beckmann@amd.com 6646882SBrad.Beckmann@amd.combool 6658874Sandreas.hansson@arm.comRubyPort::M5Port::sendNextCycle(PacketPtr pkt) 6666882SBrad.Beckmann@amd.com{ 6677558SBrad.Beckmann@amd.com //minimum latency, must be > 0 6688914Sandreas.hansson@arm.com queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 6696882SBrad.Beckmann@amd.com return true; 6706882SBrad.Beckmann@amd.com} 6716882SBrad.Beckmann@amd.com 6726882SBrad.Beckmann@amd.combool 6738874Sandreas.hansson@arm.comRubyPort::PioPort::sendNextCycle(PacketPtr pkt) 6746882SBrad.Beckmann@amd.com{ 6757558SBrad.Beckmann@amd.com //minimum latency, must be > 0 6768914Sandreas.hansson@arm.com queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock())); 6776882SBrad.Beckmann@amd.com return true; 6786882SBrad.Beckmann@amd.com} 6796882SBrad.Beckmann@amd.com 6808922Swilliam.wang@arm.comAddrRangeList 6818922Swilliam.wang@arm.comRubyPort::M5Port::getAddrRanges() 6828922Swilliam.wang@arm.com{ 6838922Swilliam.wang@arm.com // at the moment the assumption is that the master does not care 6848922Swilliam.wang@arm.com AddrRangeList ranges; 6858922Swilliam.wang@arm.com return ranges; 6868922Swilliam.wang@arm.com} 6878922Swilliam.wang@arm.com 6886882SBrad.Beckmann@amd.combool 6896882SBrad.Beckmann@amd.comRubyPort::M5Port::isPhysMemAddress(Addr addr) 6906882SBrad.Beckmann@amd.com{ 6918923Sandreas.hansson@arm.com return ruby_port->system->isMemory(addr); 6926882SBrad.Beckmann@amd.com} 6937909Shestness@cs.utexas.edu 6947909Shestness@cs.utexas.eduunsigned 6957909Shestness@cs.utexas.eduRubyPort::M5Port::deviceBlockSize() const 6967909Shestness@cs.utexas.edu{ 6977909Shestness@cs.utexas.edu return (unsigned) RubySystem::getBlockSizeBytes(); 6987909Shestness@cs.utexas.edu} 6998717Snilay@cs.wisc.edu 7008717Snilay@cs.wisc.eduvoid 7018717Snilay@cs.wisc.eduRubyPort::ruby_eviction_callback(const Address& address) 7028717Snilay@cs.wisc.edu{ 7038717Snilay@cs.wisc.edu DPRINTF(RubyPort, "Sending invalidations.\n"); 7048922Swilliam.wang@arm.com // should this really be using funcMasterId? 7058832SAli.Saidi@ARM.com Request req(address.getAddress(), 0, 0, Request::funcMasterId); 7068922Swilliam.wang@arm.com for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 7078922Swilliam.wang@arm.com if ((*p)->getMasterPort().isSnooping()) { 7088922Swilliam.wang@arm.com Packet *pkt = new Packet(&req, MemCmd::InvalidationReq, -1); 7098922Swilliam.wang@arm.com (*p)->sendNextCycle(pkt); 7108922Swilliam.wang@arm.com } 7118717Snilay@cs.wisc.edu } 7128717Snilay@cs.wisc.edu} 713